1 files changed, 9 insertions, 7 deletions

diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index bd77ef2d5ae9..91ad2070264d 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -339,7 +339,7 @@ static const struct clkops clkops_fixed = {
  * Uses the current prcm set to tell if a rate is valid.
  * You can go slower, but not faster within a given rate set.
  */
-long omap2_dpllcore_round_rate(unsigned long target_rate)
+static long omap2_dpllcore_round_rate(unsigned long target_rate)
 {
         u32 high, low, core_clk_src;
 
@@ -550,7 +550,9 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
 
                 /* Major subsystem dividers */
                 tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK;
-                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1);
+                cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD,
+                                 CM_CLKSEL1);
+
                 if (cpu_is_omap2430())
                         cm_write_mod_reg(prcm->cm_clksel_mdm,
                                          OMAP2430_MDM_MOD, CM_CLKSEL);
@@ -582,20 +584,20 @@ static struct clk_functions omap2_clk_functions = {
 
 static u32 omap2_get_apll_clkin(void)
 {
-        u32 aplls, sclk = 0;
+        u32 aplls, srate = 0;
 
         aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
         aplls &= OMAP24XX_APLLS_CLKIN_MASK;
         aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT;
 
         if (aplls == APLLS_CLKIN_19_2MHZ)
-                sclk = 19200000;
+                srate = 19200000;
         else if (aplls == APLLS_CLKIN_13MHZ)
-                sclk = 13000000;
+                srate = 13000000;
         else if (aplls == APLLS_CLKIN_12MHZ)
-                sclk = 12000000;
+                srate = 12000000;
 
-        return sclk;
+        return srate;
 }
 
 static u32 omap2_get_sysclkdiv(void)