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Diffstat (limited to 'arch/arm/mach-omap2/clock2430_data.c')
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index daf643928c26..b3895840dc41 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -386,7 +386,6 @@ static struct clk mpu_ck = { /* Control cpu */
386 .name = "mpu_ck", 386 .name = "mpu_ck",
387 .ops = &clkops_null, 387 .ops = &clkops_null,
388 .parent = &core_ck, 388 .parent = &core_ck,
389 .flags = DELAYED_APP,
390 .clkdm_name = "mpu_clkdm", 389 .clkdm_name = "mpu_clkdm",
391 .init = &omap2_init_clksel_parent, 390 .init = &omap2_init_clksel_parent,
392 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), 391 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
@@ -422,7 +421,6 @@ static struct clk dsp_fck = {
422 .name = "dsp_fck", 421 .name = "dsp_fck",
423 .ops = &clkops_omap2_dflt_wait, 422 .ops = &clkops_omap2_dflt_wait,
424 .parent = &core_ck, 423 .parent = &core_ck,
425 .flags = DELAYED_APP,
426 .clkdm_name = "dsp_clkdm", 424 .clkdm_name = "dsp_clkdm",
427 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), 425 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
428 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, 426 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
@@ -450,7 +448,6 @@ static struct clk dsp_irate_ick = {
450 .name = "dsp_irate_ick", 448 .name = "dsp_irate_ick",
451 .ops = &clkops_null, 449 .ops = &clkops_null,
452 .parent = &dsp_fck, 450 .parent = &dsp_fck,
453 .flags = DELAYED_APP,
454 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), 451 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
455 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, 452 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
456 .clksel = dsp_irate_ick_clksel, 453 .clksel = dsp_irate_ick_clksel,
@@ -501,7 +498,6 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
501 .name = "core_l3_ck", 498 .name = "core_l3_ck",
502 .ops = &clkops_null, 499 .ops = &clkops_null,
503 .parent = &core_ck, 500 .parent = &core_ck,
504 .flags = DELAYED_APP,
505 .clkdm_name = "core_l3_clkdm", 501 .clkdm_name = "core_l3_clkdm",
506 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 502 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
507 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, 503 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
@@ -527,7 +523,6 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */
527 .name = "usb_l4_ick", 523 .name = "usb_l4_ick",
528 .ops = &clkops_omap2_dflt_wait, 524 .ops = &clkops_omap2_dflt_wait,
529 .parent = &core_l3_ck, 525 .parent = &core_l3_ck,
530 .flags = DELAYED_APP,
531 .clkdm_name = "core_l4_clkdm", 526 .clkdm_name = "core_l4_clkdm",
532 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 527 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
533 .enable_bit = OMAP24XX_EN_USB_SHIFT, 528 .enable_bit = OMAP24XX_EN_USB_SHIFT,
@@ -559,14 +554,11 @@ static struct clk l4_ck = { /* used both as an ick and fck */
559 .name = "l4_ck", 554 .name = "l4_ck",
560 .ops = &clkops_null, 555 .ops = &clkops_null,
561 .parent = &core_l3_ck, 556 .parent = &core_l3_ck,
562 .flags = DELAYED_APP,
563 .clkdm_name = "core_l4_clkdm", 557 .clkdm_name = "core_l4_clkdm",
564 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), 558 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
565 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, 559 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
566 .clksel = l4_clksel, 560 .clksel = l4_clksel,
567 .recalc = &omap2_clksel_recalc, 561 .recalc = &omap2_clksel_recalc,
568 .round_rate = &omap2_clksel_round_rate,
569 .set_rate = &omap2_clksel_set_rate
570}; 562};
571 563
572/* 564/*
@@ -595,7 +587,6 @@ static struct clk ssi_ssr_sst_fck = {
595 .name = "ssi_fck", 587 .name = "ssi_fck",
596 .ops = &clkops_omap2_dflt_wait, 588 .ops = &clkops_omap2_dflt_wait,
597 .parent = &core_ck, 589 .parent = &core_ck,
598 .flags = DELAYED_APP,
599 .clkdm_name = "core_l3_clkdm", 590 .clkdm_name = "core_l3_clkdm",
600 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 591 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
601 .enable_bit = OMAP24XX_EN_SSI_SHIFT, 592 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
@@ -603,8 +594,6 @@ static struct clk ssi_ssr_sst_fck = {
603 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK, 594 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
604 .clksel = ssi_ssr_sst_fck_clksel, 595 .clksel = ssi_ssr_sst_fck_clksel,
605 .recalc = &omap2_clksel_recalc, 596 .recalc = &omap2_clksel_recalc,
606 .round_rate = &omap2_clksel_round_rate,
607 .set_rate = &omap2_clksel_set_rate
608}; 597};
609 598
610/* 599/*
@@ -659,7 +648,6 @@ static struct clk gfx_2d_fck = {
659 .name = "gfx_2d_fck", 648 .name = "gfx_2d_fck",
660 .ops = &clkops_omap2_dflt_wait, 649 .ops = &clkops_omap2_dflt_wait,
661 .parent = &core_l3_ck, 650 .parent = &core_l3_ck,
662 .flags = DELAYED_APP,
663 .clkdm_name = "gfx_clkdm", 651 .clkdm_name = "gfx_clkdm",
664 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), 652 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
665 .enable_bit = OMAP24XX_EN_2D_SHIFT, 653 .enable_bit = OMAP24XX_EN_2D_SHIFT,
@@ -703,7 +691,6 @@ static struct clk mdm_ick = { /* used both as a ick and fck */
703 .name = "mdm_ick", 691 .name = "mdm_ick",
704 .ops = &clkops_omap2_dflt_wait, 692 .ops = &clkops_omap2_dflt_wait,
705 .parent = &core_ck, 693 .parent = &core_ck,
706 .flags = DELAYED_APP,
707 .clkdm_name = "mdm_clkdm", 694 .clkdm_name = "mdm_clkdm",
708 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), 695 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
709 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, 696 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
@@ -772,7 +759,6 @@ static struct clk dss1_fck = {
772 .name = "dss1_fck", 759 .name = "dss1_fck",
773 .ops = &clkops_omap2_dflt, 760 .ops = &clkops_omap2_dflt,
774 .parent = &core_ck, /* Core or sys */ 761 .parent = &core_ck, /* Core or sys */
775 .flags = DELAYED_APP,
776 .clkdm_name = "dss_clkdm", 762 .clkdm_name = "dss_clkdm",
777 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 763 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
778 .enable_bit = OMAP24XX_EN_DSS1_SHIFT, 764 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
@@ -781,8 +767,6 @@ static struct clk dss1_fck = {
781 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK, 767 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
782 .clksel = dss1_fck_clksel, 768 .clksel = dss1_fck_clksel,
783 .recalc = &omap2_clksel_recalc, 769 .recalc = &omap2_clksel_recalc,
784 .round_rate = &omap2_clksel_round_rate,
785 .set_rate = &omap2_clksel_set_rate
786}; 770};
787 771
788static const struct clksel_rate dss2_fck_sys_rates[] = { 772static const struct clksel_rate dss2_fck_sys_rates[] = {
@@ -805,7 +789,6 @@ static struct clk dss2_fck = { /* Alt clk used in power management */
805 .name = "dss2_fck", 789 .name = "dss2_fck",
806 .ops = &clkops_omap2_dflt, 790 .ops = &clkops_omap2_dflt,
807 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ 791 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
808 .flags = DELAYED_APP,
809 .clkdm_name = "dss_clkdm", 792 .clkdm_name = "dss_clkdm",
810 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 793 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
811 .enable_bit = OMAP24XX_EN_DSS2_SHIFT, 794 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,