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-rw-r--r--arch/arm/mach-omap2/clock.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 9917f793c3b6..b40204837bd7 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -195,6 +195,10 @@ struct clksel {
195 * @enable_mask: mask of the DPLL mode bitfield in @control_reg 195 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
196 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate() 196 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
197 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate() 197 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
198 * @last_rounded_m4xen: cache of the last M4X result of
199 * omap4_dpll_regm4xen_round_rate()
200 * @last_rounded_lpmode: cache of the last lpmode result of
201 * omap4_dpll_lpmode_recalc()
198 * @max_multiplier: maximum valid non-bypass multiplier value (actual) 202 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
199 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate() 203 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
200 * @min_divider: minimum valid non-bypass divider value (actual) 204 * @min_divider: minimum valid non-bypass divider value (actual)
@@ -205,6 +209,8 @@ struct clksel {
205 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg 209 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
206 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg 210 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
207 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg 211 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
212 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
213 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
208 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg 214 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
209 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs 215 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
210 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs 216 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
@@ -233,6 +239,8 @@ struct dpll_data {
233 u32 enable_mask; 239 u32 enable_mask;
234 unsigned long last_rounded_rate; 240 unsigned long last_rounded_rate;
235 u16 last_rounded_m; 241 u16 last_rounded_m;
242 u8 last_rounded_m4xen;
243 u8 last_rounded_lpmode;
236 u16 max_multiplier; 244 u16 max_multiplier;
237 u8 last_rounded_n; 245 u8 last_rounded_n;
238 u8 min_divider; 246 u8 min_divider;
@@ -245,6 +253,8 @@ struct dpll_data {
245 u32 idlest_mask; 253 u32 idlest_mask;
246 u32 dco_mask; 254 u32 dco_mask;
247 u32 sddiv_mask; 255 u32 sddiv_mask;
256 u32 lpmode_mask;
257 u32 m4xen_mask;
248 u8 auto_recal_bit; 258 u8 auto_recal_bit;
249 u8 recal_en_bit; 259 u8 recal_en_bit;
250 u8 recal_st_bit; 260 u8 recal_st_bit;