1 files changed, 35 insertions, 8 deletions

diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 0d2f14c2dcce..d8620105c42a 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -28,16 +28,22 @@
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "cm-regbits-24xx.h"
 #include "sdrc.h"
 #include "sram.h"
 
 /* #define DOWN_VARIABLE_DPLL 1 */              /* Experimental */
 
+/*
+ * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx
+ * (currently defined as "dpll_ck" in the OMAP2xxx clock tree).  Set
+ * during dpll_ck init and used later by omap2xxx_clk_get_core_rate().
+ */
+static struct clk_hw_omap *dpll_core_ck;
+
 /**
  * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
- * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
  *
  * Returns the CORE_CLK rate.  CORE_CLK can have one of three rate
  * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
@@ -45,12 +51,14 @@
  * struct clk *dpll_ck, which is a composite clock of dpll_ck and
  * core_ck.
  */
-unsigned long omap2xxx_clk_get_core_rate(struct clk *clk)
+unsigned long omap2xxx_clk_get_core_rate(void)
 {
         long long core_clk;
         u32 v;
 
-        core_clk = omap2_get_dpll_rate(clk);
+        WARN_ON(!dpll_core_ck);
+
+        core_clk = omap2_get_dpll_rate(dpll_core_ck);
 
         v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         v &= OMAP24XX_CORE_CLK_SRC_MASK;
@@ -96,19 +104,22 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate)
 
 }
 
-unsigned long omap2_dpllcore_recalc(struct clk *clk)
+unsigned long omap2_dpllcore_recalc(struct clk_hw *hw,
+                                    unsigned long parent_rate)
 {
-        return omap2xxx_clk_get_core_rate(clk);
+        return omap2xxx_clk_get_core_rate();
 }
 
-int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
+int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
+                             unsigned long parent_rate)
 {
+        struct clk_hw_omap *clk = to_clk_hw_omap(hw);
         u32 cur_rate, low, mult, div, valid_rate, done_rate;
         u32 bypass = 0;
         struct prcm_config tmpset;
         const struct dpll_data *dd;
 
-        cur_rate = omap2xxx_clk_get_core_rate(dclk);
+        cur_rate = omap2xxx_clk_get_core_rate();
         mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
         mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
@@ -169,3 +180,19 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
         return 0;
 }
 
+/**
+ * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck
+ * @clk: struct clk *dpll_ck
+ *
+ * Store a local copy of @clk in dpll_core_ck so other code can query
+ * the core rate without having to clk_get(), which can sleep.  Must
+ * only be called once.  No return value.  XXX If the clock
+ * registration process is ever changed such that dpll_ck is no longer
+ * statically defined, this code may need to change to increment some
+ * kind of use count on dpll_ck.
+ */
+void omap2xxx_clkt_dpllcore_init(struct clk_hw *hw)
+{
+        WARN(dpll_core_ck, "dpll_core_ck already set - should never happen");
+        dpll_core_ck = to_clk_hw_omap(hw);
+}