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-rw-r--r--arch/arm/mach-omap1/clock.c508
1 files changed, 105 insertions, 403 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 436eed22801b..e0aec1007a0d 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap1/clock.c 2 * linux/arch/arm/mach-omap1/clock.c
3 * 3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation 4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * 6 *
7 * Modified to use omap shared clock framework by 7 * Modified to use omap shared clock framework by
@@ -22,152 +22,29 @@
22#include <asm/mach-types.h> 22#include <asm/mach-types.h>
23#include <asm/clkdev.h> 23#include <asm/clkdev.h>
24 24
25#include <mach/cpu.h> 25#include <plat/cpu.h>
26#include <mach/usb.h> 26#include <plat/usb.h>
27#include <mach/clock.h> 27#include <plat/clock.h>
28#include <mach/sram.h> 28#include <plat/sram.h>
29 29#include <plat/clkdev_omap.h>
30static const struct clkops clkops_generic;
31static const struct clkops clkops_uart;
32static const struct clkops clkops_dspck;
33 30
34#include "clock.h" 31#include "clock.h"
35 32#include "opp.h"
36static int clk_omap1_dummy_enable(struct clk *clk)
37{
38 return 0;
39}
40
41static void clk_omap1_dummy_disable(struct clk *clk)
42{
43}
44
45static const struct clkops clkops_dummy = {
46 .enable = clk_omap1_dummy_enable,
47 .disable = clk_omap1_dummy_disable,
48};
49
50static struct clk dummy_ck = {
51 .name = "dummy",
52 .ops = &clkops_dummy,
53 .flags = RATE_FIXED,
54};
55
56struct omap_clk {
57 u32 cpu;
58 struct clk_lookup lk;
59};
60
61#define CLK(dev, con, ck, cp) \
62 { \
63 .cpu = cp, \
64 .lk = { \
65 .dev_id = dev, \
66 .con_id = con, \
67 .clk = ck, \
68 }, \
69 }
70
71#define CK_310 (1 << 0)
72#define CK_730 (1 << 1)
73#define CK_1510 (1 << 2)
74#define CK_16XX (1 << 3)
75
76static struct omap_clk omap_clks[] = {
77 /* non-ULPD clocks */
78 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310),
79 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310),
80 /* CK_GEN1 clocks */
81 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
82 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
83 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
84 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
85 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
86 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
87 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
88 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
89 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
90 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
91 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
92 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
93 /* CK_GEN2 clocks */
94 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
95 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
96 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
97 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
98 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
99 /* CK_GEN3 clocks */
100 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730),
101 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
102 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX),
103 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
104 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
105 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
106 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
107 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310),
108 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
109 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
110 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
111 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730),
112 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
113 /* ULPD clocks */
114 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
115 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
116 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
117 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
118 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
119 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
120 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
121 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
122 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
123 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
124 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
125 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
126 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
127 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
128 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
129 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
130 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
131 /* Virtual clocks */
132 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
133 CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310),
134 CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
135 CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310),
136 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
137 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
138 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
139 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
140 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
141 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
142 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
143 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
144 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
145 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
146};
147
148static int omap1_clk_enable_generic(struct clk * clk);
149static int omap1_clk_enable(struct clk *clk);
150static void omap1_clk_disable_generic(struct clk * clk);
151static void omap1_clk_disable(struct clk *clk);
152 33
153__u32 arm_idlect1_mask; 34__u32 arm_idlect1_mask;
35struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
154 36
155/*------------------------------------------------------------------------- 37/*-------------------------------------------------------------------------
156 * Omap1 specific clock functions 38 * Omap1 specific clock functions
157 *-------------------------------------------------------------------------*/ 39 *-------------------------------------------------------------------------*/
158 40
159static unsigned long omap1_watchdog_recalc(struct clk *clk) 41unsigned long omap1_uart_recalc(struct clk *clk)
160{
161 return clk->parent->rate / 14;
162}
163
164static unsigned long omap1_uart_recalc(struct clk *clk)
165{ 42{
166 unsigned int val = __raw_readl(clk->enable_reg); 43 unsigned int val = __raw_readl(clk->enable_reg);
167 return val & clk->enable_bit ? 48000000 : 12000000; 44 return val & clk->enable_bit ? 48000000 : 12000000;
168} 45}
169 46
170static unsigned long omap1_sossi_recalc(struct clk *clk) 47unsigned long omap1_sossi_recalc(struct clk *clk)
171{ 48{
172 u32 div = omap_readl(MOD_CONF_CTRL_1); 49 u32 div = omap_readl(MOD_CONF_CTRL_1);
173 50
@@ -177,64 +54,6 @@ static unsigned long omap1_sossi_recalc(struct clk *clk)
177 return clk->parent->rate / div; 54 return clk->parent->rate / div;
178} 55}
179 56
180static int omap1_clk_enable_dsp_domain(struct clk *clk)
181{
182 int retval;
183
184 retval = omap1_clk_enable(&api_ck.clk);
185 if (!retval) {
186 retval = omap1_clk_enable_generic(clk);
187 omap1_clk_disable(&api_ck.clk);
188 }
189
190 return retval;
191}
192
193static void omap1_clk_disable_dsp_domain(struct clk *clk)
194{
195 if (omap1_clk_enable(&api_ck.clk) == 0) {
196 omap1_clk_disable_generic(clk);
197 omap1_clk_disable(&api_ck.clk);
198 }
199}
200
201static const struct clkops clkops_dspck = {
202 .enable = &omap1_clk_enable_dsp_domain,
203 .disable = &omap1_clk_disable_dsp_domain,
204};
205
206static int omap1_clk_enable_uart_functional(struct clk *clk)
207{
208 int ret;
209 struct uart_clk *uclk;
210
211 ret = omap1_clk_enable_generic(clk);
212 if (ret == 0) {
213 /* Set smart idle acknowledgement mode */
214 uclk = (struct uart_clk *)clk;
215 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
216 uclk->sysc_addr);
217 }
218
219 return ret;
220}
221
222static void omap1_clk_disable_uart_functional(struct clk *clk)
223{
224 struct uart_clk *uclk;
225
226 /* Set force idle acknowledgement mode */
227 uclk = (struct uart_clk *)clk;
228 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
229
230 omap1_clk_disable_generic(clk);
231}
232
233static const struct clkops clkops_uart = {
234 .enable = &omap1_clk_enable_uart_functional,
235 .disable = &omap1_clk_disable_uart_functional,
236};
237
238static void omap1_clk_allow_idle(struct clk *clk) 57static void omap1_clk_allow_idle(struct clk *clk)
239{ 58{
240 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; 59 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
@@ -342,7 +161,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate)
342 return dsor_exp; 161 return dsor_exp;
343} 162}
344 163
345static unsigned long omap1_ckctl_recalc(struct clk *clk) 164unsigned long omap1_ckctl_recalc(struct clk *clk)
346{ 165{
347 /* Calculate divisor encoded as 2-bit exponent */ 166 /* Calculate divisor encoded as 2-bit exponent */
348 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); 167 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
@@ -350,7 +169,7 @@ static unsigned long omap1_ckctl_recalc(struct clk *clk)
350 return clk->parent->rate / dsor; 169 return clk->parent->rate / dsor;
351} 170}
352 171
353static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) 172unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
354{ 173{
355 int dsor; 174 int dsor;
356 175
@@ -361,28 +180,29 @@ static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
361 * Note that DSP_CKCTL virt addr = phys addr, so 180 * Note that DSP_CKCTL virt addr = phys addr, so
362 * we must use __raw_readw() instead of omap_readw(). 181 * we must use __raw_readw() instead of omap_readw().
363 */ 182 */
364 omap1_clk_enable(&api_ck.clk); 183 omap1_clk_enable(api_ck_p);
365 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); 184 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
366 omap1_clk_disable(&api_ck.clk); 185 omap1_clk_disable(api_ck_p);
367 186
368 return clk->parent->rate / dsor; 187 return clk->parent->rate / dsor;
369} 188}
370 189
371/* MPU virtual clock functions */ 190/* MPU virtual clock functions */
372static int omap1_select_table_rate(struct clk * clk, unsigned long rate) 191int omap1_select_table_rate(struct clk *clk, unsigned long rate)
373{ 192{
374 /* Find the highest supported frequency <= rate and switch to it */ 193 /* Find the highest supported frequency <= rate and switch to it */
375 struct mpu_rate * ptr; 194 struct mpu_rate * ptr;
195 unsigned long dpll1_rate, ref_rate;
376 196
377 if (clk != &virtual_ck_mpu) 197 dpll1_rate = ck_dpll1_p->rate;
378 return -EINVAL; 198 ref_rate = ck_ref_p->rate;
379 199
380 for (ptr = rate_table; ptr->rate; ptr++) { 200 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
381 if (ptr->xtal != ck_ref.rate) 201 if (ptr->xtal != ref_rate)
382 continue; 202 continue;
383 203
384 /* DPLL1 cannot be reprogrammed without risking system crash */ 204 /* DPLL1 cannot be reprogrammed without risking system crash */
385 if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) 205 if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
386 continue; 206 continue;
387 207
388 /* Can check only after xtal frequency check */ 208 /* Can check only after xtal frequency check */
@@ -398,16 +218,18 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
398 * Reprogramming the DPLL is tricky, it must be done from SRAM. 218 * Reprogramming the DPLL is tricky, it must be done from SRAM.
399 * (on 730, bit 13 must always be 1) 219 * (on 730, bit 13 must always be 1)
400 */ 220 */
401 if (cpu_is_omap730()) 221 if (cpu_is_omap7xx())
402 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); 222 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
403 else 223 else
404 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); 224 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
405 225
406 ck_dpll1.rate = ptr->pll_rate; 226 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
227 ck_dpll1_p->rate = ptr->pll_rate;
228
407 return 0; 229 return 0;
408} 230}
409 231
410static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) 232int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
411{ 233{
412 int dsor_exp; 234 int dsor_exp;
413 u16 regval; 235 u16 regval;
@@ -427,7 +249,7 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
427 return 0; 249 return 0;
428} 250}
429 251
430static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) 252long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
431{ 253{
432 int dsor_exp = calc_dsor_exp(clk, rate); 254 int dsor_exp = calc_dsor_exp(clk, rate);
433 if (dsor_exp < 0) 255 if (dsor_exp < 0)
@@ -437,7 +259,7 @@ static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
437 return clk->parent->rate / (1 << dsor_exp); 259 return clk->parent->rate / (1 << dsor_exp);
438} 260}
439 261
440static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) 262int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
441{ 263{
442 int dsor_exp; 264 int dsor_exp;
443 u16 regval; 265 u16 regval;
@@ -457,19 +279,19 @@ static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
457 return 0; 279 return 0;
458} 280}
459 281
460static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) 282long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
461{ 283{
462 /* Find the highest supported frequency <= rate */ 284 /* Find the highest supported frequency <= rate */
463 struct mpu_rate * ptr; 285 struct mpu_rate * ptr;
464 long highest_rate; 286 long highest_rate;
287 unsigned long ref_rate;
465 288
466 if (clk != &virtual_ck_mpu) 289 ref_rate = ck_ref_p->rate;
467 return -EINVAL;
468 290
469 highest_rate = -EINVAL; 291 highest_rate = -EINVAL;
470 292
471 for (ptr = rate_table; ptr->rate; ptr++) { 293 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
472 if (ptr->xtal != ck_ref.rate) 294 if (ptr->xtal != ref_rate)
473 continue; 295 continue;
474 296
475 highest_rate = ptr->rate; 297 highest_rate = ptr->rate;
@@ -504,8 +326,8 @@ static unsigned calc_ext_dsor(unsigned long rate)
504 return dsor; 326 return dsor;
505} 327}
506 328
507/* Only needed on 1510 */ 329/* XXX Only needed on 1510 */
508static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) 330int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
509{ 331{
510 unsigned int val; 332 unsigned int val;
511 333
@@ -523,7 +345,7 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
523} 345}
524 346
525/* External clock (MCLK & BCLK) functions */ 347/* External clock (MCLK & BCLK) functions */
526static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) 348int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
527{ 349{
528 unsigned dsor; 350 unsigned dsor;
529 __u16 ratio_bits; 351 __u16 ratio_bits;
@@ -541,7 +363,7 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
541 return 0; 363 return 0;
542} 364}
543 365
544static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) 366int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
545{ 367{
546 u32 l; 368 u32 l;
547 int div; 369 int div;
@@ -564,12 +386,12 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
564 return 0; 386 return 0;
565} 387}
566 388
567static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) 389long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
568{ 390{
569 return 96000000 / calc_ext_dsor(rate); 391 return 96000000 / calc_ext_dsor(rate);
570} 392}
571 393
572static void omap1_init_ext_clk(struct clk * clk) 394void omap1_init_ext_clk(struct clk *clk)
573{ 395{
574 unsigned dsor; 396 unsigned dsor;
575 __u16 ratio_bits; 397 __u16 ratio_bits;
@@ -587,7 +409,7 @@ static void omap1_init_ext_clk(struct clk * clk)
587 clk-> rate = 96000000 / dsor; 409 clk-> rate = 96000000 / dsor;
588} 410}
589 411
590static int omap1_clk_enable(struct clk *clk) 412int omap1_clk_enable(struct clk *clk)
591{ 413{
592 int ret = 0; 414 int ret = 0;
593 415
@@ -615,7 +437,7 @@ err:
615 return ret; 437 return ret;
616} 438}
617 439
618static void omap1_clk_disable(struct clk *clk) 440void omap1_clk_disable(struct clk *clk)
619{ 441{
620 if (clk->usecount > 0 && !(--clk->usecount)) { 442 if (clk->usecount > 0 && !(--clk->usecount)) {
621 clk->ops->disable(clk); 443 clk->ops->disable(clk);
@@ -670,23 +492,78 @@ static void omap1_clk_disable_generic(struct clk *clk)
670 } 492 }
671} 493}
672 494
673static const struct clkops clkops_generic = { 495const struct clkops clkops_generic = {
674 .enable = &omap1_clk_enable_generic, 496 .enable = omap1_clk_enable_generic,
675 .disable = &omap1_clk_disable_generic, 497 .disable = omap1_clk_disable_generic,
498};
499
500static int omap1_clk_enable_dsp_domain(struct clk *clk)
501{
502 int retval;
503
504 retval = omap1_clk_enable(api_ck_p);
505 if (!retval) {
506 retval = omap1_clk_enable_generic(clk);
507 omap1_clk_disable(api_ck_p);
508 }
509
510 return retval;
511}
512
513static void omap1_clk_disable_dsp_domain(struct clk *clk)
514{
515 if (omap1_clk_enable(api_ck_p) == 0) {
516 omap1_clk_disable_generic(clk);
517 omap1_clk_disable(api_ck_p);
518 }
519}
520
521const struct clkops clkops_dspck = {
522 .enable = omap1_clk_enable_dsp_domain,
523 .disable = omap1_clk_disable_dsp_domain,
676}; 524};
677 525
678static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) 526static int omap1_clk_enable_uart_functional(struct clk *clk)
527{
528 int ret;
529 struct uart_clk *uclk;
530
531 ret = omap1_clk_enable_generic(clk);
532 if (ret == 0) {
533 /* Set smart idle acknowledgement mode */
534 uclk = (struct uart_clk *)clk;
535 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
536 uclk->sysc_addr);
537 }
538
539 return ret;
540}
541
542static void omap1_clk_disable_uart_functional(struct clk *clk)
679{ 543{
680 if (clk->flags & RATE_FIXED) 544 struct uart_clk *uclk;
681 return clk->rate; 545
546 /* Set force idle acknowledgement mode */
547 uclk = (struct uart_clk *)clk;
548 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
549
550 omap1_clk_disable_generic(clk);
551}
552
553const struct clkops clkops_uart = {
554 .enable = omap1_clk_enable_uart_functional,
555 .disable = omap1_clk_disable_uart_functional,
556};
682 557
558long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
559{
683 if (clk->round_rate != NULL) 560 if (clk->round_rate != NULL)
684 return clk->round_rate(clk, rate); 561 return clk->round_rate(clk, rate);
685 562
686 return clk->rate; 563 return clk->rate;
687} 564}
688 565
689static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) 566int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
690{ 567{
691 int ret = -EINVAL; 568 int ret = -EINVAL;
692 569
@@ -701,7 +578,7 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
701 578
702#ifdef CONFIG_OMAP_RESET_CLOCKS 579#ifdef CONFIG_OMAP_RESET_CLOCKS
703 580
704static void __init omap1_clk_disable_unused(struct clk *clk) 581void __init omap1_clk_disable_unused(struct clk *clk)
705{ 582{
706 __u32 regval32; 583 __u32 regval32;
707 584
@@ -722,184 +599,9 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
722 if ((regval32 & (1 << clk->enable_bit)) == 0) 599 if ((regval32 & (1 << clk->enable_bit)) == 0)
723 return; 600 return;
724 601
725 /* FIXME: This clock seems to be necessary but no-one
726 * has asked for its activation. */
727 if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */
728 || clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */
729 || clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */
730 ) {
731 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
732 clk->name);
733 return;
734 }
735
736 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); 602 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
737 clk->ops->disable(clk); 603 clk->ops->disable(clk);
738 printk(" done\n"); 604 printk(" done\n");
739} 605}
740 606
741#else
742#define omap1_clk_disable_unused NULL
743#endif
744
745static struct clk_functions omap1_clk_functions = {
746 .clk_enable = omap1_clk_enable,
747 .clk_disable = omap1_clk_disable,
748 .clk_round_rate = omap1_clk_round_rate,
749 .clk_set_rate = omap1_clk_set_rate,
750 .clk_disable_unused = omap1_clk_disable_unused,
751};
752
753int __init omap1_clk_init(void)
754{
755 struct omap_clk *c;
756 const struct omap_clock_config *info;
757 int crystal_type = 0; /* Default 12 MHz */
758 u32 reg, cpu_mask;
759
760#ifdef CONFIG_DEBUG_LL
761 /* Resets some clocks that may be left on from bootloader,
762 * but leaves serial clocks on.
763 */
764 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
765#endif
766
767 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
768 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
769 omap_writew(reg, SOFT_REQ_REG);
770 if (!cpu_is_omap15xx())
771 omap_writew(0, SOFT_REQ_REG2);
772
773 clk_init(&omap1_clk_functions);
774
775 /* By default all idlect1 clocks are allowed to idle */
776 arm_idlect1_mask = ~0;
777
778 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
779 clk_preinit(c->lk.clk);
780
781 cpu_mask = 0;
782 if (cpu_is_omap16xx())
783 cpu_mask |= CK_16XX;
784 if (cpu_is_omap1510())
785 cpu_mask |= CK_1510;
786 if (cpu_is_omap730())
787 cpu_mask |= CK_730;
788 if (cpu_is_omap310())
789 cpu_mask |= CK_310;
790
791 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
792 if (c->cpu & cpu_mask) {
793 clkdev_add(&c->lk);
794 clk_register(c->lk.clk);
795 }
796
797 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
798 if (info != NULL) {
799 if (!cpu_is_omap15xx())
800 crystal_type = info->system_clock_type;
801 }
802
803#if defined(CONFIG_ARCH_OMAP730)
804 ck_ref.rate = 13000000;
805#elif defined(CONFIG_ARCH_OMAP16XX)
806 if (crystal_type == 2)
807 ck_ref.rate = 19200000;
808#endif 607#endif
809
810 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
811 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
812 omap_readw(ARM_CKCTL));
813
814 /* We want to be in syncronous scalable mode */
815 omap_writew(0x1000, ARM_SYSST);
816
817#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
818 /* Use values set by bootloader. Determine PLL rate and recalculate
819 * dependent clocks as if kernel had changed PLL or divisors.
820 */
821 {
822 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
823
824 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
825 if (pll_ctl_val & 0x10) {
826 /* PLL enabled, apply multiplier and divisor */
827 if (pll_ctl_val & 0xf80)
828 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
829 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
830 } else {
831 /* PLL disabled, apply bypass divisor */
832 switch (pll_ctl_val & 0xc) {
833 case 0:
834 break;
835 case 0x4:
836 ck_dpll1.rate /= 2;
837 break;
838 default:
839 ck_dpll1.rate /= 4;
840 break;
841 }
842 }
843 }
844#else
845 /* Find the highest supported frequency and enable it */
846 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
847 printk(KERN_ERR "System frequencies not set. Check your config.\n");
848 /* Guess sane values (60MHz) */
849 omap_writew(0x2290, DPLL_CTL);
850 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
851 ck_dpll1.rate = 60000000;
852 }
853#endif
854 propagate_rate(&ck_dpll1);
855 /* Cache rates for clocks connected to ck_ref (not dpll1) */
856 propagate_rate(&ck_ref);
857 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
858 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
859 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
860 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
861 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
862
863#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
864 /* Select slicer output as OMAP input clock */
865 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
866#endif
867
868 /* Amstrad Delta wants BCLK high when inactive */
869 if (machine_is_ams_delta())
870 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
871 (1 << SDW_MCLK_INV_BIT),
872 ULPD_CLOCK_CTRL);
873
874 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
875 /* (on 730, bit 13 must not be cleared) */
876 if (cpu_is_omap730())
877 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
878 else
879 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
880
881 /* Put DSP/MPUI into reset until needed */
882 omap_writew(0, ARM_RSTCT1);
883 omap_writew(1, ARM_RSTCT2);
884 omap_writew(0x400, ARM_IDLECT1);
885
886 /*
887 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
888 * of the ARM_IDLECT2 register must be set to zero. The power-on
889 * default value of this bit is one.
890 */
891 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
892
893 /*
894 * Only enable those clocks we will need, let the drivers
895 * enable other clocks as necessary
896 */
897 clk_enable(&armper_ck.clk);
898 clk_enable(&armxor_ck.clk);
899 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
900
901 if (cpu_is_omap15xx())
902 clk_enable(&arm_gpio_ck);
903
904 return 0;
905}
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-25 13:41:24 -0400