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-rw-r--r--arch/arm/mach-netx/generic.c2
-rw-r--r--arch/arm/mach-netx/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-netx/include/mach/io.h28
-rw-r--r--arch/arm/mach-netx/include/mach/netx-regs.h16
4 files changed, 10 insertions, 38 deletions
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 59e67979f197..aa627465d914 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -168,7 +168,7 @@ void __init netx_init_irq(void)
168{ 168{
169 int irq; 169 int irq;
170 170
171 vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); 171 vic_init(io_p2v(NETX_PA_VIC), 0, ~0, 0);
172 172
173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { 173 for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
174 irq_set_chip_and_handler(irq, &netx_hif_chip, 174 irq_set_chip_and_handler(irq, &netx_hif_chip,
diff --git a/arch/arm/mach-netx/include/mach/hardware.h b/arch/arm/mach-netx/include/mach/hardware.h
index 517a2bd37842..b661af2f2145 100644
--- a/arch/arm/mach-netx/include/mach/hardware.h
+++ b/arch/arm/mach-netx/include/mach/hardware.h
@@ -33,7 +33,7 @@
33#define XMAC_MEM_SIZE 0x1000 33#define XMAC_MEM_SIZE 0x1000
34#define SRAM_MEM_SIZE 0x8000 34#define SRAM_MEM_SIZE 0x8000
35 35
36#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT) 36#define io_p2v(x) IOMEM((x) - NETX_IO_PHYS + NETX_IO_VIRT)
37#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS) 37#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
38 38
39#endif 39#endif
diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h
deleted file mode 100644
index c3921cb3b6a6..000000000000
--- a/arch/arm/mach-netx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-netx/include/mach/io.h
3 *
4 * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARM_ARCH_IO_H
21#define __ASM_ARM_ARCH_IO_H
22
23#define IO_SPACE_LIMIT 0xffffffff
24
25#define __io(a) __typesafe_io(a)
26#define __mem_pci(a) (a)
27
28#endif
diff --git a/arch/arm/mach-netx/include/mach/netx-regs.h b/arch/arm/mach-netx/include/mach/netx-regs.h
index 5a03e7ccb01a..fdde22b58ac3 100644
--- a/arch/arm/mach-netx/include/mach/netx-regs.h
+++ b/arch/arm/mach-netx/include/mach/netx-regs.h
@@ -115,7 +115,7 @@
115 *********************************/ 115 *********************************/
116 116
117/* Registers */ 117/* Registers */
118#define NETX_SYSTEM_REG(ofs) __io(NETX_VA_SYSTEM + (ofs)) 118#define NETX_SYSTEM_REG(ofs) IOMEM(NETX_VA_SYSTEM + (ofs))
119#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00) 119#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
120#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04) 120#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
121#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08) 121#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
@@ -185,7 +185,7 @@
185 *******************************/ 185 *******************************/
186 186
187/* Registers */ 187/* Registers */
188#define NETX_GPIO_REG(ofs) __io(NETX_VA_GPIO + (ofs)) 188#define NETX_GPIO_REG(ofs) IOMEM(NETX_VA_GPIO + (ofs))
189#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2)) 189#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
190#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2)) 190#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
191#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2)) 191#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
@@ -230,7 +230,7 @@
230 *******************************/ 230 *******************************/
231 231
232/* Registers */ 232/* Registers */
233#define NETX_PIO_REG(ofs) __io(NETX_VA_PIO + (ofs)) 233#define NETX_PIO_REG(ofs) IOMEM(NETX_VA_PIO + (ofs))
234#define NETX_PIO_INPIO NETX_PIO_REG(0x0) 234#define NETX_PIO_INPIO NETX_PIO_REG(0x0)
235#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4) 235#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)
236#define NETX_PIO_OEPIO NETX_PIO_REG(0x8) 236#define NETX_PIO_OEPIO NETX_PIO_REG(0x8)
@@ -240,7 +240,7 @@
240 *******************************/ 240 *******************************/
241 241
242/* Registers */ 242/* Registers */
243#define NETX_MIIMU __io(NETX_VA_MIIMU) 243#define NETX_MIIMU IOMEM(NETX_VA_MIIMU)
244 244
245/* Bits */ 245/* Bits */
246#define MIIMU_SNRDY (1<<0) 246#define MIIMU_SNRDY (1<<0)
@@ -317,7 +317,7 @@
317 *******************************/ 317 *******************************/
318 318
319/* Registers */ 319/* Registers */
320#define NETX_PFIFO_REG(ofs) __io(NETX_VA_PFIFO + (ofs)) 320#define NETX_PFIFO_REG(ofs) IOMEM(NETX_VA_PFIFO + (ofs))
321#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2)) 321#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
322#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2)) 322#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
323#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100) 323#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)
@@ -334,7 +334,7 @@
334 *******************************/ 334 *******************************/
335 335
336/* Registers */ 336/* Registers */
337#define NETX_MEMCR_REG(ofs) __io(NETX_VA_MEMCR + (ofs)) 337#define NETX_MEMCR_REG(ofs) IOMEM(NETX_VA_MEMCR + (ofs))
338#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */ 338#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
339#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40) 339#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40)
340#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44) 340#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44)
@@ -355,7 +355,7 @@
355 *******************************/ 355 *******************************/
356 356
357/* Registers */ 357/* Registers */
358#define NETX_DPMAS_REG(ofs) __io(NETX_VA_DPMAS + (ofs)) 358#define NETX_DPMAS_REG(ofs) IOMEM(NETX_VA_DPMAS + (ofs))
359#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8) 359#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)
360#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0) 360#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)
361#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0) 361#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)
@@ -425,7 +425,7 @@
425/******************************* 425/*******************************
426 * I2C * 426 * I2C *
427 *******************************/ 427 *******************************/
428#define NETX_I2C_REG(ofs) __io(NETX_VA_I2C, (ofs)) 428#define NETX_I2C_REG(ofs) IOMEM(NETX_VA_I2C, (ofs))
429#define NETX_I2C_CTRL NETX_I2C_REG(0x0) 429#define NETX_I2C_CTRL NETX_I2C_REG(0x0)
430#define NETX_I2C_DATA NETX_I2C_REG(0x4) 430#define NETX_I2C_DATA NETX_I2C_REG(0x4)
431 431