aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-mx5
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-mx5')
-rw-r--r--arch/arm/mach-mx5/Kconfig18
-rw-r--r--arch/arm/mach-mx5/Makefile9
-rw-r--r--arch/arm/mach-mx5/Makefile.boot3
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c98
-rw-r--r--arch/arm/mach-mx5/clock-mx51.c826
-rw-r--r--arch/arm/mach-mx5/cpu.c100
-rw-r--r--arch/arm/mach-mx5/crm_regs.h583
-rw-r--r--arch/arm/mach-mx5/devices.c96
-rw-r--r--arch/arm/mach-mx5/devices.h4
-rw-r--r--arch/arm/mach-mx5/mm.c83
10 files changed, 1820 insertions, 0 deletions
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
new file mode 100644
index 000000000000..1576d51e676c
--- /dev/null
+++ b/arch/arm/mach-mx5/Kconfig
@@ -0,0 +1,18 @@
1if ARCH_MX5
2
3config ARCH_MX51
4 bool
5 default y
6 select MXC_TZIC
7 select ARCH_MXC_IOMUX_V3
8
9comment "MX5 platforms:"
10
11config MACH_MX51_BABBAGE
12 bool "Support MX51 BABBAGE platforms"
13 help
14 Include support for MX51 Babbage platform, also known as MX51EVK in
15 u-boot. This includes specific configurations for the board and its
16 peripherals.
17
18endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
new file mode 100644
index 000000000000..bf23f869ef51
--- /dev/null
+++ b/arch/arm/mach-mx5/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6obj-y := cpu.o mm.o clock-mx51.o devices.o
7
8obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
9
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
new file mode 100644
index 000000000000..9939a19d99a1
--- /dev/null
+++ b/arch/arm/mach-mx5/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x90008000
2params_phys-y := 0x90000100
3initrd_phys-y := 0x90800000
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
new file mode 100644
index 000000000000..ee67a71db80d
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
15
16#include <mach/common.h>
17#include <mach/hardware.h>
18#include <mach/imx-uart.h>
19#include <mach/iomux-mx51.h>
20
21#include <asm/irq.h>
22#include <asm/setup.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/time.h>
26
27#include "devices.h"
28
29static struct platform_device *devices[] __initdata = {
30 &mxc_fec_device,
31};
32
33static struct pad_desc mx51babbage_pads[] = {
34 /* UART1 */
35 MX51_PAD_UART1_RXD__UART1_RXD,
36 MX51_PAD_UART1_TXD__UART1_TXD,
37 MX51_PAD_UART1_RTS__UART1_RTS,
38 MX51_PAD_UART1_CTS__UART1_CTS,
39
40 /* UART2 */
41 MX51_PAD_UART2_RXD__UART2_RXD,
42 MX51_PAD_UART2_TXD__UART2_TXD,
43
44 /* UART3 */
45 MX51_PAD_EIM_D25__UART3_RXD,
46 MX51_PAD_EIM_D26__UART3_TXD,
47 MX51_PAD_EIM_D27__UART3_RTS,
48 MX51_PAD_EIM_D24__UART3_CTS,
49};
50
51/* Serial ports */
52#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
53static struct imxuart_platform_data uart_pdata = {
54 .flags = IMXUART_HAVE_RTSCTS,
55};
56
57static inline void mxc_init_imx_uart(void)
58{
59 mxc_register_device(&mxc_uart_device0, &uart_pdata);
60 mxc_register_device(&mxc_uart_device1, &uart_pdata);
61 mxc_register_device(&mxc_uart_device2, &uart_pdata);
62}
63#else /* !SERIAL_IMX */
64static inline void mxc_init_imx_uart(void)
65{
66}
67#endif /* SERIAL_IMX */
68
69/*
70 * Board specific initialization.
71 */
72static void __init mxc_board_init(void)
73{
74 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
75 ARRAY_SIZE(mx51babbage_pads));
76 mxc_init_imx_uart();
77 platform_add_devices(devices, ARRAY_SIZE(devices));
78}
79
80static void __init mx51_babbage_timer_init(void)
81{
82 mx51_clocks_init(32768, 24000000, 22579200, 0);
83}
84
85static struct sys_timer mxc_timer = {
86 .init = mx51_babbage_timer_init,
87};
88
89MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
90 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
91 .phys_io = MX51_AIPS1_BASE_ADDR,
92 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
93 .boot_params = PHYS_OFFSET + 0x100,
94 .map_io = mx51_map_io,
95 .init_irq = mx51_init_irq,
96 .init_machine = mxc_board_init,
97 .timer = &mxc_timer,
98MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
new file mode 100644
index 000000000000..1ee6ce4087b8
--- /dev/null
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -0,0 +1,826 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/mm.h>
14#include <linux/delay.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17
18#include <asm/clkdev.h>
19#include <asm/div64.h>
20
21#include <mach/hardware.h>
22#include <mach/common.h>
23#include <mach/clock.h>
24
25#include "crm_regs.h"
26
27/* External clock values passed-in by the board code */
28static unsigned long external_high_reference, external_low_reference;
29static unsigned long oscillator_reference, ckih2_reference;
30
31static struct clk osc_clk;
32static struct clk pll1_main_clk;
33static struct clk pll1_sw_clk;
34static struct clk pll2_sw_clk;
35static struct clk pll3_sw_clk;
36static struct clk lp_apm_clk;
37static struct clk periph_apm_clk;
38static struct clk ahb_clk;
39static struct clk ipg_clk;
40
41#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
42
43static int _clk_ccgr_enable(struct clk *clk)
44{
45 u32 reg;
46
47 reg = __raw_readl(clk->enable_reg);
48 reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
49 __raw_writel(reg, clk->enable_reg);
50
51 return 0;
52}
53
54static void _clk_ccgr_disable(struct clk *clk)
55{
56 u32 reg;
57 reg = __raw_readl(clk->enable_reg);
58 reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);
59 __raw_writel(reg, clk->enable_reg);
60
61}
62
63static void _clk_ccgr_disable_inwait(struct clk *clk)
64{
65 u32 reg;
66
67 reg = __raw_readl(clk->enable_reg);
68 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
69 reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
70 __raw_writel(reg, clk->enable_reg);
71}
72
73/*
74 * For the 4-to-1 muxed input clock
75 */
76static inline u32 _get_mux(struct clk *parent, struct clk *m0,
77 struct clk *m1, struct clk *m2, struct clk *m3)
78{
79 if (parent == m0)
80 return 0;
81 else if (parent == m1)
82 return 1;
83 else if (parent == m2)
84 return 2;
85 else if (parent == m3)
86 return 3;
87 else
88 BUG();
89
90 return -EINVAL;
91}
92
93static inline void __iomem *_get_pll_base(struct clk *pll)
94{
95 if (pll == &pll1_main_clk)
96 return MX51_DPLL1_BASE;
97 else if (pll == &pll2_sw_clk)
98 return MX51_DPLL2_BASE;
99 else if (pll == &pll3_sw_clk)
100 return MX51_DPLL3_BASE;
101 else
102 BUG();
103
104 return NULL;
105}
106
107static unsigned long clk_pll_get_rate(struct clk *clk)
108{
109 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
110 unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
111 void __iomem *pllbase;
112 s64 temp;
113 unsigned long parent_rate;
114
115 parent_rate = clk_get_rate(clk->parent);
116
117 pllbase = _get_pll_base(clk);
118
119 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
120 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
121 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
122
123 if (pll_hfsm == 0) {
124 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
125 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
126 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
127 } else {
128 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
129 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
130 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
131 }
132 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
133 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
134 mfi = (mfi <= 5) ? 5 : mfi;
135 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
136 mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
137 /* Sign extend to 32-bits */
138 if (mfn >= 0x04000000) {
139 mfn |= 0xFC000000;
140 mfn_abs = -mfn;
141 }
142
143 ref_clk = 2 * parent_rate;
144 if (dbl != 0)
145 ref_clk *= 2;
146
147 ref_clk /= (pdf + 1);
148 temp = (u64) ref_clk * mfn_abs;
149 do_div(temp, mfd + 1);
150 if (mfn < 0)
151 temp = -temp;
152 temp = (ref_clk * mfi) + temp;
153
154 return temp;
155}
156
157static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
158{
159 u32 reg;
160 void __iomem *pllbase;
161
162 long mfi, pdf, mfn, mfd = 999999;
163 s64 temp64;
164 unsigned long quad_parent_rate;
165 unsigned long pll_hfsm, dp_ctl;
166 unsigned long parent_rate;
167
168 parent_rate = clk_get_rate(clk->parent);
169
170 pllbase = _get_pll_base(clk);
171
172 quad_parent_rate = 4 * parent_rate;
173 pdf = mfi = -1;
174 while (++pdf < 16 && mfi < 5)
175 mfi = rate * (pdf+1) / quad_parent_rate;
176 if (mfi > 15)
177 return -EINVAL;
178 pdf--;
179
180 temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
181 do_div(temp64, quad_parent_rate/1000000);
182 mfn = (long)temp64;
183
184 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
185 /* use dpdck0_2 */
186 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
187 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
188 if (pll_hfsm == 0) {
189 reg = mfi << 4 | pdf;
190 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
191 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
192 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
193 } else {
194 reg = mfi << 4 | pdf;
195 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
196 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
197 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
198 }
199
200 return 0;
201}
202
203static int _clk_pll_enable(struct clk *clk)
204{
205 u32 reg;
206 void __iomem *pllbase;
207 int i = 0;
208
209 pllbase = _get_pll_base(clk);
210 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
211 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
212
213 /* Wait for lock */
214 do {
215 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
216 if (reg & MXC_PLL_DP_CTL_LRF)
217 break;
218
219 udelay(1);
220 } while (++i < MAX_DPLL_WAIT_TRIES);
221
222 if (i == MAX_DPLL_WAIT_TRIES) {
223 pr_err("MX5: pll locking failed\n");
224 return -EINVAL;
225 }
226
227 return 0;
228}
229
230static void _clk_pll_disable(struct clk *clk)
231{
232 u32 reg;
233 void __iomem *pllbase;
234
235 pllbase = _get_pll_base(clk);
236 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
237 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
238}
239
240static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
241{
242 u32 reg, step;
243
244 reg = __raw_readl(MXC_CCM_CCSR);
245
246 /* When switching from pll_main_clk to a bypass clock, first select a
247 * multiplexed clock in 'step_sel', then shift the glitchless mux
248 * 'pll1_sw_clk_sel'.
249 *
250 * When switching back, do it in reverse order
251 */
252 if (parent == &pll1_main_clk) {
253 /* Switch to pll1_main_clk */
254 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
255 __raw_writel(reg, MXC_CCM_CCSR);
256 /* step_clk mux switched to lp_apm, to save power. */
257 reg = __raw_readl(MXC_CCM_CCSR);
258 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
259 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
260 MXC_CCM_CCSR_STEP_SEL_OFFSET);
261 } else {
262 if (parent == &lp_apm_clk) {
263 step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
264 } else if (parent == &pll2_sw_clk) {
265 step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
266 } else if (parent == &pll3_sw_clk) {
267 step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
268 } else
269 return -EINVAL;
270
271 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
272 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
273
274 __raw_writel(reg, MXC_CCM_CCSR);
275 /* Switch to step_clk */
276 reg = __raw_readl(MXC_CCM_CCSR);
277 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
278 }
279 __raw_writel(reg, MXC_CCM_CCSR);
280 return 0;
281}
282
283static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
284{
285 u32 reg, div;
286 unsigned long parent_rate;
287
288 parent_rate = clk_get_rate(clk->parent);
289
290 reg = __raw_readl(MXC_CCM_CCSR);
291
292 if (clk->parent == &pll2_sw_clk) {
293 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
294 MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
295 } else if (clk->parent == &pll3_sw_clk) {
296 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
297 MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
298 } else
299 div = 1;
300 return parent_rate / div;
301}
302
303static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
304{
305 u32 reg;
306
307 reg = __raw_readl(MXC_CCM_CCSR);
308
309 if (parent == &pll2_sw_clk)
310 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
311 else
312 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
313
314 __raw_writel(reg, MXC_CCM_CCSR);
315 return 0;
316}
317
318static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
319{
320 u32 reg;
321
322 if (parent == &osc_clk)
323 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
324 else
325 return -EINVAL;
326
327 __raw_writel(reg, MXC_CCM_CCSR);
328
329 return 0;
330}
331
332static unsigned long clk_arm_get_rate(struct clk *clk)
333{
334 u32 cacrr, div;
335 unsigned long parent_rate;
336
337 parent_rate = clk_get_rate(clk->parent);
338 cacrr = __raw_readl(MXC_CCM_CACRR);
339 div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
340
341 return parent_rate / div;
342}
343
344static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
345{
346 u32 reg, mux;
347 int i = 0;
348
349 mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
350
351 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
352 reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
353 __raw_writel(reg, MXC_CCM_CBCMR);
354
355 /* Wait for lock */
356 do {
357 reg = __raw_readl(MXC_CCM_CDHIPR);
358 if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
359 break;
360
361 udelay(1);
362 } while (++i < MAX_DPLL_WAIT_TRIES);
363
364 if (i == MAX_DPLL_WAIT_TRIES) {
365 pr_err("MX5: Set parent for periph_apm clock failed\n");
366 return -EINVAL;
367 }
368
369 return 0;
370}
371
372static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
373{
374 u32 reg;
375
376 reg = __raw_readl(MXC_CCM_CBCDR);
377
378 if (parent == &pll2_sw_clk)
379 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
380 else if (parent == &periph_apm_clk)
381 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
382 else
383 return -EINVAL;
384
385 __raw_writel(reg, MXC_CCM_CBCDR);
386
387 return 0;
388}
389
390static struct clk main_bus_clk = {
391 .parent = &pll2_sw_clk,
392 .set_parent = _clk_main_bus_set_parent,
393};
394
395static unsigned long clk_ahb_get_rate(struct clk *clk)
396{
397 u32 reg, div;
398 unsigned long parent_rate;
399
400 parent_rate = clk_get_rate(clk->parent);
401
402 reg = __raw_readl(MXC_CCM_CBCDR);
403 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
404 MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
405 return parent_rate / div;
406}
407
408
409static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
410{
411 u32 reg, div;
412 unsigned long parent_rate;
413 int i = 0;
414
415 parent_rate = clk_get_rate(clk->parent);
416
417 div = parent_rate / rate;
418 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
419 return -EINVAL;
420
421 reg = __raw_readl(MXC_CCM_CBCDR);
422 reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
423 reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
424 __raw_writel(reg, MXC_CCM_CBCDR);
425
426 /* Wait for lock */
427 do {
428 reg = __raw_readl(MXC_CCM_CDHIPR);
429 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
430 break;
431
432 udelay(1);
433 } while (++i < MAX_DPLL_WAIT_TRIES);
434
435 if (i == MAX_DPLL_WAIT_TRIES) {
436 pr_err("MX5: clk_ahb_set_rate failed\n");
437 return -EINVAL;
438 }
439
440 return 0;
441}
442
443static unsigned long _clk_ahb_round_rate(struct clk *clk,
444 unsigned long rate)
445{
446 u32 div;
447 unsigned long parent_rate;
448
449 parent_rate = clk_get_rate(clk->parent);
450
451 div = parent_rate / rate;
452 if (div > 8)
453 div = 8;
454 else if (div == 0)
455 div++;
456 return parent_rate / div;
457}
458
459
460static int _clk_max_enable(struct clk *clk)
461{
462 u32 reg;
463
464 _clk_ccgr_enable(clk);
465
466 /* Handshake with MAX when LPM is entered. */
467 reg = __raw_readl(MXC_CCM_CLPCR);
468 reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
469 __raw_writel(reg, MXC_CCM_CLPCR);
470
471 return 0;
472}
473
474static void _clk_max_disable(struct clk *clk)
475{
476 u32 reg;
477
478 _clk_ccgr_disable_inwait(clk);
479
480 /* No Handshake with MAX when LPM is entered as its disabled. */
481 reg = __raw_readl(MXC_CCM_CLPCR);
482 reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
483 __raw_writel(reg, MXC_CCM_CLPCR);
484}
485
486static unsigned long clk_ipg_get_rate(struct clk *clk)
487{
488 u32 reg, div;
489 unsigned long parent_rate;
490
491 parent_rate = clk_get_rate(clk->parent);
492
493 reg = __raw_readl(MXC_CCM_CBCDR);
494 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
495 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
496
497 return parent_rate / div;
498}
499
500static unsigned long clk_ipg_per_get_rate(struct clk *clk)
501{
502 u32 reg, prediv1, prediv2, podf;
503 unsigned long parent_rate;
504
505 parent_rate = clk_get_rate(clk->parent);
506
507 if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
508 /* the main_bus_clk is the one before the DVFS engine */
509 reg = __raw_readl(MXC_CCM_CBCDR);
510 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
511 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
512 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
513 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
514 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
515 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
516 return parent_rate / (prediv1 * prediv2 * podf);
517 } else if (clk->parent == &ipg_clk)
518 return parent_rate;
519 else
520 BUG();
521}
522
523static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
524{
525 u32 reg;
526
527 reg = __raw_readl(MXC_CCM_CBCMR);
528
529 reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
530 reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
531
532 if (parent == &ipg_clk)
533 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
534 else if (parent == &lp_apm_clk)
535 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
536 else if (parent != &main_bus_clk)
537 return -EINVAL;
538
539 __raw_writel(reg, MXC_CCM_CBCMR);
540
541 return 0;
542}
543
544static unsigned long clk_uart_get_rate(struct clk *clk)
545{
546 u32 reg, prediv, podf;
547 unsigned long parent_rate;
548
549 parent_rate = clk_get_rate(clk->parent);
550
551 reg = __raw_readl(MXC_CCM_CSCDR1);
552 prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
553 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
554 podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
555 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
556
557 return parent_rate / (prediv * podf);
558}
559
560static int _clk_uart_set_parent(struct clk *clk, struct clk *parent)
561{
562 u32 reg, mux;
563
564 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
565 &lp_apm_clk);
566 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
567 reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
568 __raw_writel(reg, MXC_CCM_CSCMR1);
569
570 return 0;
571}
572
573static unsigned long get_high_reference_clock_rate(struct clk *clk)
574{
575 return external_high_reference;
576}
577
578static unsigned long get_low_reference_clock_rate(struct clk *clk)
579{
580 return external_low_reference;
581}
582
583static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
584{
585 return oscillator_reference;
586}
587
588static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
589{
590 return ckih2_reference;
591}
592
593/* External high frequency clock */
594static struct clk ckih_clk = {
595 .get_rate = get_high_reference_clock_rate,
596};
597
598static struct clk ckih2_clk = {
599 .get_rate = get_ckih2_reference_clock_rate,
600};
601
602static struct clk osc_clk = {
603 .get_rate = get_oscillator_reference_clock_rate,
604};
605
606/* External low frequency (32kHz) clock */
607static struct clk ckil_clk = {
608 .get_rate = get_low_reference_clock_rate,
609};
610
611static struct clk pll1_main_clk = {
612 .parent = &osc_clk,
613 .get_rate = clk_pll_get_rate,
614 .enable = _clk_pll_enable,
615 .disable = _clk_pll_disable,
616};
617
618/* Clock tree block diagram (WIP):
619 * CCM: Clock Controller Module
620 *
621 * PLL output -> |
622 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
623 * PLL bypass -> |
624 *
625 */
626
627/* PLL1 SW supplies to ARM core */
628static struct clk pll1_sw_clk = {
629 .parent = &pll1_main_clk,
630 .set_parent = _clk_pll1_sw_set_parent,
631 .get_rate = clk_pll1_sw_get_rate,
632};
633
634/* PLL2 SW supplies to AXI/AHB/IP buses */
635static struct clk pll2_sw_clk = {
636 .parent = &osc_clk,
637 .get_rate = clk_pll_get_rate,
638 .set_rate = _clk_pll_set_rate,
639 .set_parent = _clk_pll2_sw_set_parent,
640 .enable = _clk_pll_enable,
641 .disable = _clk_pll_disable,
642};
643
644/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
645static struct clk pll3_sw_clk = {
646 .parent = &osc_clk,
647 .set_rate = _clk_pll_set_rate,
648 .get_rate = clk_pll_get_rate,
649 .enable = _clk_pll_enable,
650 .disable = _clk_pll_disable,
651};
652
653/* Low-power Audio Playback Mode clock */
654static struct clk lp_apm_clk = {
655 .parent = &osc_clk,
656 .set_parent = _clk_lp_apm_set_parent,
657};
658
659static struct clk periph_apm_clk = {
660 .parent = &pll1_sw_clk,
661 .set_parent = _clk_periph_apm_set_parent,
662};
663
664static struct clk cpu_clk = {
665 .parent = &pll1_sw_clk,
666 .get_rate = clk_arm_get_rate,
667};
668
669static struct clk ahb_clk = {
670 .parent = &main_bus_clk,
671 .get_rate = clk_ahb_get_rate,
672 .set_rate = _clk_ahb_set_rate,
673 .round_rate = _clk_ahb_round_rate,
674};
675
676/* Main IP interface clock for access to registers */
677static struct clk ipg_clk = {
678 .parent = &ahb_clk,
679 .get_rate = clk_ipg_get_rate,
680};
681
682static struct clk ipg_perclk = {
683 .parent = &lp_apm_clk,
684 .get_rate = clk_ipg_per_get_rate,
685 .set_parent = _clk_ipg_per_set_parent,
686};
687
688static struct clk uart_root_clk = {
689 .parent = &pll2_sw_clk,
690 .get_rate = clk_uart_get_rate,
691 .set_parent = _clk_uart_set_parent,
692};
693
694static struct clk ahb_max_clk = {
695 .parent = &ahb_clk,
696 .enable_reg = MXC_CCM_CCGR0,
697 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
698 .enable = _clk_max_enable,
699 .disable = _clk_max_disable,
700};
701
702static struct clk aips_tz1_clk = {
703 .parent = &ahb_clk,
704 .secondary = &ahb_max_clk,
705 .enable_reg = MXC_CCM_CCGR0,
706 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
707 .enable = _clk_ccgr_enable,
708 .disable = _clk_ccgr_disable_inwait,
709};
710
711static struct clk aips_tz2_clk = {
712 .parent = &ahb_clk,
713 .secondary = &ahb_max_clk,
714 .enable_reg = MXC_CCM_CCGR0,
715 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
716 .enable = _clk_ccgr_enable,
717 .disable = _clk_ccgr_disable_inwait,
718};
719
720static struct clk gpt_32k_clk = {
721 .id = 0,
722 .parent = &ckil_clk,
723};
724
725#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
726 static struct clk name = { \
727 .id = i, \
728 .enable_reg = er, \
729 .enable_shift = es, \
730 .get_rate = gr, \
731 .set_rate = sr, \
732 .enable = _clk_ccgr_enable, \
733 .disable = _clk_ccgr_disable, \
734 .parent = p, \
735 .secondary = s, \
736 }
737
738/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
739 get_rate, set_rate, parent, secondary); */
740
741/* Shared peripheral bus arbiter */
742DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
743 NULL, NULL, &ipg_clk, NULL);
744
745/* UART */
746DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
747 NULL, NULL, &uart_root_clk, NULL);
748DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
749 NULL, NULL, &uart_root_clk, NULL);
750DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
751 NULL, NULL, &uart_root_clk, NULL);
752DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
753 NULL, NULL, &ipg_clk, &aips_tz1_clk);
754DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
755 NULL, NULL, &ipg_clk, &aips_tz1_clk);
756DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
757 NULL, NULL, &ipg_clk, &spba_clk);
758
759/* GPT */
760DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
761 NULL, NULL, &ipg_clk, NULL);
762DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
763 NULL, NULL, &ipg_clk, NULL);
764
765/* FEC */
766DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
767 NULL, NULL, &ipg_clk, NULL);
768
769#define _REGISTER_CLOCK(d, n, c) \
770 { \
771 .dev_id = d, \
772 .con_id = n, \
773 .clk = &c, \
774 },
775
776static struct clk_lookup lookups[] = {
777 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
778 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
779 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
780 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
781 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
782};
783
784static void clk_tree_init(void)
785{
786 u32 reg;
787
788 ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
789
790 /*
791 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
792 * 8MHz, its derived from lp_apm.
793 *
794 * FIXME: Verify if true for all boards
795 */
796 reg = __raw_readl(MXC_CCM_CBCDR);
797 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
798 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
799 reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
800 reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
801 __raw_writel(reg, MXC_CCM_CBCDR);
802}
803
804int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
805 unsigned long ckih1, unsigned long ckih2)
806{
807 int i;
808
809 external_low_reference = ckil;
810 external_high_reference = ckih1;
811 ckih2_reference = ckih2;
812 oscillator_reference = osc;
813
814 for (i = 0; i < ARRAY_SIZE(lookups); i++)
815 clkdev_add(&lookups[i]);
816
817 clk_tree_init();
818
819 clk_enable(&cpu_clk);
820 clk_enable(&main_bus_clk);
821
822 /* System timer */
823 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
824 MX51_MXC_INT_GPT);
825 return 0;
826}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
new file mode 100644
index 000000000000..2d37785e3857
--- /dev/null
+++ b/arch/arm/mach-mx5/cpu.c
@@ -0,0 +1,100 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * This file contains the CPU initialization code.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <mach/hardware.h>
19#include <asm/io.h>
20
21static int cpu_silicon_rev = -1;
22
23#define SI_REV 0x48
24
25static void query_silicon_parameter(void)
26{
27 void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
28 u32 rev;
29
30 if (!rom) {
31 cpu_silicon_rev = -EINVAL;
32 return;
33 }
34
35 rev = readl(rom + SI_REV);
36 switch (rev) {
37 case 0x1:
38 cpu_silicon_rev = MX51_CHIP_REV_1_0;
39 break;
40 case 0x2:
41 cpu_silicon_rev = MX51_CHIP_REV_1_1;
42 break;
43 case 0x10:
44 cpu_silicon_rev = MX51_CHIP_REV_2_0;
45 break;
46 case 0x20:
47 cpu_silicon_rev = MX51_CHIP_REV_3_0;
48 break;
49 default:
50 cpu_silicon_rev = 0;
51 }
52
53 iounmap(rom);
54}
55
56/*
57 * Returns:
58 * the silicon revision of the cpu
59 * -EINVAL - not a mx51
60 */
61int mx51_revision(void)
62{
63 if (!cpu_is_mx51())
64 return -EINVAL;
65
66 if (cpu_silicon_rev == -1)
67 query_silicon_parameter();
68
69 return cpu_silicon_rev;
70}
71EXPORT_SYMBOL(mx51_revision);
72
73static int __init post_cpu_init(void)
74{
75 unsigned int reg;
76 void __iomem *base;
77
78 if (!cpu_is_mx51())
79 return 0;
80
81 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
82 __raw_writel(0x0, base + 0x40);
83 __raw_writel(0x0, base + 0x44);
84 __raw_writel(0x0, base + 0x48);
85 __raw_writel(0x0, base + 0x4C);
86 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
87 __raw_writel(reg, base + 0x50);
88
89 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
90 __raw_writel(0x0, base + 0x40);
91 __raw_writel(0x0, base + 0x44);
92 __raw_writel(0x0, base + 0x48);
93 __raw_writel(0x0, base + 0x4C);
94 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
95 __raw_writel(reg, base + 0x50);
96
97 return 0;
98}
99
100postcore_initcall(post_cpu_init);
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
new file mode 100644
index 000000000000..c776b9af0624
--- /dev/null
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -0,0 +1,583 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
12#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
13
14#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
15#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
16#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
17#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
18#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
19#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
20
21/* PLL Register Offsets */
22#define MXC_PLL_DP_CTL 0x00
23#define MXC_PLL_DP_CONFIG 0x04
24#define MXC_PLL_DP_OP 0x08
25#define MXC_PLL_DP_MFD 0x0C
26#define MXC_PLL_DP_MFN 0x10
27#define MXC_PLL_DP_MFNMINUS 0x14
28#define MXC_PLL_DP_MFNPLUS 0x18
29#define MXC_PLL_DP_HFS_OP 0x1C
30#define MXC_PLL_DP_HFS_MFD 0x20
31#define MXC_PLL_DP_HFS_MFN 0x24
32#define MXC_PLL_DP_MFN_TOGC 0x28
33#define MXC_PLL_DP_DESTAT 0x2c
34
35/* PLL Register Bit definitions */
36#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
37#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
38#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
39#define MXC_PLL_DP_CTL_ADE 0x800
40#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
41#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
42#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
43#define MXC_PLL_DP_CTL_HFSM 0x80
44#define MXC_PLL_DP_CTL_PRE 0x40
45#define MXC_PLL_DP_CTL_UPEN 0x20
46#define MXC_PLL_DP_CTL_RST 0x10
47#define MXC_PLL_DP_CTL_RCP 0x8
48#define MXC_PLL_DP_CTL_PLM 0x4
49#define MXC_PLL_DP_CTL_BRM0 0x2
50#define MXC_PLL_DP_CTL_LRF 0x1
51
52#define MXC_PLL_DP_CONFIG_BIST 0x8
53#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
54#define MXC_PLL_DP_CONFIG_AREN 0x2
55#define MXC_PLL_DP_CONFIG_LDREQ 0x1
56
57#define MXC_PLL_DP_OP_MFI_OFFSET 4
58#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
59#define MXC_PLL_DP_OP_PDF_OFFSET 0
60#define MXC_PLL_DP_OP_PDF_MASK 0xF
61
62#define MXC_PLL_DP_MFD_OFFSET 0
63#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
64
65#define MXC_PLL_DP_MFN_OFFSET 0x0
66#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
67
68#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
69#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
70#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
71#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
72
73#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
74#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
75
76/* Register addresses of CCM*/
77#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
78#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
79#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
80#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
81#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
82#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
83#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
84#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
85#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
86#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
87#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
88#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
89#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
90#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
91#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
92#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
93#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
94#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
95#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
96#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
97#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
98#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
99#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
100#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
101#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
102#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
103#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
104#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
105#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
106#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
107#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
108#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
109#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
110#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
111
112/* Define the bits in register CCR */
113#define MXC_CCM_CCR_COSC_EN (1 << 12)
114#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
115#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
116#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
117#define MXC_CCM_CCR_FPM_EN (1 << 8)
118#define MXC_CCM_CCR_OSCNT_OFFSET (0)
119#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
120
121/* Define the bits in register CCDR */
122#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
123#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
124#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
125
126/* Define the bits in register CSR */
127#define MXC_CCM_CSR_COSR_READY (1 << 5)
128#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
129#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
130#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
131#define MXC_CCM_CSR_FPM_READY (1 << 1)
132#define MXC_CCM_CSR_REF_EN_B (1 << 0)
133
134/* Define the bits in register CCSR */
135#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
136#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
137#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
138#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
139#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
140#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
141#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
142#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
143#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
144#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
145#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
146#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
147 1: step_clk */
148#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
149#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
150
151/* Define the bits in register CACRR */
152#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
153#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
154
155/* Define the bits in register CBCDR */
156#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
157#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
158#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
159#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
160#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
161#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
162#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
163#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
164#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
165#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
166#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
167#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
168#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
169#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
170#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
171#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
172#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
173#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
174#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
175#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
176#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
177#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
178#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
179#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
180
181/* Define the bits in register CBCMR */
182#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
183#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
184#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
185#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
186#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
187#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
188#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
189#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
190#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
191#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
192#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
193#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
194#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
195#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
196#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
197#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
198
199/* Define the bits in register CSCMR1 */
200#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
201#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
202#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
203#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
204#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
205#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
206#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
207#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
208#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
209#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
210#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
211#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
212#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
213#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
214#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
215#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
216#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
217#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
218#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
219#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
220#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
221#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
222#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
223#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
224#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
225#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
226#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
227#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
228#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
229#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
230#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
231#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
232
233/* Define the bits in register CSCMR2 */
234#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
235#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
236#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
237#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
238#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
239#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
240#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
241#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
242#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
243#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
244#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
245#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
246#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
247#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
248#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
249#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
250#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
251#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
252#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
253#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
254#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
255#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
256#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
257#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
258#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
259#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
260#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
261
262/* Define the bits in register CSCDR1 */
263#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
264#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
265#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
266#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
267#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
268#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
269#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
270#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
271#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
272#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
273#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
274#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
275#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
276#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
277#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
278#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
279#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
280#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
281
282/* Define the bits in register CS1CDR and CS2CDR */
283#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
284#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
285#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
286#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
287#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
288#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
289#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
290#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
291
292#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
293#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
294#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
295#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
296#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
297#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
298#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
299#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
300
301/* Define the bits in register CDCDR */
302#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
303#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
304#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
305#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
306#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
307#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
308#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
309#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
310#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
311#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
312#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
313#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
314#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
315#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
316#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
317#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
318
319/* Define the bits in register CHSCCDR */
320#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
321#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
322#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
323#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
324#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
325#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
326#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
327#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
328
329/* Define the bits in register CSCDR2 */
330#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
331#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
332#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
333#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
334#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
335#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
336#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
337#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
338#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
339#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
340#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
341#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
342
343/* Define the bits in register CSCDR3 */
344#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
345#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
346#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
347#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
348#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
349#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
350#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
351#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
352
353/* Define the bits in register CSCDR4 */
354#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
355#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
356#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
357#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
358#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
359#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
360#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
361#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
362
363/* Define the bits in register CDHIPR */
364#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
365#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
366#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
367#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
368#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
369#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
370#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
371#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
372#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
373#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
374
375/* Define the bits in register CDCR */
376#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
377#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
378#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
379
380/* Define the bits in register CLPCR */
381#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
382#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
383#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
384#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
385#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
386#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
387#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
388#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
389#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
390#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
391#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
392#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
393#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
394#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
395#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
396#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
397#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
398#define MXC_CCM_CLPCR_LPM_OFFSET (0)
399#define MXC_CCM_CLPCR_LPM_MASK (0x3)
400
401/* Define the bits in register CISR */
402#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
403#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
404#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
405#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
406#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
407#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
408#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
409#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
410#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
411#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
412#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
413#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
414#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
415#define MXC_CCM_CISR_LRF_PLL1 (0x1)
416
417/* Define the bits in register CIMR */
418#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
419#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
420#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
421#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
422#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
423#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
424#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
425#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
426#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
427#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
428#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
429#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
430#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
431
432/* Define the bits in register CCOSR */
433#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
434#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
435#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
436#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
437#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
438#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
439#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
440#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
441#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
442#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
443
444/* Define the bits in registers CGPR */
445#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
446#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
447#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
448#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
449
450/* Define the bits in registers CCGRx */
451#define MXC_CCM_CCGRx_CG_MASK 0x3
452#define MXC_CCM_CCGRx_MOD_OFF 0x0
453#define MXC_CCM_CCGRx_MOD_ON 0x3
454#define MXC_CCM_CCGRx_MOD_IDLE 0x1
455
456#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
457#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
458#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
459#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
460#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
461#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
462#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
463#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
464#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
465#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
466#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
467#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
468#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
469#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
470
471#define MXC_CCM_CCGRx_CG15_OFFSET 30
472#define MXC_CCM_CCGRx_CG14_OFFSET 28
473#define MXC_CCM_CCGRx_CG13_OFFSET 26
474#define MXC_CCM_CCGRx_CG12_OFFSET 24
475#define MXC_CCM_CCGRx_CG11_OFFSET 22
476#define MXC_CCM_CCGRx_CG10_OFFSET 20
477#define MXC_CCM_CCGRx_CG9_OFFSET 18
478#define MXC_CCM_CCGRx_CG8_OFFSET 16
479#define MXC_CCM_CCGRx_CG7_OFFSET 14
480#define MXC_CCM_CCGRx_CG6_OFFSET 12
481#define MXC_CCM_CCGRx_CG5_OFFSET 10
482#define MXC_CCM_CCGRx_CG4_OFFSET 8
483#define MXC_CCM_CCGRx_CG3_OFFSET 6
484#define MXC_CCM_CCGRx_CG2_OFFSET 4
485#define MXC_CCM_CCGRx_CG1_OFFSET 2
486#define MXC_CCM_CCGRx_CG0_OFFSET 0
487
488#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
489#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
490#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
491#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
492#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
493#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
494#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
495#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
496#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
497#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
498#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
499#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
500#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
501
502/* CORTEXA8 platform */
503#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
504#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
505#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
506#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
507#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
508#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
509#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
510#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
511#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
512
513/* DVFS CORE */
514#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
515#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
516#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
517#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
518#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
519#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
520#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
521#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
522#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
523#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
524#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
525#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
526#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
527#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
528#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
529#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
530#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
531
532/* GPC */
533#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
534#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
535#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
536#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
537#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
538#define MXC_GPC_PGR_ARMPG_OFFSET 8
539#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
540
541/* PGC */
542#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
543#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
544#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
545#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
546#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
547#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
548
549#define MXC_PGCR_PCR 1
550#define MXC_SRPGCR_PCR 1
551#define MXC_EMPGCR_PCR 1
552#define MXC_PGSR_PSR 1
553
554
555#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
556#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
557
558/* SRPG */
559#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
560#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
561#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
562
563#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
564#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
565#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
566
567#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
568#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
569#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
570
571#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
572#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
573#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
574
575#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
576#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
577#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
578
579#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
580#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
581#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
582
583#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
new file mode 100644
index 000000000000..d6fd3961ade9
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.c
@@ -0,0 +1,96 @@
1/*
2 * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/platform_device.h>
13#include <mach/hardware.h>
14#include <mach/imx-uart.h>
15
16static struct resource uart0[] = {
17 {
18 .start = MX51_UART1_BASE_ADDR,
19 .end = MX51_UART1_BASE_ADDR + 0xfff,
20 .flags = IORESOURCE_MEM,
21 }, {
22 .start = MX51_MXC_INT_UART1,
23 .end = MX51_MXC_INT_UART1,
24 .flags = IORESOURCE_IRQ,
25 },
26};
27
28struct platform_device mxc_uart_device0 = {
29 .name = "imx-uart",
30 .id = 0,
31 .resource = uart0,
32 .num_resources = ARRAY_SIZE(uart0),
33};
34
35static struct resource uart1[] = {
36 {
37 .start = MX51_UART2_BASE_ADDR,
38 .end = MX51_UART2_BASE_ADDR + 0xfff,
39 .flags = IORESOURCE_MEM,
40 }, {
41 .start = MX51_MXC_INT_UART2,
42 .end = MX51_MXC_INT_UART2,
43 .flags = IORESOURCE_IRQ,
44 },
45};
46
47struct platform_device mxc_uart_device1 = {
48 .name = "imx-uart",
49 .id = 1,
50 .resource = uart1,
51 .num_resources = ARRAY_SIZE(uart1),
52};
53
54static struct resource uart2[] = {
55 {
56 .start = MX51_UART3_BASE_ADDR,
57 .end = MX51_UART3_BASE_ADDR + 0xfff,
58 .flags = IORESOURCE_MEM,
59 }, {
60 .start = MX51_MXC_INT_UART3,
61 .end = MX51_MXC_INT_UART3,
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66struct platform_device mxc_uart_device2 = {
67 .name = "imx-uart",
68 .id = 2,
69 .resource = uart2,
70 .num_resources = ARRAY_SIZE(uart2),
71};
72
73static struct resource mxc_fec_resources[] = {
74 {
75 .start = MX51_MXC_FEC_BASE_ADDR,
76 .end = MX51_MXC_FEC_BASE_ADDR + 0xfff,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX51_MXC_INT_FEC,
80 .end = MX51_MXC_INT_FEC,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85struct platform_device mxc_fec_device = {
86 .name = "fec",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(mxc_fec_resources),
89 .resource = mxc_fec_resources,
90};
91
92/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */
93int __init mxc_register_gpios(void)
94{
95 return 0;
96}
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
new file mode 100644
index 000000000000..f339ab8c19be
--- /dev/null
+++ b/arch/arm/mach-mx5/devices.h
@@ -0,0 +1,4 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4extern struct platform_device mxc_fec_device;
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
new file mode 100644
index 000000000000..b7677ef80cc4
--- /dev/null
+++ b/arch/arm/mach-mx5/mm.c
@@ -0,0 +1,83 @@
1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14#include <linux/mm.h>
15#include <linux/init.h>
16
17#include <asm/mach/map.h>
18
19#include <mach/hardware.h>
20#include <mach/common.h>
21#include <mach/iomux-v3.h>
22
23/*
24 * Define the MX51 memory map.
25 */
26static struct map_desc mxc_io_desc[] __initdata = {
27 {
28 .virtual = MX51_IRAM_BASE_ADDR_VIRT,
29 .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR),
30 .length = MX51_IRAM_SIZE,
31 .type = MT_DEVICE
32 }, {
33 .virtual = MX51_DEBUG_BASE_ADDR_VIRT,
34 .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR),
35 .length = MX51_DEBUG_SIZE,
36 .type = MT_DEVICE
37 }, {
38 .virtual = MX51_AIPS1_BASE_ADDR_VIRT,
39 .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
40 .length = MX51_AIPS1_SIZE,
41 .type = MT_DEVICE
42 }, {
43 .virtual = MX51_SPBA0_BASE_ADDR_VIRT,
44 .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
45 .length = MX51_SPBA0_SIZE,
46 .type = MT_DEVICE
47 }, {
48 .virtual = MX51_AIPS2_BASE_ADDR_VIRT,
49 .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
50 .length = MX51_AIPS2_SIZE,
51 .type = MT_DEVICE
52 },
53};
54
55/*
56 * This function initializes the memory map. It is called during the
57 * system startup to create static physical to virtual memory mappings
58 * for the IO modules.
59 */
60void __init mx51_map_io(void)
61{
62 mxc_set_cpu_type(MXC_CPU_MX51);
63 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
64 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
65 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
66}
67
68void __init mx51_init_irq(void)
69{
70 unsigned long tzic_addr;
71 void __iomem *tzic_virt;
72
73 if (mx51_revision() < MX51_CHIP_REV_2_0)
74 tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
75 else
76 tzic_addr = MX51_TZIC_BASE_ADDR;
77
78 tzic_virt = ioremap(tzic_addr, SZ_16K);
79 if (!tzic_virt)
80 panic("unable to map TZIC interrupt controller\n");
81
82 tzic_init_irq(tzic_virt);
83}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-03 14:08:46 -0400