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-rw-r--r--arch/arm/mach-mx3/Kconfig24
-rw-r--r--arch/arm/mach-mx3/Makefile33
-rw-r--r--arch/arm/mach-mx3/clock-imx31.c (renamed from arch/arm/mach-mx3/clock.c)20
-rw-r--r--arch/arm/mach-mx3/clock-imx35.c55
-rw-r--r--arch/arm/mach-mx3/cpu.c57
-rw-r--r--arch/arm/mach-mx3/crm_regs.h2
-rw-r--r--arch/arm/mach-mx3/devices.c63
-rw-r--r--arch/arm/mach-mx3/devices.h5
-rw-r--r--arch/arm/mach-mx3/iomux-imx31.c (renamed from arch/arm/mach-mx3/iomux.c)2
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c (renamed from arch/arm/mach-mx3/armadillo5x0.c)240
-rw-r--r--arch/arm/mach-mx3/mach-kzm_arm11_01.c273
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c (renamed from arch/arm/mach-mx3/mx31pdk.c)133
-rw-r--r--arch/arm/mach-mx3/mach-mx31ads.c (renamed from arch/arm/mach-mx3/mx31ads.c)53
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c (renamed from arch/arm/mach-mx3/mx31lilly.c)67
-rw-r--r--arch/arm/mach-mx3/mach-mx31lite.c297
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c (renamed from arch/arm/mach-mx3/mx31moboard.c)290
-rw-r--r--arch/arm/mach-mx3/mach-mx35pdk.c (renamed from arch/arm/mach-mx3/mx35pdk.c)18
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c (renamed from arch/arm/mach-mx3/pcm037.c)187
-rw-r--r--arch/arm/mach-mx3/mach-pcm037_eet.c (renamed from arch/arm/mach-mx3/pcm037_eet.c)0
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c (renamed from arch/arm/mach-mx3/pcm043.c)167
-rw-r--r--arch/arm/mach-mx3/mach-qong.c (renamed from arch/arm/mach-mx3/qong.c)20
-rw-r--r--arch/arm/mach-mx3/mm.c5
-rw-r--r--arch/arm/mach-mx3/mx31lilly-db.c10
-rw-r--r--arch/arm/mach-mx3/mx31lite-db.c210
-rw-r--r--arch/arm/mach-mx3/mx31lite.c167
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c119
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c230
-rw-r--r--arch/arm/mach-mx3/mx31moboard-smartbot.c162
28 files changed, 2512 insertions, 397 deletions
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 851f2458bf65..170f68e46dd5 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -2,11 +2,13 @@ if ARCH_MX3
2 2
3config ARCH_MX31 3config ARCH_MX31
4 select ARCH_HAS_RNGA 4 select ARCH_HAS_RNGA
5 select ARCH_MXC_AUDMUX_V2
5 bool 6 bool
6 7
7config ARCH_MX35 8config ARCH_MX35
8 bool 9 bool
9 select ARCH_MXC_IOMUX_V3 10 select ARCH_MXC_IOMUX_V3
11 select ARCH_MXC_AUDMUX_V2
10 12
11comment "MX3 platforms:" 13comment "MX3 platforms:"
12 14
@@ -32,6 +34,7 @@ config MACH_MX31ADS_WM1133_EV1
32config MACH_PCM037 34config MACH_PCM037
33 bool "Support Phytec pcm037 (i.MX31) platforms" 35 bool "Support Phytec pcm037 (i.MX31) platforms"
34 select ARCH_MX31 36 select ARCH_MX31
37 select MXC_ULPI if USB_ULPI
35 help 38 help
36 Include support for Phytec pcm037 platform. This includes 39 Include support for Phytec pcm037 platform. This includes
37 specific configurations for the board and its peripherals. 40 specific configurations for the board and its peripherals.
@@ -47,6 +50,7 @@ config MACH_PCM037_EET
47config MACH_MX31LITE 50config MACH_MX31LITE
48 bool "Support MX31 LITEKIT (LogicPD)" 51 bool "Support MX31 LITEKIT (LogicPD)"
49 select ARCH_MX31 52 select ARCH_MX31
53 select MXC_ULPI if USB_ULPI
50 help 54 help
51 Include support for MX31 LITEKIT platform. This includes specific 55 Include support for MX31 LITEKIT platform. This includes specific
52 configurations for the board and its peripherals. 56 configurations for the board and its peripherals.
@@ -58,9 +62,19 @@ config MACH_MX31_3DS
58 Include support for MX31PDK (3DS) platform. This includes specific 62 Include support for MX31PDK (3DS) platform. This includes specific
59 configurations for the board and its peripherals. 63 configurations for the board and its peripherals.
60 64
65config MACH_MX31_3DS_MXC_NAND_USE_BBT
66 bool "Make the MXC NAND driver use the in flash Bad Block Table"
67 depends on MACH_MX31_3DS
68 depends on MTD_NAND_MXC
69 help
70 Enable this if you want that the MXC NAND driver uses the in flash
71 Bad Block Table to know what blocks are bad instead of scanning the
72 entire flash looking for bad block markers.
73
61config MACH_MX31MOBOARD 74config MACH_MX31MOBOARD
62 bool "Support mx31moboard platforms (EPFL Mobots group)" 75 bool "Support mx31moboard platforms (EPFL Mobots group)"
63 select ARCH_MX31 76 select ARCH_MX31
77 select MXC_ULPI if USB_ULPI
64 help 78 help
65 Include support for mx31moboard platform. This includes specific 79 Include support for mx31moboard platform. This includes specific
66 configurations for the board and its peripherals. 80 configurations for the board and its peripherals.
@@ -82,6 +96,7 @@ config MACH_QONG
82config MACH_PCM043 96config MACH_PCM043
83 bool "Support Phytec pcm043 (i.MX35) platforms" 97 bool "Support Phytec pcm043 (i.MX35) platforms"
84 select ARCH_MX35 98 select ARCH_MX35
99 select MXC_ULPI if USB_ULPI
85 help 100 help
86 Include support for Phytec pcm043 platform. This includes 101 Include support for Phytec pcm043 platform. This includes
87 specific configurations for the board and its peripherals. 102 specific configurations for the board and its peripherals.
@@ -89,6 +104,7 @@ config MACH_PCM043
89config MACH_ARMADILLO5X0 104config MACH_ARMADILLO5X0
90 bool "Support Atmark Armadillo-500 Development Base Board" 105 bool "Support Atmark Armadillo-500 Development Base Board"
91 select ARCH_MX31 106 select ARCH_MX31
107 select MXC_ULPI if USB_ULPI
92 help 108 help
93 Include support for Atmark Armadillo-500 platform. This includes 109 Include support for Atmark Armadillo-500 platform. This includes
94 specific configurations for the board and its peripherals. 110 specific configurations for the board and its peripherals.
@@ -100,4 +116,12 @@ config MACH_MX35_3DS
100 help 116 help
101 Include support for MX35PDK platform. This includes specific 117 Include support for MX35PDK platform. This includes specific
102 configurations for the board and its peripherals. 118 configurations for the board and its peripherals.
119
120config MACH_KZM_ARM11_01
121 bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
122 select ARCH_MX31
123 help
124 Include support for KZM-ARM11-01. This includes specific
125 configurations for the board and its peripherals.
126
103endif 127endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 6b9775471be6..5d650fda5d5d 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -4,18 +4,23 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := mm.o devices.o 7obj-y := mm.o devices.o cpu.o
8obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o 8CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
10CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
11obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o
9obj-$(CONFIG_ARCH_MX35) += clock-imx35.o 12obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
10obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o 13obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
11obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o 14obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
12obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o 15obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
13obj-$(CONFIG_MACH_PCM037) += pcm037.o 16obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
14obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o 17obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
15obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o 18obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
16obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ 19CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
17 mx31moboard-marxbot.o 20obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
18obj-$(CONFIG_MACH_QONG) += qong.o 21 mx31moboard-marxbot.o mx31moboard-smartbot.o
19obj-$(CONFIG_MACH_PCM043) += pcm043.o 22obj-$(CONFIG_MACH_QONG) += mach-qong.o
20obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o 23obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
21obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o 24obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
25obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o
26obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock-imx31.c
index b2a3bcf8266e..9a9eb6de6127 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -468,6 +468,7 @@ static struct clk ahb_clk = {
468 } 468 }
469 469
470DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); 470DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
471DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
471 472
472DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk); 473DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
473DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk); 474DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
@@ -490,7 +491,7 @@ DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
490DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk); 491DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
491DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk); 492DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
492DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk); 493DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
493DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk); 494DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk);
494DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk); 495DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
495DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk); 496DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
496DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk); 497DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
@@ -514,7 +515,6 @@ DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk)
514DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk); 515DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
515DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); 516DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
516DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); 517DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
517DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
518 518
519#define _REGISTER_CLOCK(d, n, c) \ 519#define _REGISTER_CLOCK(d, n, c) \
520 { \ 520 { \
@@ -558,8 +558,8 @@ static struct clk_lookup lookups[] = {
558 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) 558 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
559 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) 559 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
560 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) 560 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
561 _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) 561 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
562 _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) 562 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
563 _REGISTER_CLOCK(NULL, "firi", firi_clk) 563 _REGISTER_CLOCK(NULL, "firi", firi_clk)
564 _REGISTER_CLOCK(NULL, "ata", ata_clk) 564 _REGISTER_CLOCK(NULL, "ata", ata_clk)
565 _REGISTER_CLOCK(NULL, "rtic", rtic_clk) 565 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
@@ -572,18 +572,15 @@ static struct clk_lookup lookups[] = {
572 _REGISTER_CLOCK(NULL, "iim", iim_clk) 572 _REGISTER_CLOCK(NULL, "iim", iim_clk)
573 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk) 573 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
574 _REGISTER_CLOCK(NULL, "mbx", mbx_clk) 574 _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
575 _REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
576}; 575};
577 576
578int __init mx31_clocks_init(unsigned long fref) 577int __init mx31_clocks_init(unsigned long fref)
579{ 578{
580 u32 reg; 579 u32 reg;
581 int i;
582 580
583 ckih_rate = fref; 581 ckih_rate = fref;
584 582
585 for (i = 0; i < ARRAY_SIZE(lookups); i++) 583 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
586 clkdev_add(&lookups[i]);
587 584
588 /* change the csi_clk parent if necessary */ 585 /* change the csi_clk parent if necessary */
589 reg = __raw_readl(MXC_CCM_CCMR); 586 reg = __raw_readl(MXC_CCM_CCMR);
@@ -616,14 +613,17 @@ int __init mx31_clocks_init(unsigned long fref)
616 613
617 clk_enable(&serial_pll_clk); 614 clk_enable(&serial_pll_clk);
618 615
619 if (mx31_revision() >= CHIP_REV_2_0) { 616 mx31_read_cpu_rev();
617
618 if (mx31_revision() >= MX31_CHIP_REV_2_0) {
620 reg = __raw_readl(MXC_CCM_PMCR1); 619 reg = __raw_readl(MXC_CCM_PMCR1);
621 /* No PLL restart on DVFS switch; enable auto EMI handshake */ 620 /* No PLL restart on DVFS switch; enable auto EMI handshake */
622 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; 621 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
623 __raw_writel(reg, MXC_CCM_PMCR1); 622 __raw_writel(reg, MXC_CCM_PMCR1);
624 } 623 }
625 624
626 mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); 625 mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
626 MX31_INT_GPT);
627 627
628 return 0; 628 return 0;
629} 629}
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index c595260ec1f9..9f3e943e2232 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -28,7 +28,7 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/common.h> 29#include <mach/common.h>
30 30
31#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) 31#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
32 32
33#define CCM_CCMR 0x00 33#define CCM_CCMR 0x00
34#define CCM_PDR0 0x04 34#define CCM_PDR0 0x04
@@ -335,7 +335,7 @@ static void clk_cgr_disable(struct clk *clk)
335 335
336DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); 336DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL);
337DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); 337DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL);
338DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); 338/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */
339DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); 339DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL);
340DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); 340DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL);
341DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); 341DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL);
@@ -381,12 +381,43 @@ DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
381DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL); 381DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
382DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); 382DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
383DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); 383DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
384DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL); 384DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
385 385
386DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); 386DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
387DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); 387DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
388DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); 388DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
389 389
390DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL);
391
392static int clk_dummy_enable(struct clk *clk)
393{
394 return 0;
395}
396
397static void clk_dummy_disable(struct clk *clk)
398{
399}
400
401static unsigned long get_rate_nfc(struct clk *clk)
402{
403 unsigned long div1;
404
405 div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
406
407 return get_rate_ahb(NULL) / div1;
408}
409
410/* NAND Controller: It seems it can't be disabled */
411static struct clk nfc_clk = {
412 .id = 0,
413 .enable_reg = 0,
414 .enable_shift = 0,
415 .get_rate = get_rate_nfc,
416 .set_rate = NULL, /* set_rate_nfc, */
417 .enable = clk_dummy_enable,
418 .disable = clk_dummy_disable
419};
420
390#define _REGISTER_CLOCK(d, n, c) \ 421#define _REGISTER_CLOCK(d, n, c) \
391 { \ 422 { \
392 .dev_id = d, \ 423 .dev_id = d, \
@@ -397,7 +428,6 @@ DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
397static struct clk_lookup lookups[] = { 428static struct clk_lookup lookups[] = {
398 _REGISTER_CLOCK(NULL, "asrc", asrc_clk) 429 _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
399 _REGISTER_CLOCK(NULL, "ata", ata_clk) 430 _REGISTER_CLOCK(NULL, "ata", ata_clk)
400 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
401 _REGISTER_CLOCK(NULL, "can", can1_clk) 431 _REGISTER_CLOCK(NULL, "can", can1_clk)
402 _REGISTER_CLOCK(NULL, "can", can2_clk) 432 _REGISTER_CLOCK(NULL, "can", can2_clk)
403 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) 433 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
@@ -434,8 +464,8 @@ static struct clk_lookup lookups[] = {
434 _REGISTER_CLOCK(NULL, "sdma", sdma_clk) 464 _REGISTER_CLOCK(NULL, "sdma", sdma_clk)
435 _REGISTER_CLOCK(NULL, "spba", spba_clk) 465 _REGISTER_CLOCK(NULL, "spba", spba_clk)
436 _REGISTER_CLOCK(NULL, "spdif", spdif_clk) 466 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
437 _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) 467 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
438 _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) 468 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
439 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) 469 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
440 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) 470 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
441 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 471 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
@@ -443,25 +473,25 @@ static struct clk_lookup lookups[] = {
443 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) 473 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
444 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) 474 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
445 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) 475 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
476 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
446 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) 477 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
447 _REGISTER_CLOCK(NULL, "max", max_clk) 478 _REGISTER_CLOCK(NULL, "max", max_clk)
448 _REGISTER_CLOCK(NULL, "admux", admux_clk) 479 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
449 _REGISTER_CLOCK(NULL, "csi", csi_clk) 480 _REGISTER_CLOCK(NULL, "csi", csi_clk)
450 _REGISTER_CLOCK(NULL, "iim", iim_clk) 481 _REGISTER_CLOCK(NULL, "iim", iim_clk)
451 _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) 482 _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
483 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
452}; 484};
453 485
454int __init mx35_clocks_init() 486int __init mx35_clocks_init()
455{ 487{
456 int i;
457 unsigned int ll = 0; 488 unsigned int ll = 0;
458 489
459#ifdef CONFIG_DEBUG_LL_CONSOLE 490#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
460 ll = (3 << 16); 491 ll = (3 << 16);
461#endif 492#endif
462 493
463 for (i = 0; i < ARRAY_SIZE(lookups); i++) 494 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
464 clkdev_add(&lookups[i]);
465 495
466 /* Turn off all clocks except the ones we need to survive, namely: 496 /* Turn off all clocks except the ones we need to survive, namely:
467 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart 497 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
@@ -472,7 +502,8 @@ int __init mx35_clocks_init()
472 __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); 502 __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
473 __raw_writel(0, CCM_BASE + CCM_CGR3); 503 __raw_writel(0, CCM_BASE + CCM_CGR3);
474 504
475 mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); 505 mxc_timer_init(&gpt_clk,
506 MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
476 507
477 return 0; 508 return 0;
478} 509}
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
new file mode 100644
index 000000000000..861afe0fe3ad
--- /dev/null
+++ b/arch/arm/mach-mx3/cpu.c
@@ -0,0 +1,57 @@
1/*
2 * MX3 CPU type detection
3 *
4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/module.h>
13#include <linux/io.h>
14#include <mach/hardware.h>
15#include <mach/iim.h>
16
17unsigned int mx31_cpu_rev;
18EXPORT_SYMBOL(mx31_cpu_rev);
19
20struct mx3_cpu_type {
21 u8 srev;
22 const char *name;
23 const char *v;
24 unsigned int rev;
25};
26
27static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
28 { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = CHIP_REV_1_0 },
29 { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = CHIP_REV_1_1 },
30 { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = CHIP_REV_1_1 },
31 { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = CHIP_REV_1_1 },
32 { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = CHIP_REV_1_1 },
33 { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = CHIP_REV_1_2 },
34 { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = CHIP_REV_1_2 },
35 { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = CHIP_REV_2_0 },
36 { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = CHIP_REV_2_0 },
37};
38
39void __init mx31_read_cpu_rev(void)
40{
41 u32 i, srev;
42
43 /* read SREV register from IIM module */
44 srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV));
45
46 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
47 if (srev == mx31_cpu_type[i].srev) {
48 printk(KERN_INFO
49 "CPU identified as %s, silicon rev %s\n",
50 mx31_cpu_type[i].name, mx31_cpu_type[i].v);
51
52 mx31_cpu_rev = mx31_cpu_type[i].rev;
53 return;
54 }
55
56 printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
57}
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
index adfa3627ad84..37a8a07beda3 100644
--- a/arch/arm/mach-mx3/crm_regs.h
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -24,7 +24,7 @@
24#define CKIH_CLK_FREQ_27MHZ 27000000 24#define CKIH_CLK_FREQ_27MHZ 27000000
25#define CKIL_CLK_FREQ 32768 25#define CKIL_CLK_FREQ 32768
26 26
27#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) 27#define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR)
28 28
29/* Register addresses */ 29/* Register addresses */
30#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) 30#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index e6abe181b967..f8911154a9fa 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -537,16 +537,69 @@ struct platform_device mxc_fec_device = {
537}; 537};
538#endif 538#endif
539 539
540static int mx3_devices_init(void) 540static struct resource imx_ssi_resources0[] = {
541 {
542 .start = SSI1_BASE_ADDR,
543 .end = SSI1_BASE_ADDR + 0xfff,
544 .flags = IORESOURCE_MEM,
545 }, {
546 .start = MX31_INT_SSI1,
547 .end = MX31_INT_SSI1,
548 .flags = IORESOURCE_IRQ,
549 },
550};
551
552static struct resource imx_ssi_resources1[] = {
553 {
554 .start = SSI2_BASE_ADDR,
555 .end = SSI2_BASE_ADDR + 0xfff,
556 .flags = IORESOURCE_MEM
557 }, {
558 .start = MX31_INT_SSI2,
559 .end = MX31_INT_SSI2,
560 .flags = IORESOURCE_IRQ,
561 },
562};
563
564struct platform_device imx_ssi_device0 = {
565 .name = "imx-ssi",
566 .id = 0,
567 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
568 .resource = imx_ssi_resources0,
569};
570
571struct platform_device imx_ssi_device1 = {
572 .name = "imx-ssi",
573 .id = 1,
574 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
575 .resource = imx_ssi_resources1,
576};
577
578static struct resource imx_wdt_resources[] = {
579 {
580 .flags = IORESOURCE_MEM,
581 },
582};
583
584struct platform_device imx_wdt_device0 = {
585 .name = "imx-wdt",
586 .id = 0,
587 .num_resources = ARRAY_SIZE(imx_wdt_resources),
588 .resource = imx_wdt_resources,
589};
590
591static int __init mx3_devices_init(void)
541{ 592{
542 if (cpu_is_mx31()) { 593 if (cpu_is_mx31()) {
543 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; 594 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
544 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; 595 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
596 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
597 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
545 mxc_register_device(&mxc_rnga_device, NULL); 598 mxc_register_device(&mxc_rnga_device, NULL);
546 } 599 }
547 if (cpu_is_mx35()) { 600 if (cpu_is_mx35()) {
548 mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; 601 mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
549 mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff; 602 mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
550 otg_resources[0].start = MX35_OTG_BASE_ADDR; 603 otg_resources[0].start = MX35_OTG_BASE_ADDR;
551 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; 604 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
552 otg_resources[1].start = MXC_INT_USBOTG; 605 otg_resources[1].start = MXC_INT_USBOTG;
@@ -555,6 +608,12 @@ static int mx3_devices_init(void)
555 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; 608 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
556 mxc_usbh1_resources[1].start = MXC_INT_USBHS; 609 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
557 mxc_usbh1_resources[1].end = MXC_INT_USBHS; 610 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
611 imx_ssi_resources0[1].start = MX35_INT_SSI1;
612 imx_ssi_resources0[1].end = MX35_INT_SSI1;
613 imx_ssi_resources1[1].start = MX35_INT_SSI2;
614 imx_ssi_resources1[1].end = MX35_INT_SSI2;
615 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
616 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
558 } 617 }
559 618
560 return 0; 619 return 0;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index ab87419dc9a0..4f77eb501274 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -23,4 +23,7 @@ extern struct platform_device mxc_rnga_device;
23extern struct platform_device mxc_spi_device0; 23extern struct platform_device mxc_spi_device0;
24extern struct platform_device mxc_spi_device1; 24extern struct platform_device mxc_spi_device1;
25extern struct platform_device mxc_spi_device2; 25extern struct platform_device mxc_spi_device2;
26 26extern struct platform_device imx_ssi_device0;
27extern struct platform_device imx_ssi_device1;
28extern struct platform_device imx_ssi_device1;
29extern struct platform_device imx_wdt_device0;
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux-imx31.c
index c66ccbcdc11b..a1d7fa5123dc 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux-imx31.c
@@ -29,7 +29,7 @@
29/* 29/*
30 * IOMUX register (base) addresses 30 * IOMUX register (base) addresses
31 */ 31 */
32#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) 32#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
33#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) 33#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
34#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) 34#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
35#define IOMUXGPR (IOMUX_BASE + 0x008) 35#define IOMUXGPR (IOMUX_BASE + 0x008)
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 776c0ee1b3cd..5f72ec91af2d 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -33,6 +33,12 @@
33#include <linux/irq.h> 33#include <linux/irq.h>
34#include <linux/mtd/physmap.h> 34#include <linux/mtd/physmap.h>
35#include <linux/io.h> 35#include <linux/io.h>
36#include <linux/input.h>
37#include <linux/gpio_keys.h>
38#include <linux/i2c.h>
39#include <linux/usb/otg.h>
40#include <linux/usb/ulpi.h>
41#include <linux/delay.h>
36 42
37#include <mach/hardware.h> 43#include <mach/hardware.h>
38#include <asm/mach-types.h> 44#include <asm/mach-types.h>
@@ -49,6 +55,8 @@
49#include <mach/ipu.h> 55#include <mach/ipu.h>
50#include <mach/mx3fb.h> 56#include <mach/mx3fb.h>
51#include <mach/mxc_nand.h> 57#include <mach/mxc_nand.h>
58#include <mach/mxc_ehci.h>
59#include <mach/ulpi.h>
52 60
53#include "devices.h" 61#include "devices.h"
54#include "crm_regs.h" 62#include "crm_regs.h"
@@ -97,6 +105,197 @@ static int armadillo5x0_pins[] = {
97 MX31_PIN_FPSHIFT__FPSHIFT, 105 MX31_PIN_FPSHIFT__FPSHIFT,
98 MX31_PIN_DRDY0__DRDY0, 106 MX31_PIN_DRDY0__DRDY0,
99 IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ 107 IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
108 /* I2C2 */
109 MX31_PIN_CSPI2_MOSI__SCL,
110 MX31_PIN_CSPI2_MISO__SDA,
111 /* OTG */
112 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
113 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
114 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
115 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
116 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
117 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
118 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
119 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
120 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
121 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
122 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
123 MX31_PIN_USBOTG_STP__USBOTG_STP,
124 /* USB host 2 */
125 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
126 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
127 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
128 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
129 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
130 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
131 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
132 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
133 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
134 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
135 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
136 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
137};
138
139/* USB */
140#if defined(CONFIG_USB_ULPI)
141
142#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
143#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
144#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
145
146#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
147 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
148
149static int usbotg_init(struct platform_device *pdev)
150{
151 int err;
152
153 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
154 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
155 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
156 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
157 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
160 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
161 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
162 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
163 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
164 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
165
166 /* Chip already enabled by hardware */
167 /* OTG phy reset*/
168 err = gpio_request(OTG_RESET, "USB-OTG-RESET");
169 if (err) {
170 pr_err("Failed to request the usb otg reset gpio\n");
171 return err;
172 }
173
174 err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
175 if (err) {
176 pr_err("Failed to reset the usb otg phy\n");
177 goto otg_free_reset;
178 }
179
180 gpio_set_value(OTG_RESET, 0/*LOW*/);
181 mdelay(5);
182 gpio_set_value(OTG_RESET, 1/*HIGH*/);
183
184 return 0;
185
186otg_free_reset:
187 gpio_free(OTG_RESET);
188 return err;
189}
190
191static int usbh2_init(struct platform_device *pdev)
192{
193 int err;
194
195 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
196 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
197 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
198 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
199 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
200 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
201 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
202 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
203 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
204 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
205 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
206 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
207
208 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
209
210
211 /* Enable the chip */
212 err = gpio_request(USBH2_CS, "USB-H2-CS");
213 if (err) {
214 pr_err("Failed to request the usb host 2 CS gpio\n");
215 return err;
216 }
217
218 err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
219 if (err) {
220 pr_err("Failed to drive the usb host 2 CS gpio\n");
221 goto h2_free_cs;
222 }
223
224 /* H2 phy reset*/
225 err = gpio_request(USBH2_RESET, "USB-H2-RESET");
226 if (err) {
227 pr_err("Failed to request the usb host 2 reset gpio\n");
228 goto h2_free_cs;
229 }
230
231 err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
232 if (err) {
233 pr_err("Failed to reset the usb host 2 phy\n");
234 goto h2_free_reset;
235 }
236
237 gpio_set_value(USBH2_RESET, 0/*LOW*/);
238 mdelay(5);
239 gpio_set_value(USBH2_RESET, 1/*HIGH*/);
240
241 return 0;
242
243h2_free_reset:
244 gpio_free(USBH2_RESET);
245h2_free_cs:
246 gpio_free(USBH2_CS);
247 return err;
248}
249
250static struct mxc_usbh_platform_data usbotg_pdata = {
251 .init = usbotg_init,
252 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
253 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
254};
255
256static struct mxc_usbh_platform_data usbh2_pdata = {
257 .init = usbh2_init,
258 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
259 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
260};
261#endif /* CONFIG_USB_ULPI */
262
263/* RTC over I2C*/
264#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
265
266static struct i2c_board_info armadillo5x0_i2c_rtc = {
267 I2C_BOARD_INFO("s35390a", 0x30),
268};
269
270/* GPIO BUTTONS */
271static struct gpio_keys_button armadillo5x0_buttons[] = {
272 {
273 .code = KEY_ENTER, /*28*/
274 .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0),
275 .active_low = 1,
276 .desc = "menu",
277 .wakeup = 1,
278 }, {
279 .code = KEY_BACK, /*158*/
280 .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0),
281 .active_low = 1,
282 .desc = "back",
283 .wakeup = 1,
284 }
285};
286
287static struct gpio_keys_platform_data armadillo5x0_button_data = {
288 .buttons = armadillo5x0_buttons,
289 .nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
290};
291
292static struct platform_device armadillo5x0_button_device = {
293 .name = "gpio-keys",
294 .id = -1,
295 .num_resources = 0,
296 .dev = {
297 .platform_data = &armadillo5x0_button_data,
298 }
100}; 299};
101 300
102/* 301/*
@@ -138,8 +337,8 @@ static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
138 337
139static struct resource armadillo5x0_nor_flash_resource = { 338static struct resource armadillo5x0_nor_flash_resource = {
140 .flags = IORESOURCE_MEM, 339 .flags = IORESOURCE_MEM,
141 .start = CS0_BASE_ADDR, 340 .start = MX31_CS0_BASE_ADDR,
142 .end = CS0_BASE_ADDR + SZ_64M - 1, 341 .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
143}; 342};
144 343
145static struct platform_device armadillo5x0_nor_flash = { 344static struct platform_device armadillo5x0_nor_flash = {
@@ -267,8 +466,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
267 */ 466 */
268static struct resource armadillo5x0_smc911x_resources[] = { 467static struct resource armadillo5x0_smc911x_resources[] = {
269 { 468 {
270 .start = CS3_BASE_ADDR, 469 .start = MX31_CS3_BASE_ADDR,
271 .end = CS3_BASE_ADDR + SZ_32M - 1, 470 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
272 .flags = IORESOURCE_MEM, 471 .flags = IORESOURCE_MEM,
273 }, { 472 }, {
274 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), 473 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
@@ -278,7 +477,7 @@ static struct resource armadillo5x0_smc911x_resources[] = {
278}; 477};
279 478
280static struct smsc911x_platform_config smsc911x_info = { 479static struct smsc911x_platform_config smsc911x_info = {
281 .flags = SMSC911X_USE_32BIT, 480 .flags = SMSC911X_USE_16BIT,
282 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 481 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
283 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 482 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
284}; 483};
@@ -300,6 +499,8 @@ static struct imxuart_platform_data uart_pdata = {
300 499
301static struct platform_device *devices[] __initdata = { 500static struct platform_device *devices[] __initdata = {
302 &armadillo5x0_smc911x_device, 501 &armadillo5x0_smc911x_device,
502 &mxc_i2c_device1,
503 &armadillo5x0_button_device,
303}; 504};
304 505
305/* 506/*
@@ -335,6 +536,29 @@ static void __init armadillo5x0_init(void)
335 536
336 /* set NAND page size to 2k if not configured via boot mode pins */ 537 /* set NAND page size to 2k if not configured via boot mode pins */
337 __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); 538 __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
539
540 /* RTC */
541 /* Get RTC IRQ and register the chip */
542 if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) {
543 if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0)
544 armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO);
545 else
546 gpio_free(ARMADILLO5X0_RTC_GPIO);
547 }
548 if (armadillo5x0_i2c_rtc.irq == 0)
549 pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
550 i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
551
552 /* USB */
553#if defined(CONFIG_USB_ULPI)
554 usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
555 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
556 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
557 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
558
559 mxc_register_device(&mxc_otg_host, &usbotg_pdata);
560 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
561#endif
338} 562}
339 563
340static void __init armadillo5x0_timer_init(void) 564static void __init armadillo5x0_timer_init(void)
@@ -348,9 +572,9 @@ static struct sys_timer armadillo5x0_timer = {
348 572
349MACHINE_START(ARMADILLO5X0, "Armadillo-500") 573MACHINE_START(ARMADILLO5X0, "Armadillo-500")
350 /* Maintainer: Alberto Panizzo */ 574 /* Maintainer: Alberto Panizzo */
351 .phys_io = AIPS1_BASE_ADDR, 575 .phys_io = MX31_AIPS1_BASE_ADDR,
352 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 576 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
353 .boot_params = PHYS_OFFSET + 0x00000100, 577 .boot_params = MX3x_PHYS_OFFSET + 0x100,
354 .map_io = mx31_map_io, 578 .map_io = mx31_map_io,
355 .init_irq = mx31_init_irq, 579 .init_irq = mx31_init_irq,
356 .timer = &armadillo5x0_timer, 580 .timer = &armadillo5x0_timer,
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
new file mode 100644
index 000000000000..f085d5d1a6de
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -0,0 +1,273 @@
1/*
2 * KZM-ARM11-01 support
3 * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
4 *
5 * based on code for MX31ADS,
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/platform_device.h>
28#include <linux/serial_8250.h>
29#include <linux/smsc911x.h>
30#include <linux/types.h>
31
32#include <asm/irq.h>
33#include <asm/mach-types.h>
34#include <asm/setup.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/irq.h>
37#include <asm/mach/map.h>
38#include <asm/mach/time.h>
39
40#include <mach/board-kzmarm11.h>
41#include <mach/clock.h>
42#include <mach/common.h>
43#include <mach/imx-uart.h>
44#include <mach/iomux-mx3.h>
45#include <mach/memory.h>
46
47#include "devices.h"
48
49#define KZM_ARM11_IO_ADDRESS(x) ( \
50 IMX_IO_ADDRESS(x, MX31_CS4) ?: \
51 IMX_IO_ADDRESS(x, MX31_CS5) ?: \
52 MX31_IO_ADDRESS(x))
53
54#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
55/*
56 * KZM-ARM11-01 has an external UART on FPGA
57 */
58static struct plat_serial8250_port serial_platform_data[] = {
59 {
60 .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
61 .mapbase = KZM_ARM11_16550,
62 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
63 .irqflags = IRQ_TYPE_EDGE_RISING,
64 .uartclk = 14745600,
65 .regshift = 0,
66 .iotype = UPIO_MEM,
67 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
68 UPF_BUGGY_UART,
69 },
70 {},
71};
72
73static struct resource serial8250_resources[] = {
74 {
75 .start = KZM_ARM11_16550,
76 .end = KZM_ARM11_16550 + 0x10,
77 .flags = IORESOURCE_MEM,
78 },
79 {
80 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
81 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
82 .flags = IORESOURCE_IRQ,
83 },
84};
85
86static struct platform_device serial_device = {
87 .name = "serial8250",
88 .id = PLAT8250_DEV_PLATFORM,
89 .dev = {
90 .platform_data = serial_platform_data,
91 },
92 .num_resources = ARRAY_SIZE(serial8250_resources),
93 .resource = serial8250_resources,
94};
95
96static int __init kzm_init_ext_uart(void)
97{
98 u8 tmp;
99
100 /*
101 * GPIO 1-1: external UART interrupt line
102 */
103 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
104 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
105 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
106
107 /*
108 * Unmask UART interrupt
109 */
110 tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
111 tmp |= 0x2;
112 __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
113
114 return platform_device_register(&serial_device);
115}
116#else
117static inline int kzm_init_ext_uart(void)
118{
119 return 0;
120}
121#endif
122
123/*
124 * SMSC LAN9118
125 */
126#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
127static struct smsc911x_platform_config kzm_smsc9118_config = {
128 .phy_interface = PHY_INTERFACE_MODE_MII,
129 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
130 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
131 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
132};
133
134static struct resource kzm_smsc9118_resources[] = {
135 {
136 .start = MX31_CS5_BASE_ADDR,
137 .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
138 .flags = IORESOURCE_MEM,
139 },
140 {
141 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
142 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
143 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
144 },
145};
146
147static struct platform_device kzm_smsc9118_device = {
148 .name = "smsc911x",
149 .id = -1,
150 .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
151 .resource = kzm_smsc9118_resources,
152 .dev = {
153 .platform_data = &kzm_smsc9118_config,
154 },
155};
156
157static int __init kzm_init_smsc9118(void)
158{
159 /*
160 * GPIO 1-2: SMSC9118 interrupt line
161 */
162 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
163 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
164 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
165
166 return platform_device_register(&kzm_smsc9118_device);
167}
168#else
169static inline int kzm_init_smsc9118(void)
170{
171 return 0;
172}
173#endif
174
175#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
176static struct imxuart_platform_data uart_pdata = {
177 .flags = IMXUART_HAVE_RTSCTS,
178};
179
180static void __init kzm_init_imx_uart(void)
181{
182 mxc_register_device(&mxc_uart_device0, &uart_pdata);
183
184 mxc_register_device(&mxc_uart_device1, &uart_pdata);
185}
186#else
187static inline void kzm_init_imx_uart(void)
188{
189}
190#endif
191
192static int kzm_pins[] __initdata = {
193 MX31_PIN_CTS1__CTS1,
194 MX31_PIN_RTS1__RTS1,
195 MX31_PIN_TXD1__TXD1,
196 MX31_PIN_RXD1__RXD1,
197 MX31_PIN_DCD_DCE1__DCD_DCE1,
198 MX31_PIN_RI_DCE1__RI_DCE1,
199 MX31_PIN_DSR_DCE1__DSR_DCE1,
200 MX31_PIN_DTR_DCE1__DTR_DCE1,
201 MX31_PIN_CTS2__CTS2,
202 MX31_PIN_RTS2__RTS2,
203 MX31_PIN_TXD2__TXD2,
204 MX31_PIN_RXD2__RXD2,
205 MX31_PIN_DCD_DTE1__DCD_DTE2,
206 MX31_PIN_RI_DTE1__RI_DTE2,
207 MX31_PIN_DSR_DTE1__DSR_DTE2,
208 MX31_PIN_DTR_DTE1__DTR_DTE2,
209};
210
211/*
212 * Board specific initialization.
213 */
214static void __init kzm_board_init(void)
215{
216 mxc_iomux_setup_multiple_pins(kzm_pins,
217 ARRAY_SIZE(kzm_pins), "kzm");
218 kzm_init_ext_uart();
219 kzm_init_smsc9118();
220 kzm_init_imx_uart();
221
222 pr_info("Clock input source is 26MHz\n");
223}
224
225/*
226 * This structure defines static mappings for the kzm-arm11-01 board.
227 */
228static struct map_desc kzm_io_desc[] __initdata = {
229 {
230 .virtual = MX31_CS4_BASE_ADDR_VIRT,
231 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
232 .length = MX31_CS4_SIZE,
233 .type = MT_DEVICE
234 },
235 {
236 .virtual = MX31_CS5_BASE_ADDR_VIRT,
237 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
238 .length = MX31_CS5_SIZE,
239 .type = MT_DEVICE
240 },
241};
242
243/*
244 * Set up static virtual mappings.
245 */
246static void __init kzm_map_io(void)
247{
248 mx31_map_io();
249 iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
250}
251
252static void __init kzm_timer_init(void)
253{
254 mx31_clocks_init(26000000);
255}
256
257static struct sys_timer kzm_timer = {
258 .init = kzm_timer_init,
259};
260
261/*
262 * The following uses standard kernel macros define in arch.h in order to
263 * initialize __mach_desc_KZM_ARM11_01 data structure.
264 */
265MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
266 .phys_io = MX31_AIPS1_BASE_ADDR,
267 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
268 .boot_params = MX3x_PHYS_OFFSET + 0x100,
269 .map_io = kzm_map_io,
270 .init_irq = mx31_init_irq,
271 .init_machine = kzm_board_init,
272 .timer = &kzm_timer,
273MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 0f7a2f06bc2d..f54af1e29ca4 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -23,6 +23,9 @@
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <linux/smsc911x.h> 24#include <linux/smsc911x.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/mfd/mc13783.h>
27#include <linux/spi/spi.h>
28#include <linux/regulator/machine.h>
26 29
27#include <mach/hardware.h> 30#include <mach/hardware.h>
28#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -31,26 +34,96 @@
31#include <asm/memory.h> 34#include <asm/memory.h>
32#include <asm/mach/map.h> 35#include <asm/mach/map.h>
33#include <mach/common.h> 36#include <mach/common.h>
34#include <mach/board-mx31pdk.h> 37#include <mach/board-mx31_3ds.h>
35#include <mach/imx-uart.h> 38#include <mach/imx-uart.h>
36#include <mach/iomux-mx3.h> 39#include <mach/iomux-mx3.h>
40#include <mach/mxc_nand.h>
41#include <mach/spi.h>
37#include "devices.h" 42#include "devices.h"
38 43
39/*! 44/*!
40 * @file mx31pdk.c 45 * @file mx31_3ds.c
41 * 46 *
42 * @brief This file contains the board-specific initialization routines. 47 * @brief This file contains the board-specific initialization routines.
43 * 48 *
44 * @ingroup System 49 * @ingroup System
45 */ 50 */
46 51
47static int mx31pdk_pins[] = { 52static int mx31_3ds_pins[] = {
48 /* UART1 */ 53 /* UART1 */
49 MX31_PIN_CTS1__CTS1, 54 MX31_PIN_CTS1__CTS1,
50 MX31_PIN_RTS1__RTS1, 55 MX31_PIN_RTS1__RTS1,
51 MX31_PIN_TXD1__TXD1, 56 MX31_PIN_TXD1__TXD1,
52 MX31_PIN_RXD1__RXD1, 57 MX31_PIN_RXD1__RXD1,
53 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), 58 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
59 /* SPI 1 */
60 MX31_PIN_CSPI2_SCLK__SCLK,
61 MX31_PIN_CSPI2_MOSI__MOSI,
62 MX31_PIN_CSPI2_MISO__MISO,
63 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
64 MX31_PIN_CSPI2_SS0__SS0,
65 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
66 /* MC13783 IRQ */
67 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
68};
69
70/* Regulators */
71static struct regulator_init_data pwgtx_init = {
72 .constraints = {
73 .boot_on = 1,
74 .always_on = 1,
75 },
76};
77
78static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
79 {
80 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
81 .init_data = &pwgtx_init,
82 }, {
83 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
84 .init_data = &pwgtx_init,
85 },
86};
87
88/* MC13783 */
89static struct mc13783_platform_data mc13783_pdata __initdata = {
90 .regulators = mx31_3ds_regulators,
91 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
92 .flags = MC13783_USE_REGULATOR,
93};
94
95/* SPI */
96static int spi1_internal_chipselect[] = {
97 MXC_SPI_CS(0),
98 MXC_SPI_CS(2),
99};
100
101static struct spi_imx_master spi1_pdata = {
102 .chipselect = spi1_internal_chipselect,
103 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
104};
105
106static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
107 {
108 .modalias = "mc13783",
109 .max_speed_hz = 1000000,
110 .bus_num = 1,
111 .chip_select = 1, /* SS2 */
112 .platform_data = &mc13783_pdata,
113 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
114 .mode = SPI_CS_HIGH,
115 },
116};
117
118/*
119 * NAND Flash
120 */
121static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
122 .width = 1,
123 .hw_ecc = 1,
124#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
125 .flash_bbt = 1,
126#endif
54}; 127};
55 128
56static struct imxuart_platform_data uart_pdata = { 129static struct imxuart_platform_data uart_pdata = {
@@ -95,7 +168,7 @@ static struct platform_device smsc911x_device = {
95 * LEDs, switches, interrupts for Ethernet. 168 * LEDs, switches, interrupts for Ethernet.
96 */ 169 */
97 170
98static void mx31pdk_expio_irq_handler(uint32_t irq, struct irq_desc *desc) 171static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
99{ 172{
100 uint32_t imr_val; 173 uint32_t imr_val;
101 uint32_t int_valid; 174 uint32_t int_valid;
@@ -163,7 +236,7 @@ static struct irq_chip expio_irq_chip = {
163 .unmask = expio_unmask_irq, 236 .unmask = expio_unmask_irq,
164}; 237};
165 238
166static int __init mx31pdk_init_expio(void) 239static int __init mx31_3ds_init_expio(void)
167{ 240{
168 int i; 241 int i;
169 int ret; 242 int ret;
@@ -176,7 +249,7 @@ static int __init mx31pdk_init_expio(void)
176 return -ENODEV; 249 return -ENODEV;
177 } 250 }
178 251
179 pr_info("i.MX31PDK Debug board detected, rev = 0x%04X\n", 252 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
180 __raw_readw(CPLD_CODE_VER_REG)); 253 __raw_readw(CPLD_CODE_VER_REG));
181 254
182 /* 255 /*
@@ -201,7 +274,7 @@ static int __init mx31pdk_init_expio(void)
201 set_irq_flags(i, IRQF_VALID); 274 set_irq_flags(i, IRQF_VALID);
202 } 275 }
203 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW); 276 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
204 set_irq_chained_handler(EXPIO_PARENT_INT, mx31pdk_expio_irq_handler); 277 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
205 278
206 return 0; 279 return 0;
207} 280}
@@ -209,16 +282,11 @@ static int __init mx31pdk_init_expio(void)
209/* 282/*
210 * This structure defines the MX31 memory map. 283 * This structure defines the MX31 memory map.
211 */ 284 */
212static struct map_desc mx31pdk_io_desc[] __initdata = { 285static struct map_desc mx31_3ds_io_desc[] __initdata = {
213 { 286 {
214 .virtual = SPBA0_BASE_ADDR_VIRT, 287 .virtual = MX31_CS5_BASE_ADDR_VIRT,
215 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), 288 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
216 .length = SPBA0_SIZE, 289 .length = MX31_CS5_SIZE,
217 .type = MT_DEVICE_NONSHARED,
218 }, {
219 .virtual = CS5_BASE_ADDR_VIRT,
220 .pfn = __phys_to_pfn(CS5_BASE_ADDR),
221 .length = CS5_SIZE,
222 .type = MT_DEVICE, 290 .type = MT_DEVICE,
223 }, 291 },
224}; 292};
@@ -226,10 +294,10 @@ static struct map_desc mx31pdk_io_desc[] __initdata = {
226/* 294/*
227 * Set up static virtual mappings. 295 * Set up static virtual mappings.
228 */ 296 */
229static void __init mx31pdk_map_io(void) 297static void __init mx31_3ds_map_io(void)
230{ 298{
231 mx31_map_io(); 299 mx31_map_io();
232 iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); 300 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
233} 301}
234 302
235/*! 303/*!
@@ -237,35 +305,40 @@ static void __init mx31pdk_map_io(void)
237 */ 305 */
238static void __init mxc_board_init(void) 306static void __init mxc_board_init(void)
239{ 307{
240 mxc_iomux_setup_multiple_pins(mx31pdk_pins, ARRAY_SIZE(mx31pdk_pins), 308 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
241 "mx31pdk"); 309 "mx31_3ds");
242 310
243 mxc_register_device(&mxc_uart_device0, &uart_pdata); 311 mxc_register_device(&mxc_uart_device0, &uart_pdata);
312 mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
313
314 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
315 spi_register_board_info(mx31_3ds_spi_devs,
316 ARRAY_SIZE(mx31_3ds_spi_devs));
244 317
245 if (!mx31pdk_init_expio()) 318 if (!mx31_3ds_init_expio())
246 platform_device_register(&smsc911x_device); 319 platform_device_register(&smsc911x_device);
247} 320}
248 321
249static void __init mx31pdk_timer_init(void) 322static void __init mx31_3ds_timer_init(void)
250{ 323{
251 mx31_clocks_init(26000000); 324 mx31_clocks_init(26000000);
252} 325}
253 326
254static struct sys_timer mx31pdk_timer = { 327static struct sys_timer mx31_3ds_timer = {
255 .init = mx31pdk_timer_init, 328 .init = mx31_3ds_timer_init,
256}; 329};
257 330
258/* 331/*
259 * The following uses standard kernel macros defined in arch.h in order to 332 * The following uses standard kernel macros defined in arch.h in order to
260 * initialize __mach_desc_MX31PDK data structure. 333 * initialize __mach_desc_MX31_3DS data structure.
261 */ 334 */
262MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") 335MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
263 /* Maintainer: Freescale Semiconductor, Inc. */ 336 /* Maintainer: Freescale Semiconductor, Inc. */
264 .phys_io = AIPS1_BASE_ADDR, 337 .phys_io = MX31_AIPS1_BASE_ADDR,
265 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 338 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
266 .boot_params = PHYS_OFFSET + 0x100, 339 .boot_params = MX3x_PHYS_OFFSET + 0x100,
267 .map_io = mx31pdk_map_io, 340 .map_io = mx31_3ds_map_io,
268 .init_irq = mx31_init_irq, 341 .init_irq = mx31_init_irq,
269 .init_machine = mxc_board_init, 342 .init_machine = mxc_board_init,
270 .timer = &mx31pdk_timer, 343 .timer = &mx31_3ds_timer,
271MACHINE_END 344MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 0497c152be18..b3d1a1895c20 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -60,7 +60,7 @@
60static struct plat_serial8250_port serial_platform_data[] = { 60static struct plat_serial8250_port serial_platform_data[] = {
61 { 61 {
62 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), 62 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
63 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA), 63 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
64 .irq = EXPIO_INT_XUART_INTA, 64 .irq = EXPIO_INT_XUART_INTA,
65 .uartclk = 14745600, 65 .uartclk = 14745600,
66 .regshift = 0, 66 .regshift = 0,
@@ -68,7 +68,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, 68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
69 }, { 69 }, {
70 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), 70 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
71 .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB), 71 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
72 .irq = EXPIO_INT_XUART_INTB, 72 .irq = EXPIO_INT_XUART_INTB,
73 .uartclk = 14745600, 73 .uartclk = 14745600,
74 .regshift = 0, 74 .regshift = 0,
@@ -173,6 +173,7 @@ static void expio_unmask_irq(u32 irq)
173} 173}
174 174
175static struct irq_chip expio_irq_chip = { 175static struct irq_chip expio_irq_chip = {
176 .name = "EXPIO(CPLD)",
176 .ack = expio_ack_irq, 177 .ack = expio_ack_irq,
177 .mask = expio_mask_irq, 178 .mask = expio_mask_irq,
178 .unmask = expio_unmask_irq, 179 .unmask = expio_unmask_irq,
@@ -302,17 +303,14 @@ static struct regulator_init_data ldo1_data = {
302 .min_uV = 2800000, 303 .min_uV = 2800000,
303 .max_uV = 2800000, 304 .max_uV = 2800000,
304 .valid_modes_mask = REGULATOR_MODE_NORMAL, 305 .valid_modes_mask = REGULATOR_MODE_NORMAL,
306 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
305 .apply_uV = 1, 307 .apply_uV = 1,
306 }, 308 },
307}; 309};
308 310
309static struct regulator_consumer_supply ldo2_consumers[] = { 311static struct regulator_consumer_supply ldo2_consumers[] = {
310 { 312 { .supply = "AVDD", .dev_name = "1-001a" },
311 .supply = "AVDD", 313 { .supply = "HPVDD", .dev_name = "1-001a" },
312 },
313 {
314 .supply = "HPVDD",
315 },
316}; 314};
317 315
318/* CODEC and SIM */ 316/* CODEC and SIM */
@@ -322,6 +320,7 @@ static struct regulator_init_data ldo2_data = {
322 .min_uV = 3300000, 320 .min_uV = 3300000,
323 .max_uV = 3300000, 321 .max_uV = 3300000,
324 .valid_modes_mask = REGULATOR_MODE_NORMAL, 322 .valid_modes_mask = REGULATOR_MODE_NORMAL,
323 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
325 .apply_uV = 1, 324 .apply_uV = 1,
326 }, 325 },
327 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), 326 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
@@ -382,8 +381,6 @@ static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
382 381
383static int mx31_wm8350_init(struct wm8350 *wm8350) 382static int mx31_wm8350_init(struct wm8350 *wm8350)
384{ 383{
385 int i;
386
387 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, 384 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
388 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, 385 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
389 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, 386 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
@@ -419,10 +416,6 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
419 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, 416 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
420 WM8350_GPIO_DEBOUNCE_OFF); 417 WM8350_GPIO_DEBOUNCE_OFF);
421 418
422 /* Fix up for our own supplies. */
423 for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++)
424 ldo2_consumers[i].dev = wm8350->dev;
425
426 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); 419 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
427 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); 420 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
428 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); 421 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
@@ -459,6 +452,7 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
459 452
460static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { 453static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
461 .init = mx31_wm8350_init, 454 .init = mx31_wm8350_init,
455 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
462}; 456};
463#endif 457#endif
464 458
@@ -489,19 +483,27 @@ static void mxc_init_i2c(void)
489} 483}
490#endif 484#endif
491 485
486static unsigned int ssi_pins[] = {
487 MX31_PIN_SFS5__SFS5,
488 MX31_PIN_SCK5__SCK5,
489 MX31_PIN_SRXD5__SRXD5,
490 MX31_PIN_STXD5__STXD5,
491};
492
493static void mxc_init_audio(void)
494{
495 mxc_register_device(&imx_ssi_device0, NULL);
496 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
497}
498
492/*! 499/*!
493 * This structure defines static mappings for the i.MX31ADS board. 500 * This structure defines static mappings for the i.MX31ADS board.
494 */ 501 */
495static struct map_desc mx31ads_io_desc[] __initdata = { 502static struct map_desc mx31ads_io_desc[] __initdata = {
496 { 503 {
497 .virtual = SPBA0_BASE_ADDR_VIRT, 504 .virtual = MX31_CS4_BASE_ADDR_VIRT,
498 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), 505 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
499 .length = SPBA0_SIZE, 506 .length = MX31_CS4_SIZE / 2,
500 .type = MT_DEVICE_NONSHARED
501 }, {
502 .virtual = CS4_BASE_ADDR_VIRT,
503 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
504 .length = CS4_SIZE / 2,
505 .type = MT_DEVICE 507 .type = MT_DEVICE
506 }, 508 },
507}; 509};
@@ -529,6 +531,7 @@ static void __init mxc_board_init(void)
529 mxc_init_extuart(); 531 mxc_init_extuart();
530 mxc_init_imx_uart(); 532 mxc_init_imx_uart();
531 mxc_init_i2c(); 533 mxc_init_i2c();
534 mxc_init_audio();
532} 535}
533 536
534static void __init mx31ads_timer_init(void) 537static void __init mx31ads_timer_init(void)
@@ -546,9 +549,9 @@ static struct sys_timer mx31ads_timer = {
546 */ 549 */
547MACHINE_START(MX31ADS, "Freescale MX31ADS") 550MACHINE_START(MX31ADS, "Freescale MX31ADS")
548 /* Maintainer: Freescale Semiconductor, Inc. */ 551 /* Maintainer: Freescale Semiconductor, Inc. */
549 .phys_io = AIPS1_BASE_ADDR, 552 .phys_io = MX31_AIPS1_BASE_ADDR,
550 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 553 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
551 .boot_params = PHYS_OFFSET + 0x100, 554 .boot_params = MX3x_PHYS_OFFSET + 0x100,
552 .map_io = mx31ads_map_io, 555 .map_io = mx31ads_map_io,
553 .init_irq = mx31ads_init_irq, 556 .init_irq = mx31ads_init_irq,
554 .init_machine = mxc_board_init, 557 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 423025150f6f..80847b04c063 100644
--- a/arch/arm/mach-mx3/mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -31,6 +31,8 @@
31#include <linux/interrupt.h> 31#include <linux/interrupt.h>
32#include <linux/smsc911x.h> 32#include <linux/smsc911x.h>
33#include <linux/mtd/physmap.h> 33#include <linux/mtd/physmap.h>
34#include <linux/spi/spi.h>
35#include <linux/mfd/mc13783.h>
34 36
35#include <asm/mach-types.h> 37#include <asm/mach-types.h>
36#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
@@ -41,6 +43,7 @@
41#include <mach/common.h> 43#include <mach/common.h>
42#include <mach/iomux-mx3.h> 44#include <mach/iomux-mx3.h>
43#include <mach/board-mx31lilly.h> 45#include <mach/board-mx31lilly.h>
46#include <mach/spi.h>
44 47
45#include "devices.h" 48#include "devices.h"
46 49
@@ -54,8 +57,8 @@
54 57
55static struct resource smsc91x_resources[] = { 58static struct resource smsc91x_resources[] = {
56 { 59 {
57 .start = CS4_BASE_ADDR, 60 .start = MX31_CS4_BASE_ADDR,
58 .end = CS4_BASE_ADDR + 0xffff, 61 .end = MX31_CS4_BASE_ADDR + 0xffff,
59 .flags = IORESOURCE_MEM, 62 .flags = IORESOURCE_MEM,
60 }, 63 },
61 { 64 {
@@ -108,7 +111,36 @@ static struct platform_device physmap_flash_device = {
108static struct platform_device *devices[] __initdata = { 111static struct platform_device *devices[] __initdata = {
109 &smsc91x_device, 112 &smsc91x_device,
110 &physmap_flash_device, 113 &physmap_flash_device,
111 &mxc_i2c_device1, 114};
115
116/* SPI */
117
118static int spi_internal_chipselect[] = {
119 MXC_SPI_CS(0),
120 MXC_SPI_CS(1),
121 MXC_SPI_CS(2),
122};
123
124static struct spi_imx_master spi0_pdata = {
125 .chipselect = spi_internal_chipselect,
126 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
127};
128
129static struct spi_imx_master spi1_pdata = {
130 .chipselect = spi_internal_chipselect,
131 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
132};
133
134static struct mc13783_platform_data mc13783_pdata __initdata = {
135 .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN,
136};
137
138static struct spi_board_info mc13783_dev __initdata = {
139 .modalias = "mc13783",
140 .max_speed_hz = 1000000,
141 .bus_num = 1,
142 .chip_select = 0,
143 .platform_data = &mc13783_pdata,
112}; 144};
113 145
114static int mx31lilly_baseboard; 146static int mx31lilly_baseboard;
@@ -128,8 +160,27 @@ static void __init mx31lilly_board_init(void)
128 } 160 }
129 161
130 mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); 162 mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
131 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__SCL, "I2C SCL"); 163
132 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__SDA, "I2C SDA"); 164 /* SPI */
165 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
166 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
167 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
168 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
169 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
170 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
171 mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
172
173 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
174 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
175 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
176 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
177 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
178 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
179 mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
180
181 mxc_register_device(&mxc_spi_device0, &spi0_pdata);
182 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
183 spi_register_board_info(&mc13783_dev, 1);
133 184
134 platform_add_devices(devices, ARRAY_SIZE(devices)); 185 platform_add_devices(devices, ARRAY_SIZE(devices));
135} 186}
@@ -144,9 +195,9 @@ static struct sys_timer mx31lilly_timer = {
144}; 195};
145 196
146MACHINE_START(LILLY1131, "INCO startec LILLY-1131") 197MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
147 .phys_io = AIPS1_BASE_ADDR, 198 .phys_io = MX31_AIPS1_BASE_ADDR,
148 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 199 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
149 .boot_params = PHYS_OFFSET + 0x100, 200 .boot_params = MX3x_PHYS_OFFSET + 0x100,
150 .map_io = mx31_map_io, 201 .map_io = mx31_map_io,
151 .init_irq = mx31_init_irq, 202 .init_irq = mx31_init_irq,
152 .init_machine = mx31lilly_board_init, 203 .init_machine = mx31lilly_board_init,
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
new file mode 100644
index 000000000000..2b6d11400877
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -0,0 +1,297 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/memory.h>
26#include <linux/platform_device.h>
27#include <linux/gpio.h>
28#include <linux/smsc911x.h>
29#include <linux/mfd/mc13783.h>
30#include <linux/spi/spi.h>
31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
33#include <linux/mtd/physmap.h>
34
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/time.h>
38#include <asm/mach/map.h>
39#include <asm/page.h>
40#include <asm/setup.h>
41
42#include <mach/hardware.h>
43#include <mach/common.h>
44#include <mach/board-mx31lite.h>
45#include <mach/imx-uart.h>
46#include <mach/iomux-mx3.h>
47#include <mach/irqs.h>
48#include <mach/mxc_nand.h>
49#include <mach/spi.h>
50#include <mach/mxc_ehci.h>
51#include <mach/ulpi.h>
52
53#include "devices.h"
54
55/*
56 * This file contains the module-specific initialization routines.
57 */
58
59static unsigned int mx31lite_pins[] = {
60 /* LAN9117 IRQ pin */
61 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
62 /* SPI 1 */
63 MX31_PIN_CSPI2_SCLK__SCLK,
64 MX31_PIN_CSPI2_MOSI__MOSI,
65 MX31_PIN_CSPI2_MISO__MISO,
66 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
67 MX31_PIN_CSPI2_SS0__SS0,
68 MX31_PIN_CSPI2_SS1__SS1,
69 MX31_PIN_CSPI2_SS2__SS2,
70};
71
72static struct mxc_nand_platform_data mx31lite_nand_board_info = {
73 .width = 1,
74 .hw_ecc = 1,
75};
76
77static struct smsc911x_platform_config smsc911x_config = {
78 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
79 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
80 .flags = SMSC911X_USE_16BIT,
81};
82
83static struct resource smsc911x_resources[] = {
84 {
85 .start = MX31_CS4_BASE_ADDR,
86 .end = MX31_CS4_BASE_ADDR + 0x100,
87 .flags = IORESOURCE_MEM,
88 }, {
89 .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
90 .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device smsc911x_device = {
96 .name = "smsc911x",
97 .id = -1,
98 .num_resources = ARRAY_SIZE(smsc911x_resources),
99 .resource = smsc911x_resources,
100 .dev = {
101 .platform_data = &smsc911x_config,
102 },
103};
104
105/*
106 * SPI
107 *
108 * The MC13783 is the only hard-wired SPI device on the module.
109 */
110
111static int spi_internal_chipselect[] = {
112 MXC_SPI_CS(0),
113};
114
115static struct spi_imx_master spi1_pdata = {
116 .chipselect = spi_internal_chipselect,
117 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
118};
119
120static struct mc13783_platform_data mc13783_pdata __initdata = {
121 .flags = MC13783_USE_RTC |
122 MC13783_USE_REGULATOR,
123};
124
125static struct spi_board_info mc13783_spi_dev __initdata = {
126 .modalias = "mc13783",
127 .max_speed_hz = 1000000,
128 .bus_num = 1,
129 .chip_select = 0,
130 .platform_data = &mc13783_pdata,
131 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
132};
133
134/*
135 * USB
136 */
137
138#if defined(CONFIG_USB_ULPI)
139#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
140 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
141
142static int usbh2_init(struct platform_device *pdev)
143{
144 int pins[] = {
145 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
146 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
147 MX31_PIN_USBH2_CLK__USBH2_CLK,
148 MX31_PIN_USBH2_DIR__USBH2_DIR,
149 MX31_PIN_USBH2_NXT__USBH2_NXT,
150 MX31_PIN_USBH2_STP__USBH2_STP,
151 };
152
153 mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
154
155 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
156 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
157 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
158 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
159 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
160 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
161 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
162 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
163 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
164 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
165 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
166 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
167
168 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
169
170 /* chip select */
171 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
172 "USBH2_CS");
173 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
174 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
175
176 return 0;
177}
178
179static struct mxc_usbh_platform_data usbh2_pdata = {
180 .init = usbh2_init,
181 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
182 .flags = MXC_EHCI_POWER_PINS_ENABLED,
183};
184#endif
185
186/*
187 * NOR flash
188 */
189
190static struct physmap_flash_data nor_flash_data = {
191 .width = 2,
192};
193
194static struct resource nor_flash_resource = {
195 .start = 0xa0000000,
196 .end = 0xa1ffffff,
197 .flags = IORESOURCE_MEM,
198};
199
200static struct platform_device physmap_flash_device = {
201 .name = "physmap-flash",
202 .id = 0,
203 .dev = {
204 .platform_data = &nor_flash_data,
205 },
206 .resource = &nor_flash_resource,
207 .num_resources = 1,
208};
209
210
211
212/*
213 * This structure defines the MX31 memory map.
214 */
215static struct map_desc mx31lite_io_desc[] __initdata = {
216 {
217 .virtual = MX31_CS4_BASE_ADDR_VIRT,
218 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
219 .length = MX31_CS4_SIZE,
220 .type = MT_DEVICE
221 }
222};
223
224/*
225 * Set up static virtual mappings.
226 */
227void __init mx31lite_map_io(void)
228{
229 mx31_map_io();
230 iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
231}
232
233static int mx31lite_baseboard;
234core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
235
236static void __init mxc_board_init(void)
237{
238 int ret;
239
240 switch (mx31lite_baseboard) {
241 case MX31LITE_NOBOARD:
242 break;
243 case MX31LITE_DB:
244 mx31lite_db_init();
245 break;
246 default:
247 printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
248 mx31lite_baseboard);
249 }
250
251 mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
252 "mx31lite");
253
254 /* NOR and NAND flash */
255 platform_device_register(&physmap_flash_device);
256 mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
257
258 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
259 spi_register_board_info(&mc13783_spi_dev, 1);
260
261#if defined(CONFIG_USB_ULPI)
262 /* USB */
263 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
264 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
265
266 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
267#endif
268
269 /* SMSC9117 IRQ pin */
270 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
271 if (ret)
272 pr_warning("could not get LAN irq gpio\n");
273 else {
274 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
275 platform_device_register(&smsc911x_device);
276 }
277}
278
279static void __init mx31lite_timer_init(void)
280{
281 mx31_clocks_init(26000000);
282}
283
284struct sys_timer mx31lite_timer = {
285 .init = mx31lite_timer_init,
286};
287
288MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
289 /* Maintainer: Freescale Semiconductor, Inc. */
290 .phys_io = MX31_AIPS1_BASE_ADDR,
291 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
292 .boot_params = MX3x_PHYS_OFFSET + 0x100,
293 .map_io = mx31lite_map_io,
294 .init_irq = mx31_init_irq,
295 .init_machine = mxc_board_init,
296 .timer = &mx31lite_timer,
297MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 9243de54041a..fccb9207b78d 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -17,7 +17,9 @@
17 */ 17 */
18 18
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/dma-mapping.h>
20#include <linux/fsl_devices.h> 21#include <linux/fsl_devices.h>
22#include <linux/gfp.h>
21#include <linux/gpio.h> 23#include <linux/gpio.h>
22#include <linux/init.h> 24#include <linux/init.h>
23#include <linux/interrupt.h> 25#include <linux/interrupt.h>
@@ -26,8 +28,14 @@
26#include <linux/mtd/physmap.h> 28#include <linux/mtd/physmap.h>
27#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
28#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include <linux/regulator/machine.h>
32#include <linux/mfd/mc13783.h>
33#include <linux/spi/spi.h>
29#include <linux/types.h> 34#include <linux/types.h>
30 35
36#include <linux/usb/otg.h>
37#include <linux/usb/ulpi.h>
38
31#include <asm/mach-types.h> 39#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 40#include <asm/mach/arch.h>
33#include <asm/mach/time.h> 41#include <asm/mach/time.h>
@@ -37,16 +45,20 @@
37#include <mach/hardware.h> 45#include <mach/hardware.h>
38#include <mach/imx-uart.h> 46#include <mach/imx-uart.h>
39#include <mach/iomux-mx3.h> 47#include <mach/iomux-mx3.h>
48#include <mach/ipu.h>
40#include <mach/i2c.h> 49#include <mach/i2c.h>
41#include <mach/mmc.h> 50#include <mach/mmc.h>
42#include <mach/mx31.h> 51#include <mach/mxc_ehci.h>
52#include <mach/mx3_camera.h>
53#include <mach/spi.h>
54#include <mach/ulpi.h>
43 55
44#include "devices.h" 56#include "devices.h"
45 57
46static unsigned int moboard_pins[] = { 58static unsigned int moboard_pins[] = {
47 /* UART0 */ 59 /* UART0 */
48 MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1,
49 MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, 60 MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
61 MX31_PIN_CTS1__GPIO2_7,
50 /* UART4 */ 62 /* UART4 */
51 MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, 63 MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
52 MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, 64 MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
@@ -73,12 +85,28 @@ static unsigned int moboard_pins[] = {
73 MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, 85 MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
74 MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, 86 MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
75 MX31_PIN_USB_OC__GPIO1_30, 87 MX31_PIN_USB_OC__GPIO1_30,
88 /* USB H2 */
89 MX31_PIN_USBH2_DATA0__USBH2_DATA0,
90 MX31_PIN_USBH2_DATA1__USBH2_DATA1,
91 MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
92 MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
93 MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
94 MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
95 MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
96 MX31_PIN_SCK6__GPIO1_25,
76 /* LEDs */ 97 /* LEDs */
77 MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, 98 MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
78 MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, 99 MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
79 /* SEL */ 100 /* SPI1 */
80 MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, 101 MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
81 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, 102 MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
103 MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
104 /* Atlas IRQ */
105 MX31_PIN_GPIO1_3__GPIO1_3,
106 /* SPI2 */
107 MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
108 MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
109 MX31_PIN_CSPI2_SS1__CSPI3_SS1,
82}; 110};
83 111
84static struct physmap_flash_data mx31moboard_flash_data = { 112static struct physmap_flash_data mx31moboard_flash_data = {
@@ -101,7 +129,18 @@ static struct platform_device mx31moboard_flash = {
101 .num_resources = 1, 129 .num_resources = 1,
102}; 130};
103 131
104static struct imxuart_platform_data uart_pdata = { 132static int moboard_uart0_init(struct platform_device *pdev)
133{
134 gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
135 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
136 return 0;
137}
138
139static struct imxuart_platform_data uart0_pdata = {
140 .init = moboard_uart0_init,
141};
142
143static struct imxuart_platform_data uart4_pdata = {
105 .flags = IMXUART_HAVE_RTSCTS, 144 .flags = IMXUART_HAVE_RTSCTS,
106}; 145};
107 146
@@ -113,6 +152,103 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
113 .bitrate = 100000, 152 .bitrate = 100000,
114}; 153};
115 154
155static int moboard_spi1_cs[] = {
156 MXC_SPI_CS(0),
157 MXC_SPI_CS(2),
158};
159
160static struct spi_imx_master moboard_spi1_master = {
161 .chipselect = moboard_spi1_cs,
162 .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
163};
164
165static struct regulator_consumer_supply sdhc_consumers[] = {
166 {
167 .dev = &mxcsdhc_device0.dev,
168 .supply = "sdhc0_vcc",
169 },
170 {
171 .dev = &mxcsdhc_device1.dev,
172 .supply = "sdhc1_vcc",
173 },
174};
175
176static struct regulator_init_data sdhc_vreg_data = {
177 .constraints = {
178 .min_uV = 2700000,
179 .max_uV = 3000000,
180 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
181 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
182 .valid_modes_mask = REGULATOR_MODE_NORMAL |
183 REGULATOR_MODE_FAST,
184 .always_on = 0,
185 .boot_on = 1,
186 },
187 .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
188 .consumer_supplies = sdhc_consumers,
189};
190
191static struct regulator_consumer_supply cam_consumers[] = {
192 {
193 .dev = &mx3_camera.dev,
194 .supply = "cam_vcc",
195 },
196};
197
198static struct regulator_init_data cam_vreg_data = {
199 .constraints = {
200 .min_uV = 2700000,
201 .max_uV = 3000000,
202 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
203 REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
204 .valid_modes_mask = REGULATOR_MODE_NORMAL |
205 REGULATOR_MODE_FAST,
206 .always_on = 0,
207 .boot_on = 1,
208 },
209 .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
210 .consumer_supplies = cam_consumers,
211};
212
213static struct mc13783_regulator_init_data moboard_regulators[] = {
214 {
215 .id = MC13783_REGU_VMMC1,
216 .init_data = &sdhc_vreg_data,
217 },
218 {
219 .id = MC13783_REGU_VCAM,
220 .init_data = &cam_vreg_data,
221 },
222};
223
224static struct mc13783_platform_data moboard_pmic = {
225 .regulators = moboard_regulators,
226 .num_regulators = ARRAY_SIZE(moboard_regulators),
227 .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC |
228 MC13783_USE_ADC,
229};
230
231static struct spi_board_info moboard_spi_board_info[] __initdata = {
232 {
233 .modalias = "mc13783",
234 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
235 .max_speed_hz = 300000,
236 .bus_num = 1,
237 .chip_select = 0,
238 .platform_data = &moboard_pmic,
239 .mode = SPI_CS_HIGH,
240 },
241};
242
243static int moboard_spi2_cs[] = {
244 MXC_SPI_CS(1),
245};
246
247static struct spi_imx_master moboard_spi2_master = {
248 .chipselect = moboard_spi2_cs,
249 .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
250};
251
116#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) 252#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
117#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) 253#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
118 254
@@ -208,6 +344,62 @@ static struct fsl_usb2_platform_data usb_pdata = {
208 .phy_mode = FSL_USB2_PHY_ULPI, 344 .phy_mode = FSL_USB2_PHY_ULPI,
209}; 345};
210 346
347#if defined(CONFIG_USB_ULPI)
348
349#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
350
351static int moboard_usbh2_hw_init(struct platform_device *pdev)
352{
353 int ret;
354
355 mxc_iomux_set_gpr(MUX_PGP_UH2, true);
356
357 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
358 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
359 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
360 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
361 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
362 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
363 mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
364 mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
365 mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
366 mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
367 mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
368 mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
369
370 ret = gpio_request(USBH2_EN_B, "usbh2-en");
371 if (ret)
372 return ret;
373 gpio_direction_output(USBH2_EN_B, 0);
374
375 return 0;
376}
377
378static int moboard_usbh2_hw_exit(struct platform_device *pdev)
379{
380 gpio_free(USBH2_EN_B);
381 return 0;
382}
383
384static struct mxc_usbh_platform_data usbh2_pdata = {
385 .init = moboard_usbh2_hw_init,
386 .exit = moboard_usbh2_hw_exit,
387 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
388 .flags = MXC_EHCI_POWER_PINS_ENABLED,
389};
390
391static int __init moboard_usbh2_init(void)
392{
393 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
394 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
395
396 return mxc_register_device(&mxc_usbh2, &usbh2_pdata);
397}
398#else
399static inline int moboard_usbh2_init(void) { return 0; }
400#endif
401
402
211static struct gpio_led mx31moboard_leds[] = { 403static struct gpio_led mx31moboard_leds[] = {
212 { 404 {
213 .name = "coreboard-led-0:red:running", 405 .name = "coreboard-led-0:red:running",
@@ -238,38 +430,47 @@ static struct platform_device mx31moboard_leds_device = {
238 }, 430 },
239}; 431};
240 432
241#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) 433static struct ipu_platform_data mx3_ipu_data = {
242#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) 434 .irq_base = MXC_IPU_IRQ_START,
243#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) 435};
244#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) 436
437static struct platform_device *devices[] __initdata = {
438 &mx31moboard_flash,
439 &mx31moboard_leds_device,
440};
245 441
246static void mx31moboard_init_sel_gpios(void) 442static struct mx3_camera_pdata camera_pdata = {
443 .dma_dev = &mx3_ipu.dev,
444 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
445 .mclk_10khz = 4800,
446};
447
448#define CAMERA_BUF_SIZE (4*1024*1024)
449
450static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
247{ 451{
248 if (!gpio_request(SEL0, "sel0")) { 452 dma_addr_t dma_handle;
249 gpio_direction_input(SEL0); 453 void *buf;
250 gpio_export(SEL0, true); 454 int dma;
251 }
252 455
253 if (!gpio_request(SEL1, "sel1")) { 456 if (buf_size < 2 * 1024 * 1024)
254 gpio_direction_input(SEL1); 457 return -EINVAL;
255 gpio_export(SEL1, true);
256 }
257 458
258 if (!gpio_request(SEL2, "sel2")) { 459 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
259 gpio_direction_input(SEL2); 460 if (!buf) {
260 gpio_export(SEL2, true); 461 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
462 return -ENOMEM;
261 } 463 }
262 464
263 if (!gpio_request(SEL3, "sel3")) { 465 memset(buf, 0, buf_size);
264 gpio_direction_input(SEL3);
265 gpio_export(SEL3, true);
266 }
267}
268 466
269static struct platform_device *devices[] __initdata = { 467 dma = dma_declare_coherent_memory(&mx3_camera.dev,
270 &mx31moboard_flash, 468 dma_handle, dma_handle, buf_size,
271 &mx31moboard_leds_device, 469 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
272}; 470
471 /* The way we call dma_declare_coherent_memory only a malloc can fail */
472 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
473}
273 474
274static int mx31moboard_baseboard; 475static int mx31moboard_baseboard;
275core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); 476core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
@@ -284,20 +485,32 @@ static void __init mxc_board_init(void)
284 485
285 platform_add_devices(devices, ARRAY_SIZE(devices)); 486 platform_add_devices(devices, ARRAY_SIZE(devices));
286 487
287 mxc_register_device(&mxc_uart_device0, &uart_pdata); 488 mxc_register_device(&mxc_uart_device0, &uart0_pdata);
288 mxc_register_device(&mxc_uart_device4, &uart_pdata);
289 489
290 mx31moboard_init_sel_gpios(); 490 mxc_register_device(&mxc_uart_device4, &uart4_pdata);
291 491
292 mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); 492 mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
293 mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); 493 mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
294 494
495 mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
496 mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
497
498 gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
499 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
500 spi_register_board_info(moboard_spi_board_info,
501 ARRAY_SIZE(moboard_spi_board_info));
502
295 mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); 503 mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
296 504
505 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
506 if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
507 mxc_register_device(&mx3_camera, &camera_pdata);
508
297 usb_xcvr_reset(); 509 usb_xcvr_reset();
298 510
299 moboard_usbotg_init(); 511 moboard_usbotg_init();
300 mxc_register_device(&mxc_otg_udc_device, &usb_pdata); 512 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
513 moboard_usbh2_init();
301 514
302 switch (mx31moboard_baseboard) { 515 switch (mx31moboard_baseboard) {
303 case MX31NOBOARD: 516 case MX31NOBOARD:
@@ -308,6 +521,9 @@ static void __init mxc_board_init(void)
308 case MX31MARXBOT: 521 case MX31MARXBOT:
309 mx31moboard_marxbot_init(); 522 mx31moboard_marxbot_init();
310 break; 523 break;
524 case MX31SMARTBOT:
525 mx31moboard_smartbot_init();
526 break;
311 default: 527 default:
312 printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", 528 printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
313 mx31moboard_baseboard); 529 mx31moboard_baseboard);
@@ -325,9 +541,9 @@ struct sys_timer mx31moboard_timer = {
325 541
326MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") 542MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
327 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 543 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
328 .phys_io = AIPS1_BASE_ADDR, 544 .phys_io = MX31_AIPS1_BASE_ADDR,
329 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 545 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
330 .boot_params = PHYS_OFFSET + 0x100, 546 .boot_params = MX3x_PHYS_OFFSET + 0x100,
331 .map_io = mx31_map_io, 547 .map_io = mx31_map_io,
332 .init_irq = mx31_init_irq, 548 .init_irq = mx31_init_irq,
333 .init_machine = mxc_board_init, 549 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c
index 6ff186e46ceb..bcac84d4dca4 100644
--- a/arch/arm/mach-mx3/mx35pdk.c
+++ b/arch/arm/mach-mx3/mach-mx35pdk.c
@@ -23,6 +23,7 @@
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/memory.h> 24#include <linux/memory.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/fsl_devices.h>
26 27
27#include <asm/mach-types.h> 28#include <asm/mach-types.h>
28#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
@@ -69,6 +70,15 @@ static struct pad_desc mx35pdk_pads[] = {
69 MX35_PAD_FEC_TDATA2__FEC_TDATA_2, 70 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
70 MX35_PAD_FEC_RDATA3__FEC_RDATA_3, 71 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
71 MX35_PAD_FEC_TDATA3__FEC_TDATA_3, 72 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
73 /* USBOTG */
74 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
75 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
76};
77
78/* OTG config */
79static struct fsl_usb2_platform_data usb_pdata = {
80 .operating_mode = FSL_USB2_DR_DEVICE,
81 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
72}; 82};
73 83
74/* 84/*
@@ -81,6 +91,8 @@ static void __init mxc_board_init(void)
81 platform_add_devices(devices, ARRAY_SIZE(devices)); 91 platform_add_devices(devices, ARRAY_SIZE(devices));
82 92
83 mxc_register_device(&mxc_uart_device0, &uart_pdata); 93 mxc_register_device(&mxc_uart_device0, &uart_pdata);
94
95 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
84} 96}
85 97
86static void __init mx35pdk_timer_init(void) 98static void __init mx35pdk_timer_init(void)
@@ -94,9 +106,9 @@ struct sys_timer mx35pdk_timer = {
94 106
95MACHINE_START(MX35_3DS, "Freescale MX35PDK") 107MACHINE_START(MX35_3DS, "Freescale MX35PDK")
96 /* Maintainer: Freescale Semiconductor, Inc */ 108 /* Maintainer: Freescale Semiconductor, Inc */
97 .phys_io = AIPS1_BASE_ADDR, 109 .phys_io = MX35_AIPS1_BASE_ADDR,
98 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 110 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
99 .boot_params = PHYS_OFFSET + 0x100, 111 .boot_params = MX3x_PHYS_OFFSET + 0x100,
100 .map_io = mx35_map_io, 112 .map_io = mx35_map_io,
101 .init_irq = mx35_init_irq, 113 .init_irq = mx35_init_irq,
102 .init_machine = mxc_board_init, 114 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 6cbaabedf386..2df1ec55a97e 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -33,6 +33,9 @@
33#include <linux/irq.h> 33#include <linux/irq.h>
34#include <linux/fsl_devices.h> 34#include <linux/fsl_devices.h>
35#include <linux/can/platform/sja1000.h> 35#include <linux/can/platform/sja1000.h>
36#include <linux/usb/otg.h>
37#include <linux/usb/ulpi.h>
38#include <linux/gfp.h>
36 39
37#include <media/soc_camera.h> 40#include <media/soc_camera.h>
38 41
@@ -51,6 +54,8 @@
51#include <mach/mx3_camera.h> 54#include <mach/mx3_camera.h>
52#include <mach/mx3fb.h> 55#include <mach/mx3fb.h>
53#include <mach/mxc_nand.h> 56#include <mach/mxc_nand.h>
57#include <mach/mxc_ehci.h>
58#include <mach/ulpi.h>
54 59
55#include "devices.h" 60#include "devices.h"
56#include "pcm037.h" 61#include "pcm037.h"
@@ -172,19 +177,7 @@ static unsigned int pcm037_pins[] = {
172 MX31_PIN_CSI_VSYNC__CSI_VSYNC, 177 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
173 /* GPIO */ 178 /* GPIO */
174 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO), 179 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
175}; 180 /* OTG */
176
177static struct physmap_flash_data pcm037_flash_data = {
178 .width = 2,
179};
180
181static struct resource pcm037_flash_resource = {
182 .start = 0xa0000000,
183 .end = 0xa1ffffff,
184 .flags = IORESOURCE_MEM,
185};
186
187static int usbotg_pins[] = {
188 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, 181 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
189 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, 182 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
190 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, 183 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
@@ -197,39 +190,29 @@ static int usbotg_pins[] = {
197 MX31_PIN_USBOTG_DIR__USBOTG_DIR, 190 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
198 MX31_PIN_USBOTG_NXT__USBOTG_NXT, 191 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
199 MX31_PIN_USBOTG_STP__USBOTG_STP, 192 MX31_PIN_USBOTG_STP__USBOTG_STP,
193 /* USB host 2 */
194 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
195 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
196 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
197 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
198 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
199 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
200 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
201 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
202 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
203 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
204 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
205 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
200}; 206};
201 207
202/* USB OTG HS port */ 208static struct physmap_flash_data pcm037_flash_data = {
203static int __init gpio_usbotg_hs_activate(void) 209 .width = 2,
204{ 210};
205 int ret = mxc_iomux_setup_multiple_pins(usbotg_pins,
206 ARRAY_SIZE(usbotg_pins), "usbotg");
207
208 if (ret < 0) {
209 printk(KERN_ERR "Cannot set up OTG pins\n");
210 return ret;
211 }
212
213 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
214 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
215 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
216 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
217 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
218 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
219 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
220 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
221 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
222 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
223 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
224 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
225
226 return 0;
227}
228 211
229/* OTG config */ 212static struct resource pcm037_flash_resource = {
230static struct fsl_usb2_platform_data usb_pdata = { 213 .start = 0xa0000000,
231 .operating_mode = FSL_USB2_DR_DEVICE, 214 .end = 0xa1ffffff,
232 .phy_mode = FSL_USB2_PHY_ULPI, 215 .flags = IORESOURCE_MEM,
233}; 216};
234 217
235static struct platform_device pcm037_flash = { 218static struct platform_device pcm037_flash = {
@@ -248,8 +231,8 @@ static struct imxuart_platform_data uart_pdata = {
248 231
249static struct resource smsc911x_resources[] = { 232static struct resource smsc911x_resources[] = {
250 { 233 {
251 .start = CS1_BASE_ADDR + 0x300, 234 .start = MX31_CS1_BASE_ADDR + 0x300,
252 .end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1, 235 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
253 .flags = IORESOURCE_MEM, 236 .flags = IORESOURCE_MEM,
254 }, { 237 }, {
255 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), 238 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
@@ -281,8 +264,8 @@ static struct platdata_mtd_ram pcm038_sram_data = {
281}; 264};
282 265
283static struct resource pcm038_sram_resource = { 266static struct resource pcm038_sram_resource = {
284 .start = CS4_BASE_ADDR, 267 .start = MX31_CS4_BASE_ADDR,
285 .end = CS4_BASE_ADDR + 512 * 1024 - 1, 268 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
286 .flags = IORESOURCE_MEM, 269 .flags = IORESOURCE_MEM,
287}; 270};
288 271
@@ -322,16 +305,25 @@ static int pcm037_camera_power(struct device *dev, int on)
322 return 0; 305 return 0;
323} 306}
324 307
325static struct i2c_board_info pcm037_i2c_2_devices[] = { 308static struct i2c_board_info pcm037_i2c_camera[] = {
326 { 309 {
327 I2C_BOARD_INFO("mt9t031", 0x5d), 310 I2C_BOARD_INFO("mt9t031", 0x5d),
311 }, {
312 I2C_BOARD_INFO("mt9v022", 0x48),
328 }, 313 },
329}; 314};
330 315
331static struct soc_camera_link iclink = { 316static struct soc_camera_link iclink_mt9v022 = {
317 .bus_id = 0, /* Must match with the camera ID */
318 .board_info = &pcm037_i2c_camera[1],
319 .i2c_adapter_id = 2,
320 .module_name = "mt9v022",
321};
322
323static struct soc_camera_link iclink_mt9t031 = {
332 .bus_id = 0, /* Must match with the camera ID */ 324 .bus_id = 0, /* Must match with the camera ID */
333 .power = pcm037_camera_power, 325 .power = pcm037_camera_power,
334 .board_info = &pcm037_i2c_2_devices[0], 326 .board_info = &pcm037_i2c_camera[0],
335 .i2c_adapter_id = 2, 327 .i2c_adapter_id = 2,
336 .module_name = "mt9t031", 328 .module_name = "mt9t031",
337}; 329};
@@ -345,11 +337,19 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
345 } 337 }
346}; 338};
347 339
348static struct platform_device pcm037_camera = { 340static struct platform_device pcm037_mt9t031 = {
349 .name = "soc-camera-pdrv", 341 .name = "soc-camera-pdrv",
350 .id = 0, 342 .id = 0,
351 .dev = { 343 .dev = {
352 .platform_data = &iclink, 344 .platform_data = &iclink_mt9t031,
345 },
346};
347
348static struct platform_device pcm037_mt9v022 = {
349 .name = "soc-camera-pdrv",
350 .id = 1,
351 .dev = {
352 .platform_data = &iclink_mt9v022,
353 }, 353 },
354}; 354};
355 355
@@ -449,7 +449,8 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
449static struct platform_device *devices[] __initdata = { 449static struct platform_device *devices[] __initdata = {
450 &pcm037_flash, 450 &pcm037_flash,
451 &pcm037_sram_device, 451 &pcm037_sram_device,
452 &pcm037_camera, 452 &pcm037_mt9t031,
453 &pcm037_mt9v022,
453}; 454};
454 455
455static struct ipu_platform_data mx3_ipu_data = { 456static struct ipu_platform_data mx3_ipu_data = {
@@ -518,8 +519,8 @@ static struct mx3fb_platform_data mx3fb_pdata = {
518 519
519static struct resource pcm970_sja1000_resources[] = { 520static struct resource pcm970_sja1000_resources[] = {
520 { 521 {
521 .start = CS5_BASE_ADDR, 522 .start = MX31_CS5_BASE_ADDR,
522 .end = CS5_BASE_ADDR + 0x100 - 1, 523 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
523 .flags = IORESOURCE_MEM, 524 .flags = IORESOURCE_MEM,
524 }, { 525 }, {
525 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), 526 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
@@ -543,16 +544,65 @@ static struct platform_device pcm970_sja1000 = {
543 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), 544 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
544}; 545};
545 546
547static struct mxc_usbh_platform_data otg_pdata = {
548 .portsc = MXC_EHCI_MODE_ULPI,
549 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
550};
551
552static struct mxc_usbh_platform_data usbh2_pdata = {
553 .portsc = MXC_EHCI_MODE_ULPI,
554 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
555};
556
557static struct fsl_usb2_platform_data otg_device_pdata = {
558 .operating_mode = FSL_USB2_DR_DEVICE,
559 .phy_mode = FSL_USB2_PHY_ULPI,
560};
561
562static int otg_mode_host;
563
564static int __init pcm037_otg_mode(char *options)
565{
566 if (!strcmp(options, "host"))
567 otg_mode_host = 1;
568 else if (!strcmp(options, "device"))
569 otg_mode_host = 0;
570 else
571 pr_info("otg_mode neither \"host\" nor \"device\". "
572 "Defaulting to device\n");
573 return 0;
574}
575__setup("otg_mode=", pcm037_otg_mode);
576
546/* 577/*
547 * Board specific initialization. 578 * Board specific initialization.
548 */ 579 */
549static void __init mxc_board_init(void) 580static void __init mxc_board_init(void)
550{ 581{
551 int ret; 582 int ret;
583 u32 tmp;
584
585 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
552 586
553 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), 587 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
554 "pcm037"); 588 "pcm037");
555 589
590#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
591 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
592
593 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
594 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
595 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
596 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
597 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
598 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
599 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
600 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
601 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
602 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
603 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
604 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
605
556 if (pcm037_variant() == PCM037_EET) 606 if (pcm037_variant() == PCM037_EET)
557 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, 607 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
558 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); 608 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
@@ -590,8 +640,6 @@ static void __init mxc_board_init(void)
590 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); 640 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
591 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 641 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
592 mxc_register_device(&mx3_fb, &mx3fb_pdata); 642 mxc_register_device(&mx3_fb, &mx3fb_pdata);
593 if (!gpio_usbotg_hs_activate())
594 mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
595 643
596 /* CSI */ 644 /* CSI */
597 /* Camera power: default - off */ 645 /* Camera power: default - off */
@@ -599,12 +647,29 @@ static void __init mxc_board_init(void)
599 if (!ret) 647 if (!ret)
600 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1); 648 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
601 else 649 else
602 iclink.power = NULL; 650 iclink_mt9t031.power = NULL;
603 651
604 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024)) 652 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
605 mxc_register_device(&mx3_camera, &camera_pdata); 653 mxc_register_device(&mx3_camera, &camera_pdata);
606 654
607 platform_device_register(&pcm970_sja1000); 655 platform_device_register(&pcm970_sja1000);
656
657#if defined(CONFIG_USB_ULPI)
658 if (otg_mode_host) {
659 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
660 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
661
662 mxc_register_device(&mxc_otg_host, &otg_pdata);
663 }
664
665 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
666 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
667
668 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
669#endif
670 if (!otg_mode_host)
671 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
672
608} 673}
609 674
610static void __init pcm037_timer_init(void) 675static void __init pcm037_timer_init(void)
@@ -618,9 +683,9 @@ struct sys_timer pcm037_timer = {
618 683
619MACHINE_START(PCM037, "Phytec Phycore pcm037") 684MACHINE_START(PCM037, "Phytec Phycore pcm037")
620 /* Maintainer: Pengutronix */ 685 /* Maintainer: Pengutronix */
621 .phys_io = AIPS1_BASE_ADDR, 686 .phys_io = MX31_AIPS1_BASE_ADDR,
622 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 687 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
623 .boot_params = PHYS_OFFSET + 0x100, 688 .boot_params = MX3x_PHYS_OFFSET + 0x100,
624 .map_io = mx31_map_io, 689 .map_io = mx31_map_io,
625 .init_irq = mx31_init_irq, 690 .init_irq = mx31_init_irq,
626 .init_machine = mxc_board_init, 691 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index 8d386000fc40..8d386000fc40 100644
--- a/arch/arm/mach-mx3/pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index e18a224671fa..1bf1ec2eef5e 100644
--- a/arch/arm/mach-mx3/pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -26,8 +26,12 @@
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/smc911x.h> 27#include <linux/smc911x.h>
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/delay.h>
29#include <linux/i2c.h> 30#include <linux/i2c.h>
30#include <linux/i2c/at24.h> 31#include <linux/i2c/at24.h>
32#include <linux/usb/otg.h>
33#include <linux/usb/ulpi.h>
34#include <linux/fsl_devices.h>
31 35
32#include <asm/mach-types.h> 36#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
@@ -43,6 +47,11 @@
43#include <mach/iomux-mx35.h> 47#include <mach/iomux-mx35.h>
44#include <mach/ipu.h> 48#include <mach/ipu.h>
45#include <mach/mx3fb.h> 49#include <mach/mx3fb.h>
50#include <mach/mxc_nand.h>
51#include <mach/mxc_ehci.h>
52#include <mach/ulpi.h>
53#include <mach/audmux.h>
54#include <mach/ssi.h>
46 55
47#include "devices.h" 56#include "devices.h"
48 57
@@ -204,8 +213,132 @@ static struct pad_desc pcm043_pads[] = {
204 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, 213 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
205 /* gpio */ 214 /* gpio */
206 MX35_PAD_ATA_CS0__GPIO2_6, 215 MX35_PAD_ATA_CS0__GPIO2_6,
216 /* USB host */
217 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
218 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
219 /* SSI */
220 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
221 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
222 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
223 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
207}; 224};
208 225
226#define AC97_GPIO_TXFS (1 * 32 + 31)
227#define AC97_GPIO_TXD (1 * 32 + 28)
228#define AC97_GPIO_RESET (1 * 32 + 0)
229
230static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
231{
232 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
233 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
234 int ret;
235
236 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
237 if (ret) {
238 printk("failed to get GPIO_TXFS: %d\n", ret);
239 return;
240 }
241
242 mxc_iomux_v3_setup_pad(&txfs_gpio);
243
244 /* warm reset */
245 gpio_direction_output(AC97_GPIO_TXFS, 1);
246 udelay(2);
247 gpio_set_value(AC97_GPIO_TXFS, 0);
248
249 gpio_free(AC97_GPIO_TXFS);
250 mxc_iomux_v3_setup_pad(&txfs);
251}
252
253static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
254{
255 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
256 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
257 struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
258 struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
259 struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
260 int ret;
261
262 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
263 if (ret)
264 goto err1;
265
266 ret = gpio_request(AC97_GPIO_TXD, "SSI");
267 if (ret)
268 goto err2;
269
270 ret = gpio_request(AC97_GPIO_RESET, "SSI");
271 if (ret)
272 goto err3;
273
274 mxc_iomux_v3_setup_pad(&txfs_gpio);
275 mxc_iomux_v3_setup_pad(&txd_gpio);
276 mxc_iomux_v3_setup_pad(&reset_gpio);
277
278 gpio_direction_output(AC97_GPIO_TXFS, 0);
279 gpio_direction_output(AC97_GPIO_TXD, 0);
280
281 /* cold reset */
282 gpio_direction_output(AC97_GPIO_RESET, 0);
283 udelay(10);
284 gpio_direction_output(AC97_GPIO_RESET, 1);
285
286 mxc_iomux_v3_setup_pad(&txd);
287 mxc_iomux_v3_setup_pad(&txfs);
288
289 gpio_free(AC97_GPIO_RESET);
290err3:
291 gpio_free(AC97_GPIO_TXD);
292err2:
293 gpio_free(AC97_GPIO_TXFS);
294err1:
295 if (ret)
296 printk("%s failed with %d\n", __func__, ret);
297 mdelay(1);
298}
299
300static struct imx_ssi_platform_data pcm043_ssi_pdata = {
301 .ac97_reset = pcm043_ac97_cold_reset,
302 .ac97_warm_reset = pcm043_ac97_warm_reset,
303 .flags = IMX_SSI_USE_AC97,
304};
305
306static struct mxc_nand_platform_data pcm037_nand_board_info = {
307 .width = 1,
308 .hw_ecc = 1,
309};
310
311static struct mxc_usbh_platform_data otg_pdata = {
312 .portsc = MXC_EHCI_MODE_UTMI,
313 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
314};
315
316static struct mxc_usbh_platform_data usbh1_pdata = {
317 .portsc = MXC_EHCI_MODE_SERIAL,
318 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
319 MXC_EHCI_IPPUE_DOWN,
320};
321
322static struct fsl_usb2_platform_data otg_device_pdata = {
323 .operating_mode = FSL_USB2_DR_DEVICE,
324 .phy_mode = FSL_USB2_PHY_UTMI,
325};
326
327static int otg_mode_host;
328
329static int __init pcm043_otg_mode(char *options)
330{
331 if (!strcmp(options, "host"))
332 otg_mode_host = 1;
333 else if (!strcmp(options, "device"))
334 otg_mode_host = 0;
335 else
336 pr_info("otg_mode neither \"host\" nor \"device\". "
337 "Defaulting to device\n");
338 return 0;
339}
340__setup("otg_mode=", pcm043_otg_mode);
341
209/* 342/*
210 * Board specific initialization. 343 * Board specific initialization.
211 */ 344 */
@@ -213,9 +346,23 @@ static void __init mxc_board_init(void)
213{ 346{
214 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); 347 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
215 348
349 mxc_audmux_v2_configure_port(3,
350 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
351 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
352 MXC_AUDMUX_V2_PTCR_TFSDIR,
353 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
354
355 mxc_audmux_v2_configure_port(0,
356 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
357 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
358 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
359 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
360
216 platform_add_devices(devices, ARRAY_SIZE(devices)); 361 platform_add_devices(devices, ARRAY_SIZE(devices));
217 362
218 mxc_register_device(&mxc_uart_device0, &uart_pdata); 363 mxc_register_device(&mxc_uart_device0, &uart_pdata);
364 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
365 mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
219 366
220 mxc_register_device(&mxc_uart_device1, &uart_pdata); 367 mxc_register_device(&mxc_uart_device1, &uart_pdata);
221 368
@@ -228,6 +375,20 @@ static void __init mxc_board_init(void)
228 375
229 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 376 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
230 mxc_register_device(&mx3_fb, &mx3fb_pdata); 377 mxc_register_device(&mx3_fb, &mx3fb_pdata);
378
379#if defined(CONFIG_USB_ULPI)
380 if (otg_mode_host) {
381 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
382 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
383
384 mxc_register_device(&mxc_otg_host, &otg_pdata);
385 }
386
387 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
388#endif
389 if (!otg_mode_host)
390 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
391
231} 392}
232 393
233static void __init pcm043_timer_init(void) 394static void __init pcm043_timer_init(void)
@@ -241,9 +402,9 @@ struct sys_timer pcm043_timer = {
241 402
242MACHINE_START(PCM043, "Phytec Phycore pcm043") 403MACHINE_START(PCM043, "Phytec Phycore pcm043")
243 /* Maintainer: Pengutronix */ 404 /* Maintainer: Pengutronix */
244 .phys_io = AIPS1_BASE_ADDR, 405 .phys_io = MX35_AIPS1_BASE_ADDR,
245 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 406 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
246 .boot_params = PHYS_OFFSET + 0x100, 407 .boot_params = MX3x_PHYS_OFFSET + 0x100,
247 .map_io = mx35_map_io, 408 .map_io = mx35_map_io,
248 .init_irq = mx35_init_irq, 409 .init_irq = mx35_init_irq,
249 .init_machine = mxc_board_init, 410 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/mach-qong.c
index 044511f1b9a9..e5b5b8323a17 100644
--- a/arch/arm/mach-mx3/qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -43,7 +43,7 @@
43#define QONG_FPGA_VERSION(major, minor, rev) \ 43#define QONG_FPGA_VERSION(major, minor, rev) \
44 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) 44 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
45 45
46#define QONG_FPGA_BASEADDR CS1_BASE_ADDR 46#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
47#define QONG_FPGA_PERIPH_SIZE (1 << 24) 47#define QONG_FPGA_PERIPH_SIZE (1 << 24)
48 48
49#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR 49#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
@@ -115,8 +115,8 @@ static struct physmap_flash_data qong_flash_data = {
115}; 115};
116 116
117static struct resource qong_flash_resource = { 117static struct resource qong_flash_resource = {
118 .start = CS0_BASE_ADDR, 118 .start = MX31_CS0_BASE_ADDR,
119 .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1, 119 .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
120 .flags = IORESOURCE_MEM, 120 .flags = IORESOURCE_MEM,
121}; 121};
122 122
@@ -180,8 +180,8 @@ static struct platform_nand_data qong_nand_data = {
180}; 180};
181 181
182static struct resource qong_nand_resource = { 182static struct resource qong_nand_resource = {
183 .start = CS3_BASE_ADDR, 183 .start = MX31_CS3_BASE_ADDR,
184 .end = CS3_BASE_ADDR + SZ_32M - 1, 184 .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
185 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
186}; 186};
187 187
@@ -198,9 +198,7 @@ static struct platform_device qong_nand_device = {
198static void __init qong_init_nand_mtd(void) 198static void __init qong_init_nand_mtd(void)
199{ 199{
200 /* init CS */ 200 /* init CS */
201 __raw_writel(0x00004f00, CSCR_U(3)); 201 mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
202 __raw_writel(0x20013b31, CSCR_L(3));
203 __raw_writel(0x00020800, CSCR_A(3));
204 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); 202 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
205 203
206 /* enable pin */ 204 /* enable pin */
@@ -275,9 +273,9 @@ static struct sys_timer qong_timer = {
275 273
276MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") 274MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
277 /* Maintainer: DENX Software Engineering GmbH */ 275 /* Maintainer: DENX Software Engineering GmbH */
278 .phys_io = AIPS1_BASE_ADDR, 276 .phys_io = MX31_AIPS1_BASE_ADDR,
279 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 277 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
280 .boot_params = PHYS_OFFSET + 0x100, 278 .boot_params = MX3x_PHYS_OFFSET + 0x100,
281 .map_io = mx31_map_io, 279 .map_io = mx31_map_io,
282 .init_irq = mx31_init_irq, 280 .init_irq = mx31_init_irq,
283 .init_machine = mxc_board_init, 281 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index bedf5b8d976a..6858a4f9806c 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -65,6 +65,11 @@ static struct map_desc mxc_io_desc[] __initdata = {
65 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), 65 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
66 .length = AIPS2_SIZE, 66 .length = AIPS2_SIZE,
67 .type = MT_DEVICE_NONSHARED 67 .type = MT_DEVICE_NONSHARED
68 }, {
69 .virtual = SPBA0_BASE_ADDR_VIRT,
70 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
71 .length = SPBA0_SIZE,
72 .type = MT_DEVICE_NONSHARED
68 }, 73 },
69}; 74};
70 75
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 3b3a78f49c23..7aebd74a12e8 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -109,6 +109,9 @@ static int mxc_mmc1_get_ro(struct device *dev)
109 109
110static int gpio_det, gpio_wp; 110static int gpio_det, gpio_wp;
111 111
112#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
113 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
114
112static int mxc_mmc1_init(struct device *dev, 115static int mxc_mmc1_init(struct device *dev,
113 irq_handler_t detect_irq, void *data) 116 irq_handler_t detect_irq, void *data)
114{ 117{
@@ -117,6 +120,13 @@ static int mxc_mmc1_init(struct device *dev,
117 gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1); 120 gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
118 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0); 121 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
119 122
123 mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
124 mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
125 mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
126 mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
127 mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
128 mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
129
120 ret = gpio_request(gpio_det, "MMC detect"); 130 ret = gpio_request(gpio_det, "MMC detect");
121 if (ret) 131 if (ret)
122 return ret; 132 return ret;
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
new file mode 100644
index 000000000000..093c595ca581
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -0,0 +1,210 @@
1/*
2 * LogicPD i.MX31 SOM-LV development board support
3 *
4 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
5 *
6 * based on code for other MX31 boards,
7 *
8 * Copyright 2005-2007 Freescale Semiconductor
9 * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
10 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 */
26
27#include <linux/kernel.h>
28#include <linux/types.h>
29#include <linux/init.h>
30#include <linux/gpio.h>
31#include <linux/leds.h>
32#include <linux/platform_device.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37
38#include <mach/hardware.h>
39#include <mach/common.h>
40#include <mach/imx-uart.h>
41#include <mach/iomux-mx3.h>
42#include <mach/board-mx31lite.h>
43#include <mach/mmc.h>
44#include <mach/spi.h>
45
46#include "devices.h"
47
48/*
49 * This file contains board-specific initialization routines for the
50 * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
51 * If you design an own baseboard for the module, use this file as base
52 * for support code.
53 */
54
55static unsigned int litekit_db_board_pins[] __initdata = {
56 /* UART1 */
57 MX31_PIN_CTS1__CTS1,
58 MX31_PIN_RTS1__RTS1,
59 MX31_PIN_TXD1__TXD1,
60 MX31_PIN_RXD1__RXD1,
61 /* SPI 0 */
62 MX31_PIN_CSPI1_SCLK__SCLK,
63 MX31_PIN_CSPI1_MOSI__MOSI,
64 MX31_PIN_CSPI1_MISO__MISO,
65 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
66 MX31_PIN_CSPI1_SS0__SS0,
67 MX31_PIN_CSPI1_SS1__SS1,
68 MX31_PIN_CSPI1_SS2__SS2,
69 /* SDHC1 */
70 MX31_PIN_SD1_DATA0__SD1_DATA0,
71 MX31_PIN_SD1_DATA1__SD1_DATA1,
72 MX31_PIN_SD1_DATA2__SD1_DATA2,
73 MX31_PIN_SD1_DATA3__SD1_DATA3,
74 MX31_PIN_SD1_CLK__SD1_CLK,
75 MX31_PIN_SD1_CMD__SD1_CMD,
76};
77
78/* UART */
79static struct imxuart_platform_data uart_pdata __initdata = {
80 .flags = IMXUART_HAVE_RTSCTS,
81};
82
83/* MMC */
84
85static int gpio_det, gpio_wp;
86
87#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
88 PAD_CTL_ODE_CMOS)
89
90static int mxc_mmc1_get_ro(struct device *dev)
91{
92 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
93}
94
95static int mxc_mmc1_init(struct device *dev,
96 irq_handler_t detect_irq, void *data)
97{
98 int ret;
99
100 gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
101 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
102
103 mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
104 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
105 mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
106 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
107 mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
108 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
109 mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
110 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
111 mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
112 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
113 mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
114
115 ret = gpio_request(gpio_det, "MMC detect");
116 if (ret)
117 return ret;
118
119 ret = gpio_request(gpio_wp, "MMC w/p");
120 if (ret)
121 goto exit_free_det;
122
123 gpio_direction_input(gpio_det);
124 gpio_direction_input(gpio_wp);
125
126 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
127 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
128 "MMC detect", data);
129 if (ret)
130 goto exit_free_wp;
131
132 return 0;
133
134exit_free_wp:
135 gpio_free(gpio_wp);
136
137exit_free_det:
138 gpio_free(gpio_det);
139
140 return ret;
141}
142
143static void mxc_mmc1_exit(struct device *dev, void *data)
144{
145 gpio_free(gpio_det);
146 gpio_free(gpio_wp);
147 free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
148}
149
150static struct imxmmc_platform_data mmc_pdata = {
151 .get_ro = mxc_mmc1_get_ro,
152 .init = mxc_mmc1_init,
153 .exit = mxc_mmc1_exit,
154};
155
156/* SPI */
157
158static int spi_internal_chipselect[] = {
159 MXC_SPI_CS(0),
160 MXC_SPI_CS(1),
161 MXC_SPI_CS(2),
162};
163
164static struct spi_imx_master spi0_pdata = {
165 .chipselect = spi_internal_chipselect,
166 .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
167};
168
169/* GPIO LEDs */
170
171static struct gpio_led litekit_leds[] = {
172 {
173 .name = "GPIO0",
174 .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
175 .active_low = 1,
176 .default_state = LEDS_GPIO_DEFSTATE_OFF,
177 },
178 {
179 .name = "GPIO1",
180 .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
181 .active_low = 1,
182 .default_state = LEDS_GPIO_DEFSTATE_OFF,
183 }
184};
185
186static struct gpio_led_platform_data litekit_led_platform_data = {
187 .leds = litekit_leds,
188 .num_leds = ARRAY_SIZE(litekit_leds),
189};
190
191static struct platform_device litekit_led_device = {
192 .name = "leds-gpio",
193 .id = -1,
194 .dev = {
195 .platform_data = &litekit_led_platform_data,
196 },
197};
198
199void __init mx31lite_db_init(void)
200{
201 mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
202 ARRAY_SIZE(litekit_db_board_pins),
203 "development board pins");
204 mxc_register_device(&mxc_uart_device0, &uart_pdata);
205 mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
206 mxc_register_device(&mxc_spi_device0, &spi0_pdata);
207 platform_device_register(&litekit_led_device);
208 mxc_register_device(&imx_wdt_device0, NULL);
209}
210
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
deleted file mode 100644
index a8d57decdfdb..000000000000
--- a/arch/arm/mach-mx3/mx31lite.c
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/memory.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27#include <linux/smsc911x.h>
28
29#include <mach/hardware.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/mach/map.h>
34#include <mach/common.h>
35#include <asm/page.h>
36#include <asm/setup.h>
37#include <mach/board-mx31lite.h>
38#include <mach/imx-uart.h>
39#include <mach/iomux-mx3.h>
40#include <mach/irqs.h>
41#include <mach/mxc_nand.h>
42#include "devices.h"
43
44/*
45 * This file contains the board-specific initialization routines.
46 */
47
48static unsigned int mx31lite_pins[] = {
49 /* UART1 */
50 MX31_PIN_CTS1__CTS1,
51 MX31_PIN_RTS1__RTS1,
52 MX31_PIN_TXD1__TXD1,
53 MX31_PIN_RXD1__RXD1,
54 /* LAN9117 IRQ pin */
55 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
56};
57
58static struct imxuart_platform_data uart_pdata = {
59 .flags = IMXUART_HAVE_RTSCTS,
60};
61
62static struct mxc_nand_platform_data mx31lite_nand_board_info = {
63 .width = 1,
64 .hw_ecc = 1,
65};
66
67static struct smsc911x_platform_config smsc911x_config = {
68 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
69 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
70 .flags = SMSC911X_USE_16BIT,
71};
72
73static struct resource smsc911x_resources[] = {
74 {
75 .start = CS4_BASE_ADDR,
76 .end = CS4_BASE_ADDR + 0x100,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
80 .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct platform_device smsc911x_device = {
86 .name = "smsc911x",
87 .id = -1,
88 .num_resources = ARRAY_SIZE(smsc911x_resources),
89 .resource = smsc911x_resources,
90 .dev = {
91 .platform_data = &smsc911x_config,
92 },
93};
94
95/*
96 * This structure defines the MX31 memory map.
97 */
98static struct map_desc mx31lite_io_desc[] __initdata = {
99 {
100 .virtual = SPBA0_BASE_ADDR_VIRT,
101 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
102 .length = SPBA0_SIZE,
103 .type = MT_DEVICE_NONSHARED
104 }, {
105 .virtual = CS4_BASE_ADDR_VIRT,
106 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
107 .length = CS4_SIZE,
108 .type = MT_DEVICE
109 }
110};
111
112/*
113 * Set up static virtual mappings.
114 */
115void __init mx31lite_map_io(void)
116{
117 mx31_map_io();
118 iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
119}
120
121/*
122 * Board specific initialization.
123 */
124static void __init mxc_board_init(void)
125{
126 int ret;
127
128 mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
129 "mx31lite");
130
131 mxc_register_device(&mxc_uart_device0, &uart_pdata);
132 mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
133
134 /* SMSC9117 IRQ pin */
135 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
136 if (ret)
137 pr_warning("could not get LAN irq gpio\n");
138 else {
139 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
140 platform_device_register(&smsc911x_device);
141 }
142}
143
144static void __init mx31lite_timer_init(void)
145{
146 mx31_clocks_init(26000000);
147}
148
149struct sys_timer mx31lite_timer = {
150 .init = mx31lite_timer_init,
151};
152
153/*
154 * The following uses standard kernel macros defined in arch.h in order to
155 * initialize __mach_desc_MX31LITE data structure.
156 */
157
158MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
159 /* Maintainer: Freescale Semiconductor, Inc. */
160 .phys_io = AIPS1_BASE_ADDR,
161 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
162 .boot_params = PHYS_OFFSET + 0x100,
163 .map_io = mx31lite_map_io,
164 .init_irq = mx31_init_irq,
165 .init_machine = mxc_board_init,
166 .timer = &mx31lite_timer,
167MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 5592cdb8d0ad..11b906ce7eae 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -20,13 +20,18 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/slab.h>
23#include <linux/types.h> 24#include <linux/types.h>
24 25
26#include <linux/usb/otg.h>
27
25#include <mach/common.h> 28#include <mach/common.h>
26#include <mach/imx-uart.h> 29#include <mach/imx-uart.h>
27#include <mach/iomux-mx3.h> 30#include <mach/iomux-mx3.h>
28#include <mach/hardware.h> 31#include <mach/hardware.h>
29#include <mach/mmc.h> 32#include <mach/mmc.h>
33#include <mach/mxc_ehci.h>
34#include <mach/ulpi.h>
30 35
31#include "devices.h" 36#include "devices.h"
32 37
@@ -39,6 +44,15 @@ static unsigned int devboard_pins[] = {
39 MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, 44 MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
40 MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, 45 MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
41 MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, 46 MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
47 /* USB H1 */
48 MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
49 MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
50 MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
51 MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
52 MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
53 /* SEL */
54 MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
55 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
42}; 56};
43 57
44static struct imxuart_platform_data uart_pdata = { 58static struct imxuart_platform_data uart_pdata = {
@@ -98,6 +112,107 @@ static struct imxmmc_platform_data sdhc2_pdata = {
98 .exit = devboard_sdhc2_exit, 112 .exit = devboard_sdhc2_exit,
99}; 113};
100 114
115#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
116#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
117#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
118#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
119
120static void devboard_init_sel_gpios(void)
121{
122 if (!gpio_request(SEL0, "sel0")) {
123 gpio_direction_input(SEL0);
124 gpio_export(SEL0, true);
125 }
126
127 if (!gpio_request(SEL1, "sel1")) {
128 gpio_direction_input(SEL1);
129 gpio_export(SEL1, true);
130 }
131
132 if (!gpio_request(SEL2, "sel2")) {
133 gpio_direction_input(SEL2);
134 gpio_export(SEL2, true);
135 }
136
137 if (!gpio_request(SEL3, "sel3")) {
138 gpio_direction_input(SEL3);
139 gpio_export(SEL3, true);
140 }
141}
142#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
143 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
144
145static int devboard_usbh1_hw_init(struct platform_device *pdev)
146{
147 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
148
149 mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
150 mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
151 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
152 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
153 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
154 mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
155 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
156 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
157
158 return 0;
159}
160
161#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
162#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
163
164static int devboard_isp1105_init(struct otg_transceiver *otg)
165{
166 int ret = gpio_request(USBH1_MODE, "usbh1-mode");
167 if (ret)
168 return ret;
169 /* single ended */
170 gpio_direction_output(USBH1_MODE, 0);
171
172 ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
173 if (ret) {
174 gpio_free(USBH1_MODE);
175 return ret;
176 }
177 gpio_direction_output(USBH1_VBUSEN_B, 1);
178
179 return 0;
180}
181
182
183static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
184{
185 if (on)
186 gpio_set_value(USBH1_VBUSEN_B, 0);
187 else
188 gpio_set_value(USBH1_VBUSEN_B, 1);
189
190 return 0;
191}
192
193static struct mxc_usbh_platform_data usbh1_pdata = {
194 .init = devboard_usbh1_hw_init,
195 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
196 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
197};
198
199static int __init devboard_usbh1_init(void)
200{
201 struct otg_transceiver *otg;
202
203 otg = kzalloc(sizeof(*otg), GFP_KERNEL);
204 if (!otg)
205 return -ENOMEM;
206
207 otg->label = "ISP1105";
208 otg->init = devboard_isp1105_init;
209 otg->set_vbus = devboard_isp1105_set_vbus;
210
211 usbh1_pdata.otg = otg;
212
213 return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
214}
215
101/* 216/*
102 * system init for baseboard usage. Will be called by mx31moboard init. 217 * system init for baseboard usage. Will be called by mx31moboard init.
103 */ 218 */
@@ -111,4 +226,8 @@ void __init mx31moboard_devboard_init(void)
111 mxc_register_device(&mxc_uart_device1, &uart_pdata); 226 mxc_register_device(&mxc_uart_device1, &uart_pdata);
112 227
113 mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); 228 mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
229
230 devboard_init_sel_gpios();
231
232 devboard_usbh1_init();
114} 233}
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 2bfaffb344f0..ffb105e14d88 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -16,17 +16,27 @@
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */ 17 */
18 18
19#include <linux/delay.h>
19#include <linux/gpio.h> 20#include <linux/gpio.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/i2c.h>
24#include <linux/spi/spi.h>
25#include <linux/slab.h>
22#include <linux/platform_device.h> 26#include <linux/platform_device.h>
23#include <linux/types.h> 27#include <linux/types.h>
24 28
29#include <linux/usb/otg.h>
30
25#include <mach/common.h> 31#include <mach/common.h>
26#include <mach/hardware.h> 32#include <mach/hardware.h>
27#include <mach/imx-uart.h> 33#include <mach/imx-uart.h>
28#include <mach/iomux-mx3.h> 34#include <mach/iomux-mx3.h>
29#include <mach/mmc.h> 35#include <mach/mmc.h>
36#include <mach/mxc_ehci.h>
37#include <mach/ulpi.h>
38
39#include <media/soc_camera.h>
30 40
31#include "devices.h" 41#include "devices.h"
32 42
@@ -37,7 +47,6 @@ static unsigned int marxbot_pins[] = {
37 MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, 47 MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
38 MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, 48 MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
39 /* CSI */ 49 /* CSI */
40 MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
41 MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, 50 MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
42 MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, 51 MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
43 MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, 52 MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
@@ -45,10 +54,22 @@ static unsigned int marxbot_pins[] = {
45 MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, 54 MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
46 MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, 55 MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
47 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, 56 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
57 MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5,
48 MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, 58 MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
49 MX31_PIN_TXD2__GPIO1_28, 59 MX31_PIN_TXD2__GPIO1_28,
50 /* dsPIC resets */ 60 /* dsPIC resets */
51 MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22, 61 MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
62 /*battery detection */
63 MX31_PIN_LCS0__GPIO3_23,
64 /* USB H1 */
65 MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
66 MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
67 MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
68 MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
69 MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
70 /* SEL */
71 MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
72 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
52}; 73};
53 74
54#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) 75#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
@@ -110,16 +131,204 @@ static struct imxmmc_platform_data sdhc2_pdata = {
110static void dspics_resets_init(void) 131static void dspics_resets_init(void)
111{ 132{
112 if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { 133 if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
113 gpio_direction_output(TRSLAT_RST_B, 1); 134 gpio_direction_output(TRSLAT_RST_B, 0);
114 gpio_export(TRSLAT_RST_B, false); 135 gpio_export(TRSLAT_RST_B, false);
115 } 136 }
116 137
117 if (!gpio_request(DSPICS_RST_B, "dspics-rst")) { 138 if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
118 gpio_direction_output(DSPICS_RST_B, 1); 139 gpio_direction_output(DSPICS_RST_B, 0);
119 gpio_export(DSPICS_RST_B, false); 140 gpio_export(DSPICS_RST_B, false);
120 } 141 }
121} 142}
122 143
144static struct spi_board_info marxbot_spi_board_info[] __initdata = {
145 {
146 .modalias = "spidev",
147 .max_speed_hz = 300000,
148 .bus_num = 1,
149 .chip_select = 1, /* according spi1_cs[] ! */
150 },
151};
152
153#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
154#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
155#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
156#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4)
157#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2)
158
159static int marxbot_basecam_power(struct device *dev, int on)
160{
161 gpio_set_value(BASECAM_POWER, !on);
162 return 0;
163}
164
165static int marxbot_basecam_reset(struct device *dev)
166{
167 gpio_set_value(BASECAM_RST_B, 0);
168 udelay(100);
169 gpio_set_value(BASECAM_RST_B, 1);
170 return 0;
171}
172
173static struct i2c_board_info marxbot_i2c_devices[] = {
174 {
175 I2C_BOARD_INFO("mt9t031", 0x5d),
176 },
177};
178
179static struct soc_camera_link base_iclink = {
180 .bus_id = 0, /* Must match with the camera ID */
181 .power = marxbot_basecam_power,
182 .reset = marxbot_basecam_reset,
183 .board_info = &marxbot_i2c_devices[0],
184 .i2c_adapter_id = 0,
185 .module_name = "mt9t031",
186};
187
188static struct platform_device marxbot_camera[] = {
189 {
190 .name = "soc-camera-pdrv",
191 .id = 0,
192 .dev = {
193 .platform_data = &base_iclink,
194 },
195 },
196};
197
198static struct platform_device *marxbot_cameras[] __initdata = {
199 &marxbot_camera[0],
200};
201
202static int __init marxbot_cam_init(void)
203{
204 int ret = gpio_request(CAM_CHOICE, "cam-choice");
205 if (ret)
206 return ret;
207 gpio_direction_output(CAM_CHOICE, 0);
208
209 ret = gpio_request(BASECAM_RST_B, "basecam-reset");
210 if (ret)
211 return ret;
212 gpio_direction_output(BASECAM_RST_B, 1);
213 ret = gpio_request(BASECAM_POWER, "basecam-standby");
214 if (ret)
215 return ret;
216 gpio_direction_output(BASECAM_POWER, 0);
217
218 ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset");
219 if (ret)
220 return ret;
221 gpio_direction_output(TURRETCAM_RST_B, 1);
222 ret = gpio_request(TURRETCAM_POWER, "turretcam-standby");
223 if (ret)
224 return ret;
225 gpio_direction_output(TURRETCAM_POWER, 0);
226
227 return 0;
228}
229
230#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
231#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
232#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
233#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
234
235static void marxbot_init_sel_gpios(void)
236{
237 if (!gpio_request(SEL0, "sel0")) {
238 gpio_direction_input(SEL0);
239 gpio_export(SEL0, true);
240 }
241
242 if (!gpio_request(SEL1, "sel1")) {
243 gpio_direction_input(SEL1);
244 gpio_export(SEL1, true);
245 }
246
247 if (!gpio_request(SEL2, "sel2")) {
248 gpio_direction_input(SEL2);
249 gpio_export(SEL2, true);
250 }
251
252 if (!gpio_request(SEL3, "sel3")) {
253 gpio_direction_input(SEL3);
254 gpio_export(SEL3, true);
255 }
256}
257
258#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
259 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
260
261static int marxbot_usbh1_hw_init(struct platform_device *pdev)
262{
263 mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
264
265 mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
266 mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
267 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
268 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
269 mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
270 mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
271 mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
272 mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
273
274 return 0;
275}
276
277#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
278#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
279
280static int marxbot_isp1105_init(struct otg_transceiver *otg)
281{
282 int ret = gpio_request(USBH1_MODE, "usbh1-mode");
283 if (ret)
284 return ret;
285 /* single ended */
286 gpio_direction_output(USBH1_MODE, 0);
287
288 ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
289 if (ret) {
290 gpio_free(USBH1_MODE);
291 return ret;
292 }
293 gpio_direction_output(USBH1_VBUSEN_B, 1);
294
295 return 0;
296}
297
298
299static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
300{
301 if (on)
302 gpio_set_value(USBH1_VBUSEN_B, 0);
303 else
304 gpio_set_value(USBH1_VBUSEN_B, 1);
305
306 return 0;
307}
308
309static struct mxc_usbh_platform_data usbh1_pdata = {
310 .init = marxbot_usbh1_hw_init,
311 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
312 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
313};
314
315static int __init marxbot_usbh1_init(void)
316{
317 struct otg_transceiver *otg;
318
319 otg = kzalloc(sizeof(*otg), GFP_KERNEL);
320 if (!otg)
321 return -ENOMEM;
322
323 otg->label = "ISP1105";
324 otg->init = marxbot_isp1105_init;
325 otg->set_vbus = marxbot_isp1105_set_vbus;
326
327 usbh1_pdata.otg = otg;
328
329 return mxc_register_device(&mxc_usbh1, &usbh1_pdata);
330}
331
123/* 332/*
124 * system init for baseboard usage. Will be called by mx31moboard init. 333 * system init for baseboard usage. Will be called by mx31moboard init.
125 */ 334 */
@@ -130,7 +339,22 @@ void __init mx31moboard_marxbot_init(void)
130 mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), 339 mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
131 "marxbot"); 340 "marxbot");
132 341
342 marxbot_init_sel_gpios();
343
133 dspics_resets_init(); 344 dspics_resets_init();
134 345
135 mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); 346 mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
347
348 spi_register_board_info(marxbot_spi_board_info,
349 ARRAY_SIZE(marxbot_spi_board_info));
350
351 marxbot_cam_init();
352 platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras));
353
354 /* battery present pin */
355 gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
356 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
357 gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
358
359 marxbot_usbh1_init();
136} 360}
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
new file mode 100644
index 000000000000..52a69fc8b14f
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -0,0 +1,162 @@
1/*
2 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/delay.h>
20#include <linux/gpio.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
25#include <linux/types.h>
26
27#include <mach/common.h>
28#include <mach/hardware.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx3.h>
31
32#include <media/soc_camera.h>
33
34#include "devices.h"
35
36static unsigned int smartbot_pins[] = {
37 /* UART1 */
38 MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
39 MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
40 /* CSI */
41 MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
42 MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
43 MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
44 MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
45 MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
46 MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
47 MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
48 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
49 MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
50 /* ENABLES */
51 MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
52 MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
53};
54
55static struct imxuart_platform_data uart_pdata = {
56 .flags = IMXUART_HAVE_RTSCTS,
57};
58
59#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
60#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
61
62static int smartbot_cam_power(struct device *dev, int on)
63{
64 gpio_set_value(CAM_POWER, !on);
65 return 0;
66}
67
68static int smartbot_cam_reset(struct device *dev)
69{
70 gpio_set_value(CAM_RST_B, 0);
71 udelay(100);
72 gpio_set_value(CAM_RST_B, 1);
73 return 0;
74}
75
76static struct i2c_board_info smartbot_i2c_devices[] = {
77 {
78 I2C_BOARD_INFO("mt9t031", 0x5d),
79 },
80};
81
82static struct soc_camera_link base_iclink = {
83 .bus_id = 0, /* Must match with the camera ID */
84 .power = smartbot_cam_power,
85 .reset = smartbot_cam_reset,
86 .board_info = &smartbot_i2c_devices[0],
87 .i2c_adapter_id = 0,
88 .module_name = "mt9t031",
89};
90
91static struct platform_device smartbot_camera[] = {
92 {
93 .name = "soc-camera-pdrv",
94 .id = 0,
95 .dev = {
96 .platform_data = &base_iclink,
97 },
98 },
99};
100
101static struct platform_device *smartbot_cameras[] __initdata = {
102 &smartbot_camera[0],
103};
104
105static int __init smartbot_cam_init(void)
106{
107 int ret = gpio_request(CAM_RST_B, "cam-reset");
108 if (ret)
109 return ret;
110 gpio_direction_output(CAM_RST_B, 1);
111 ret = gpio_request(CAM_POWER, "cam-standby");
112 if (ret)
113 return ret;
114 gpio_direction_output(CAM_POWER, 0);
115
116 return 0;
117}
118
119#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
120#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
121#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
122#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
123
124static void smartbot_resets_init(void)
125{
126 if (!gpio_request(POWER_EN, "power-enable")) {
127 gpio_direction_output(POWER_EN, 0);
128 gpio_export(POWER_EN, false);
129 }
130
131 if (!gpio_request(DSPIC_RST_B, "dspic-rst")) {
132 gpio_direction_output(DSPIC_RST_B, 0);
133 gpio_export(DSPIC_RST_B, false);
134 }
135
136 if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
137 gpio_direction_output(TRSLAT_RST_B, 0);
138 gpio_export(TRSLAT_RST_B, false);
139 }
140
141 if (!gpio_request(SEL3, "sel3")) {
142 gpio_direction_input(SEL3);
143 gpio_export(SEL3, true);
144 }
145}
146/*
147 * system init for baseboard usage. Will be called by mx31moboard init.
148 */
149void __init mx31moboard_smartbot_init(void)
150{
151 printk(KERN_INFO "Initializing mx31smartbot peripherals\n");
152
153 mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
154 "smartbot");
155
156 mxc_register_device(&mxc_uart_device1, &uart_pdata);
157
158 smartbot_resets_init();
159
160 smartbot_cam_init();
161 platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras));
162}
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-07 06:08:00 -0400