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path: root/arch/arm/mach-mx3/mx31lite-db.c
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Diffstat (limited to 'arch/arm/mach-mx3/mx31lite-db.c')
-rw-r--r--arch/arm/mach-mx3/mx31lite-db.c30
1 files changed, 21 insertions, 9 deletions
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 694611d6b057..ccd874225c3b 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -67,6 +67,13 @@ static unsigned int litekit_db_board_pins[] __initdata = {
67 MX31_PIN_CSPI1_SS0__SS0, 67 MX31_PIN_CSPI1_SS0__SS0,
68 MX31_PIN_CSPI1_SS1__SS1, 68 MX31_PIN_CSPI1_SS1__SS1,
69 MX31_PIN_CSPI1_SS2__SS2, 69 MX31_PIN_CSPI1_SS2__SS2,
70 /* SDHC1 */
71 MX31_PIN_SD1_DATA0__SD1_DATA0,
72 MX31_PIN_SD1_DATA1__SD1_DATA1,
73 MX31_PIN_SD1_DATA2__SD1_DATA2,
74 MX31_PIN_SD1_DATA3__SD1_DATA3,
75 MX31_PIN_SD1_CLK__SD1_CLK,
76 MX31_PIN_SD1_CMD__SD1_CMD,
70}; 77};
71 78
72/* UART */ 79/* UART */
@@ -79,11 +86,11 @@ static struct imxuart_platform_data uart_pdata __initdata = {
79static int gpio_det, gpio_wp; 86static int gpio_det, gpio_wp;
80 87
81#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ 88#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
82 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 89 PAD_CTL_ODE_CMOS)
83 90
84static int mxc_mmc1_get_ro(struct device *dev) 91static int mxc_mmc1_get_ro(struct device *dev)
85{ 92{
86 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); 93 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
87} 94}
88 95
89static int mxc_mmc1_init(struct device *dev, 96static int mxc_mmc1_init(struct device *dev,
@@ -94,12 +101,17 @@ static int mxc_mmc1_init(struct device *dev,
94 gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); 101 gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
95 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); 102 gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
96 103
97 mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); 104 mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
98 mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); 105 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
99 mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); 106 mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
100 mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); 107 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
108 mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
109 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
110 mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
111 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
112 mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
113 MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
101 mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); 114 mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
102 mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
103 115
104 ret = gpio_request(gpio_det, "MMC detect"); 116 ret = gpio_request(gpio_det, "MMC detect");
105 if (ret) 117 if (ret)
@@ -113,7 +125,7 @@ static int mxc_mmc1_init(struct device *dev,
113 gpio_direction_input(gpio_wp); 125 gpio_direction_input(gpio_wp);
114 126
115 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq, 127 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
116 IRQF_DISABLED | IRQF_TRIGGER_FALLING, 128 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
117 "MMC detect", data); 129 "MMC detect", data);
118 if (ret) 130 if (ret)
119 goto exit_free_wp; 131 goto exit_free_wp;
@@ -133,7 +145,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
133{ 145{
134 gpio_free(gpio_det); 146 gpio_free(gpio_det);
135 gpio_free(gpio_wp); 147 gpio_free(gpio_wp);
136 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); 148 free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
137} 149}
138 150
139static struct imxmmc_platform_data mmc_pdata = { 151static struct imxmmc_platform_data mmc_pdata = {