diff options
Diffstat (limited to 'arch/arm/mach-mx3/crm_regs.h')
| -rw-r--r-- | arch/arm/mach-mx3/crm_regs.h | 153 |
1 files changed, 0 insertions, 153 deletions
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h index 4a0e0ede23bb..adfa3627ad84 100644 --- a/arch/arm/mach-mx3/crm_regs.h +++ b/arch/arm/mach-mx3/crm_regs.h | |||
| @@ -91,47 +91,6 @@ | |||
| 91 | #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 | 91 | #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 |
| 92 | #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 | 92 | #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 |
| 93 | 93 | ||
| 94 | #define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11) | ||
| 95 | #define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11) | ||
| 96 | #define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11) | ||
| 97 | #define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11) | ||
| 98 | #define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11) | ||
| 99 | #define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11) | ||
| 100 | #define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11) | ||
| 101 | #define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11) | ||
| 102 | |||
| 103 | #define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6) | ||
| 104 | #define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6) | ||
| 105 | #define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6) | ||
| 106 | #define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6) | ||
| 107 | |||
| 108 | #define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3) | ||
| 109 | #define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3) | ||
| 110 | #define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3) | ||
| 111 | #define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3) | ||
| 112 | #define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3) | ||
| 113 | #define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3) | ||
| 114 | #define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3) | ||
| 115 | #define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3) | ||
| 116 | |||
| 117 | #define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8) | ||
| 118 | #define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8) | ||
| 119 | #define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8) | ||
| 120 | #define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8) | ||
| 121 | #define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8) | ||
| 122 | #define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8) | ||
| 123 | #define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8) | ||
| 124 | #define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8) | ||
| 125 | |||
| 126 | #define MXC_CCM_PDR0_MCU_DIV_1 0x0 | ||
| 127 | #define MXC_CCM_PDR0_MCU_DIV_2 0x1 | ||
| 128 | #define MXC_CCM_PDR0_MCU_DIV_3 0x2 | ||
| 129 | #define MXC_CCM_PDR0_MCU_DIV_4 0x3 | ||
| 130 | #define MXC_CCM_PDR0_MCU_DIV_5 0x4 | ||
| 131 | #define MXC_CCM_PDR0_MCU_DIV_6 0x5 | ||
| 132 | #define MXC_CCM_PDR0_MCU_DIV_7 0x6 | ||
| 133 | #define MXC_CCM_PDR0_MCU_DIV_8 0x7 | ||
| 134 | |||
| 135 | #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 | 94 | #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 |
| 136 | #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) | 95 | #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) |
| 137 | #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 | 96 | #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 |
| @@ -152,118 +111,6 @@ | |||
| 152 | /* Bit definitions for RCSR */ | 111 | /* Bit definitions for RCSR */ |
| 153 | #define MXC_CCM_RCSR_NF16B 0x80000000 | 112 | #define MXC_CCM_RCSR_NF16B 0x80000000 |
| 154 | 113 | ||
| 155 | /* Bit definitions for both MCU, USB and SR PLL control registers */ | ||
| 156 | #define MXC_CCM_PCTL_BRM 0x80000000 | ||
| 157 | #define MXC_CCM_PCTL_PD_OFFSET 26 | ||
| 158 | #define MXC_CCM_PCTL_PD_MASK (0xF << 26) | ||
| 159 | #define MXC_CCM_PCTL_MFD_OFFSET 16 | ||
| 160 | #define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) | ||
| 161 | #define MXC_CCM_PCTL_MFI_OFFSET 10 | ||
| 162 | #define MXC_CCM_PCTL_MFI_MASK (0xF << 10) | ||
| 163 | #define MXC_CCM_PCTL_MFN_OFFSET 0 | ||
| 164 | #define MXC_CCM_PCTL_MFN_MASK 0x3FF | ||
| 165 | |||
| 166 | #define MXC_CCM_CGR0_SD_MMC1_OFFSET 0 | ||
| 167 | #define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0) | ||
| 168 | #define MXC_CCM_CGR0_SD_MMC2_OFFSET 2 | ||
| 169 | #define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2) | ||
| 170 | #define MXC_CCM_CGR0_GPT_OFFSET 4 | ||
| 171 | #define MXC_CCM_CGR0_GPT_MASK (0x3 << 4) | ||
| 172 | #define MXC_CCM_CGR0_EPIT1_OFFSET 6 | ||
| 173 | #define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6) | ||
| 174 | #define MXC_CCM_CGR0_EPIT2_OFFSET 8 | ||
| 175 | #define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8) | ||
| 176 | #define MXC_CCM_CGR0_IIM_OFFSET 10 | ||
| 177 | #define MXC_CCM_CGR0_IIM_MASK (0x3 << 10) | ||
| 178 | #define MXC_CCM_CGR0_ATA_OFFSET 12 | ||
| 179 | #define MXC_CCM_CGR0_ATA_MASK (0x3 << 12) | ||
| 180 | #define MXC_CCM_CGR0_SDMA_OFFSET 14 | ||
| 181 | #define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14) | ||
| 182 | #define MXC_CCM_CGR0_CSPI3_OFFSET 16 | ||
| 183 | #define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16) | ||
| 184 | #define MXC_CCM_CGR0_RNG_OFFSET 18 | ||
| 185 | #define MXC_CCM_CGR0_RNG_MASK (0x3 << 18) | ||
| 186 | #define MXC_CCM_CGR0_UART1_OFFSET 20 | ||
| 187 | #define MXC_CCM_CGR0_UART1_MASK (0x3 << 20) | ||
| 188 | #define MXC_CCM_CGR0_UART2_OFFSET 22 | ||
| 189 | #define MXC_CCM_CGR0_UART2_MASK (0x3 << 22) | ||
| 190 | #define MXC_CCM_CGR0_SSI1_OFFSET 24 | ||
| 191 | #define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24) | ||
| 192 | #define MXC_CCM_CGR0_I2C1_OFFSET 26 | ||
| 193 | #define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26) | ||
| 194 | #define MXC_CCM_CGR0_I2C2_OFFSET 28 | ||
| 195 | #define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28) | ||
| 196 | #define MXC_CCM_CGR0_I2C3_OFFSET 30 | ||
| 197 | #define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30) | ||
| 198 | |||
| 199 | #define MXC_CCM_CGR1_HANTRO_OFFSET 0 | ||
| 200 | #define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0) | ||
| 201 | #define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2 | ||
| 202 | #define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2) | ||
| 203 | #define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4 | ||
| 204 | #define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4) | ||
| 205 | #define MXC_CCM_CGR1_CSI_OFFSET 6 | ||
| 206 | #define MXC_CCM_CGR1_CSI_MASK (0x3 << 6) | ||
| 207 | #define MXC_CCM_CGR1_RTC_OFFSET 8 | ||
| 208 | #define MXC_CCM_CGR1_RTC_MASK (0x3 << 8) | ||
| 209 | #define MXC_CCM_CGR1_WDOG_OFFSET 10 | ||
| 210 | #define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10) | ||
| 211 | #define MXC_CCM_CGR1_PWM_OFFSET 12 | ||
| 212 | #define MXC_CCM_CGR1_PWM_MASK (0x3 << 12) | ||
| 213 | #define MXC_CCM_CGR1_SIM_OFFSET 14 | ||
| 214 | #define MXC_CCM_CGR1_SIM_MASK (0x3 << 14) | ||
| 215 | #define MXC_CCM_CGR1_ECT_OFFSET 16 | ||
| 216 | #define MXC_CCM_CGR1_ECT_MASK (0x3 << 16) | ||
| 217 | #define MXC_CCM_CGR1_USBOTG_OFFSET 18 | ||
| 218 | #define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18) | ||
| 219 | #define MXC_CCM_CGR1_KPP_OFFSET 20 | ||
| 220 | #define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) | ||
| 221 | #define MXC_CCM_CGR1_IPU_OFFSET 22 | ||
| 222 | #define MXC_CCM_CGR1_IPU_MASK (0x3 << 22) | ||
| 223 | #define MXC_CCM_CGR1_UART3_OFFSET 24 | ||
| 224 | #define MXC_CCM_CGR1_UART3_MASK (0x3 << 24) | ||
| 225 | #define MXC_CCM_CGR1_UART4_OFFSET 26 | ||
| 226 | #define MXC_CCM_CGR1_UART4_MASK (0x3 << 26) | ||
| 227 | #define MXC_CCM_CGR1_UART5_OFFSET 28 | ||
| 228 | #define MXC_CCM_CGR1_UART5_MASK (0x3 << 28) | ||
| 229 | #define MXC_CCM_CGR1_OWIRE_OFFSET 30 | ||
| 230 | #define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30) | ||
| 231 | |||
| 232 | #define MXC_CCM_CGR2_SSI2_OFFSET 0 | ||
| 233 | #define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0) | ||
| 234 | #define MXC_CCM_CGR2_CSPI1_OFFSET 2 | ||
| 235 | #define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2) | ||
| 236 | #define MXC_CCM_CGR2_CSPI2_OFFSET 4 | ||
| 237 | #define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4) | ||
| 238 | #define MXC_CCM_CGR2_GACC_OFFSET 6 | ||
| 239 | #define MXC_CCM_CGR2_GACC_MASK (0x3 << 6) | ||
| 240 | #define MXC_CCM_CGR2_EMI_OFFSET 8 | ||
| 241 | #define MXC_CCM_CGR2_EMI_MASK (0x3 << 8) | ||
| 242 | #define MXC_CCM_CGR2_RTIC_OFFSET 10 | ||
| 243 | #define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10) | ||
| 244 | #define MXC_CCM_CGR2_FIRI_OFFSET 12 | ||
| 245 | #define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12) | ||
| 246 | #define MXC_CCM_CGR2_IPMUX1_OFFSET 14 | ||
| 247 | #define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14) | ||
| 248 | #define MXC_CCM_CGR2_IPMUX2_OFFSET 16 | ||
| 249 | #define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16) | ||
| 250 | |||
| 251 | /* These new CGR2 bits are added in MX32 */ | ||
| 252 | #define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18 | ||
| 253 | #define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18) | ||
| 254 | #define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20 | ||
| 255 | #define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20) | ||
| 256 | #define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22 | ||
| 257 | #define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22) | ||
| 258 | #define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24 | ||
| 259 | #define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24) | ||
| 260 | #define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25 | ||
| 261 | #define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25) | ||
| 262 | #define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26 | ||
| 263 | #define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26) | ||
| 264 | #define MXC_CCM_CGR2_APMENA_OFFSET 30 | ||
| 265 | #define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30) | ||
| 266 | |||
| 267 | /* | 114 | /* |
| 268 | * LTR0 register offsets | 115 | * LTR0 register offsets |
| 269 | */ | 116 | */ |