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-rw-r--r--arch/arm/mach-mx2/devices.c640
1 files changed, 238 insertions, 402 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 3956d82b7c4e..b91e412f7b3e 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -47,65 +47,31 @@
47 * - i.MX21: 2 channel 47 * - i.MX21: 2 channel
48 * - i.MX27: 3 channel 48 * - i.MX27: 3 channel
49 */ 49 */
50static struct resource mxc_spi_resources0[] = { 50#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
51 { 51 static struct resource mxc_spi_resources ## n[] = { \
52 .start = CSPI1_BASE_ADDR, 52 { \
53 .end = CSPI1_BASE_ADDR + SZ_4K - 1, 53 .start = baseaddr, \
54 .flags = IORESOURCE_MEM, 54 .end = baseaddr + SZ_4K - 1, \
55 }, { 55 .flags = IORESOURCE_MEM, \
56 .start = MXC_INT_CSPI1, 56 }, { \
57 .end = MXC_INT_CSPI1, 57 .start = irq, \
58 .flags = IORESOURCE_IRQ, 58 .end = irq, \
59 }, 59 .flags = IORESOURCE_IRQ, \
60}; 60 }, \
61 61 }; \
62static struct resource mxc_spi_resources1[] = { 62 \
63 { 63 struct platform_device mxc_spi_device ## n = { \
64 .start = CSPI2_BASE_ADDR, 64 .name = "spi_imx", \
65 .end = CSPI2_BASE_ADDR + SZ_4K - 1, 65 .id = n, \
66 .flags = IORESOURCE_MEM, 66 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
67 }, { 67 .resource = mxc_spi_resources ## n, \
68 .start = MXC_INT_CSPI2, 68 }
69 .end = MXC_INT_CSPI2,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74#ifdef CONFIG_MACH_MX27
75static struct resource mxc_spi_resources2[] = {
76 {
77 .start = CSPI3_BASE_ADDR,
78 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
79 .flags = IORESOURCE_MEM,
80 }, {
81 .start = MXC_INT_CSPI3,
82 .end = MXC_INT_CSPI3,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86#endif
87
88struct platform_device mxc_spi_device0 = {
89 .name = "spi_imx",
90 .id = 0,
91 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
92 .resource = mxc_spi_resources0,
93};
94 69
95struct platform_device mxc_spi_device1 = { 70DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
96 .name = "spi_imx", 71DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
97 .id = 1,
98 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
99 .resource = mxc_spi_resources1,
100};
101 72
102#ifdef CONFIG_MACH_MX27 73#ifdef CONFIG_MACH_MX27
103struct platform_device mxc_spi_device2 = { 74DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
104 .name = "spi_imx",
105 .id = 2,
106 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
107 .resource = mxc_spi_resources2,
108};
109#endif 75#endif
110 76
111/* 77/*
@@ -113,104 +79,34 @@ struct platform_device mxc_spi_device2 = {
113 * - i.MX21: 3 timers 79 * - i.MX21: 3 timers
114 * - i.MX27: 6 timers 80 * - i.MX27: 6 timers
115 */ 81 */
116 82#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
117/* We use gpt0 as system timer, so do not add a device for this one */ 83 static struct resource timer ## n ##_resources[] = { \
118 84 { \
119static struct resource timer1_resources[] = { 85 .start = baseaddr, \
120 { 86 .end = baseaddr + SZ_4K - 1, \
121 .start = GPT2_BASE_ADDR, 87 .flags = IORESOURCE_MEM, \
122 .end = GPT2_BASE_ADDR + 0x17, 88 }, { \
123 .flags = IORESOURCE_MEM, 89 .start = irq, \
124 }, { 90 .end = irq, \
125 .start = MXC_INT_GPT2, 91 .flags = IORESOURCE_IRQ, \
126 .end = MXC_INT_GPT2, 92 } \
127 .flags = IORESOURCE_IRQ, 93 }; \
128 } 94 \
129}; 95 struct platform_device mxc_gpt ## n = { \
130 96 .name = "imx_gpt", \
131struct platform_device mxc_gpt1 = { 97 .id = n, \
132 .name = "imx_gpt", 98 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
133 .id = 1, 99 .resource = timer ## n ## _resources, \
134 .num_resources = ARRAY_SIZE(timer1_resources),
135 .resource = timer1_resources,
136};
137
138static struct resource timer2_resources[] = {
139 {
140 .start = GPT3_BASE_ADDR,
141 .end = GPT3_BASE_ADDR + 0x17,
142 .flags = IORESOURCE_MEM,
143 }, {
144 .start = MXC_INT_GPT3,
145 .end = MXC_INT_GPT3,
146 .flags = IORESOURCE_IRQ,
147 } 100 }
148};
149 101
150struct platform_device mxc_gpt2 = { 102/* We use gpt1 as system timer, so do not add a device for this one */
151 .name = "imx_gpt", 103DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
152 .id = 2, 104DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
153 .num_resources = ARRAY_SIZE(timer2_resources),
154 .resource = timer2_resources,
155};
156 105
157#ifdef CONFIG_MACH_MX27 106#ifdef CONFIG_MACH_MX27
158static struct resource timer3_resources[] = { 107DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
159 { 108DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
160 .start = GPT4_BASE_ADDR, 109DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
161 .end = GPT4_BASE_ADDR + 0x17,
162 .flags = IORESOURCE_MEM,
163 }, {
164 .start = MXC_INT_GPT4,
165 .end = MXC_INT_GPT4,
166 .flags = IORESOURCE_IRQ,
167 }
168};
169
170struct platform_device mxc_gpt3 = {
171 .name = "imx_gpt",
172 .id = 3,
173 .num_resources = ARRAY_SIZE(timer3_resources),
174 .resource = timer3_resources,
175};
176
177static struct resource timer4_resources[] = {
178 {
179 .start = GPT5_BASE_ADDR,
180 .end = GPT5_BASE_ADDR + 0x17,
181 .flags = IORESOURCE_MEM,
182 }, {
183 .start = MXC_INT_GPT5,
184 .end = MXC_INT_GPT5,
185 .flags = IORESOURCE_IRQ,
186 }
187};
188
189struct platform_device mxc_gpt4 = {
190 .name = "imx_gpt",
191 .id = 4,
192 .num_resources = ARRAY_SIZE(timer4_resources),
193 .resource = timer4_resources,
194};
195
196static struct resource timer5_resources[] = {
197 {
198 .start = GPT6_BASE_ADDR,
199 .end = GPT6_BASE_ADDR + 0x17,
200 .flags = IORESOURCE_MEM,
201 }, {
202 .start = MXC_INT_GPT6,
203 .end = MXC_INT_GPT6,
204 .flags = IORESOURCE_IRQ,
205 }
206};
207
208struct platform_device mxc_gpt5 = {
209 .name = "imx_gpt",
210 .id = 5,
211 .num_resources = ARRAY_SIZE(timer5_resources),
212 .resource = timer5_resources,
213};
214#endif 110#endif
215 111
216/* 112/*
@@ -221,9 +117,9 @@ struct platform_device mxc_gpt5 = {
221 */ 117 */
222static struct resource mxc_wdt_resources[] = { 118static struct resource mxc_wdt_resources[] = {
223 { 119 {
224 .start = WDOG_BASE_ADDR, 120 .start = MX2x_WDOG_BASE_ADDR,
225 .end = WDOG_BASE_ADDR + 0x30, 121 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
226 .flags = IORESOURCE_MEM, 122 .flags = IORESOURCE_MEM,
227 }, 123 },
228}; 124};
229 125
@@ -236,8 +132,8 @@ struct platform_device mxc_wdt = {
236 132
237static struct resource mxc_w1_master_resources[] = { 133static struct resource mxc_w1_master_resources[] = {
238 { 134 {
239 .start = OWIRE_BASE_ADDR, 135 .start = MX2x_OWIRE_BASE_ADDR,
240 .end = OWIRE_BASE_ADDR + SZ_4K - 1, 136 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
241 .flags = IORESOURCE_MEM, 137 .flags = IORESOURCE_MEM,
242 }, 138 },
243}; 139};
@@ -249,24 +145,33 @@ struct platform_device mxc_w1_master_device = {
249 .resource = mxc_w1_master_resources, 145 .resource = mxc_w1_master_resources,
250}; 146};
251 147
252static struct resource mxc_nand_resources[] = { 148#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
253 { 149 static struct resource pfx ## _nand_resources[] = { \
254 .start = NFC_BASE_ADDR, 150 { \
255 .end = NFC_BASE_ADDR + 0xfff, 151 .start = baseaddr, \
256 .flags = IORESOURCE_MEM, 152 .end = baseaddr + SZ_4K - 1, \
257 }, { 153 .flags = IORESOURCE_MEM, \
258 .start = MXC_INT_NANDFC, 154 }, { \
259 .end = MXC_INT_NANDFC, 155 .start = irq, \
260 .flags = IORESOURCE_IRQ, 156 .end = irq, \
261 }, 157 .flags = IORESOURCE_IRQ, \
262}; 158 }, \
159 }; \
160 \
161 struct platform_device pfx ## _nand_device = { \
162 .name = "mxc_nand", \
163 .id = 0, \
164 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
165 .resource = pfx ## _nand_resources, \
166 }
263 167
264struct platform_device mxc_nand_device = { 168#ifdef CONFIG_MACH_MX21
265 .name = "mxc_nand", 169DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
266 .id = 0, 170#endif
267 .num_resources = ARRAY_SIZE(mxc_nand_resources), 171
268 .resource = mxc_nand_resources, 172#ifdef CONFIG_MACH_MX27
269}; 173DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
174#endif
270 175
271/* 176/*
272 * lcdc: 177 * lcdc:
@@ -276,12 +181,12 @@ struct platform_device mxc_nand_device = {
276 */ 181 */
277static struct resource mxc_fb[] = { 182static struct resource mxc_fb[] = {
278 { 183 {
279 .start = LCDC_BASE_ADDR, 184 .start = MX2x_LCDC_BASE_ADDR,
280 .end = LCDC_BASE_ADDR + 0xFFF, 185 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
281 .flags = IORESOURCE_MEM, 186 .flags = IORESOURCE_MEM,
282 }, { 187 }, {
283 .start = MXC_INT_LCDC, 188 .start = MX2x_INT_LCDC,
284 .end = MXC_INT_LCDC, 189 .end = MX2x_INT_LCDC,
285 .flags = IORESOURCE_IRQ, 190 .flags = IORESOURCE_IRQ,
286 } 191 }
287}; 192};
@@ -300,13 +205,13 @@ struct platform_device mxc_fb_device = {
300#ifdef CONFIG_MACH_MX27 205#ifdef CONFIG_MACH_MX27
301static struct resource mxc_fec_resources[] = { 206static struct resource mxc_fec_resources[] = {
302 { 207 {
303 .start = FEC_BASE_ADDR, 208 .start = MX27_FEC_BASE_ADDR,
304 .end = FEC_BASE_ADDR + 0xfff, 209 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
305 .flags = IORESOURCE_MEM, 210 .flags = IORESOURCE_MEM,
306 }, { 211 }, {
307 .start = MXC_INT_FEC, 212 .start = MX27_INT_FEC,
308 .end = MXC_INT_FEC, 213 .end = MX27_INT_FEC,
309 .flags = IORESOURCE_IRQ, 214 .flags = IORESOURCE_IRQ,
310 }, 215 },
311}; 216};
312 217
@@ -318,55 +223,41 @@ struct platform_device mxc_fec_device = {
318}; 223};
319#endif 224#endif
320 225
321static struct resource mxc_i2c_1_resources[] = { 226#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
322 { 227 static struct resource mxc_i2c_resources ## n[] = { \
323 .start = I2C_BASE_ADDR, 228 { \
324 .end = I2C_BASE_ADDR + 0x0fff, 229 .start = baseaddr, \
325 .flags = IORESOURCE_MEM, 230 .end = baseaddr + SZ_4K - 1, \
326 }, { 231 .flags = IORESOURCE_MEM, \
327 .start = MXC_INT_I2C, 232 }, { \
328 .end = MXC_INT_I2C, 233 .start = irq, \
329 .flags = IORESOURCE_IRQ, 234 .end = irq, \
235 .flags = IORESOURCE_IRQ, \
236 } \
237 }; \
238 \
239 struct platform_device mxc_i2c_device ## n = { \
240 .name = "imx-i2c", \
241 .id = n, \
242 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
243 .resource = mxc_i2c_resources ## n, \
330 } 244 }
331};
332 245
333struct platform_device mxc_i2c_device0 = { 246DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
334 .name = "imx-i2c",
335 .id = 0,
336 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
337 .resource = mxc_i2c_1_resources,
338};
339 247
340#ifdef CONFIG_MACH_MX27 248#ifdef CONFIG_MACH_MX27
341static struct resource mxc_i2c_2_resources[] = { 249DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
342 {
343 .start = I2C2_BASE_ADDR,
344 .end = I2C2_BASE_ADDR + 0x0fff,
345 .flags = IORESOURCE_MEM,
346 }, {
347 .start = MXC_INT_I2C2,
348 .end = MXC_INT_I2C2,
349 .flags = IORESOURCE_IRQ,
350 }
351};
352
353struct platform_device mxc_i2c_device1 = {
354 .name = "imx-i2c",
355 .id = 1,
356 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
357 .resource = mxc_i2c_2_resources,
358};
359#endif 250#endif
360 251
361static struct resource mxc_pwm_resources[] = { 252static struct resource mxc_pwm_resources[] = {
362 { 253 {
363 .start = PWM_BASE_ADDR, 254 .start = MX2x_PWM_BASE_ADDR,
364 .end = PWM_BASE_ADDR + 0x0fff, 255 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
365 .flags = IORESOURCE_MEM, 256 .flags = IORESOURCE_MEM,
366 }, { 257 }, {
367 .start = MXC_INT_PWM, 258 .start = MX2x_INT_PWM,
368 .end = MXC_INT_PWM, 259 .end = MX2x_INT_PWM,
369 .flags = IORESOURCE_IRQ, 260 .flags = IORESOURCE_IRQ,
370 } 261 }
371}; 262};
372 263
@@ -377,77 +268,49 @@ struct platform_device mxc_pwm_device = {
377 .resource = mxc_pwm_resources, 268 .resource = mxc_pwm_resources,
378}; 269};
379 270
380/* 271#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
381 * Resource definition for the MXC SDHC 272 static struct resource mxc_sdhc_resources ## n[] = { \
382 */ 273 { \
383static struct resource mxc_sdhc1_resources[] = { 274 .start = baseaddr, \
384 { 275 .end = baseaddr + SZ_4K - 1, \
385 .start = SDHC1_BASE_ADDR, 276 .flags = IORESOURCE_MEM, \
386 .end = SDHC1_BASE_ADDR + SZ_4K - 1, 277 }, { \
387 .flags = IORESOURCE_MEM, 278 .start = irq, \
388 }, { 279 .end = irq, \
389 .start = MXC_INT_SDHC1, 280 .flags = IORESOURCE_IRQ, \
390 .end = MXC_INT_SDHC1, 281 }, { \
391 .flags = IORESOURCE_IRQ, 282 .start = dmareq, \
392 }, { 283 .end = dmareq, \
393 .start = DMA_REQ_SDHC1, 284 .flags = IORESOURCE_DMA, \
394 .end = DMA_REQ_SDHC1, 285 }, \
395 .flags = IORESOURCE_DMA, 286 }; \
396 }, 287 \
397}; 288 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
398 289 \
399static u64 mxc_sdhc1_dmamask = DMA_BIT_MASK(32); 290 struct platform_device mxc_sdhc_device ## n = { \
400 291 .name = "mxc-mmc", \
401struct platform_device mxc_sdhc_device0 = { 292 .id = n, \
402 .name = "mxc-mmc", 293 .dev = { \
403 .id = 0, 294 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
404 .dev = { 295 .coherent_dma_mask = DMA_BIT_MASK(32), \
405 .dma_mask = &mxc_sdhc1_dmamask, 296 }, \
406 .coherent_dma_mask = DMA_BIT_MASK(32), 297 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
407 }, 298 .resource = mxc_sdhc_resources ## n, \
408 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), 299 }
409 .resource = mxc_sdhc1_resources,
410};
411
412static struct resource mxc_sdhc2_resources[] = {
413 {
414 .start = SDHC2_BASE_ADDR,
415 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
416 .flags = IORESOURCE_MEM,
417 }, {
418 .start = MXC_INT_SDHC2,
419 .end = MXC_INT_SDHC2,
420 .flags = IORESOURCE_IRQ,
421 }, {
422 .start = DMA_REQ_SDHC2,
423 .end = DMA_REQ_SDHC2,
424 .flags = IORESOURCE_DMA,
425 },
426};
427
428static u64 mxc_sdhc2_dmamask = DMA_BIT_MASK(32);
429 300
430struct platform_device mxc_sdhc_device1 = { 301DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
431 .name = "mxc-mmc", 302DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
432 .id = 1,
433 .dev = {
434 .dma_mask = &mxc_sdhc2_dmamask,
435 .coherent_dma_mask = DMA_BIT_MASK(32),
436 },
437 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
438 .resource = mxc_sdhc2_resources,
439};
440 303
441#ifdef CONFIG_MACH_MX27 304#ifdef CONFIG_MACH_MX27
442static struct resource otg_resources[] = { 305static struct resource otg_resources[] = {
443 { 306 {
444 .start = OTG_BASE_ADDR, 307 .start = MX27_USBOTG_BASE_ADDR,
445 .end = OTG_BASE_ADDR + 0x1ff, 308 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
446 .flags = IORESOURCE_MEM, 309 .flags = IORESOURCE_MEM,
447 }, { 310 }, {
448 .start = MXC_INT_USB3, 311 .start = MX27_INT_USB3,
449 .end = MXC_INT_USB3, 312 .end = MX27_INT_USB3,
450 .flags = IORESOURCE_IRQ, 313 .flags = IORESOURCE_IRQ,
451 }, 314 },
452}; 315};
453 316
@@ -483,12 +346,12 @@ static u64 usbh1_dmamask = DMA_BIT_MASK(32);
483 346
484static struct resource mxc_usbh1_resources[] = { 347static struct resource mxc_usbh1_resources[] = {
485 { 348 {
486 .start = OTG_BASE_ADDR + 0x200, 349 .start = MX27_USBOTG_BASE_ADDR + 0x200,
487 .end = OTG_BASE_ADDR + 0x3ff, 350 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
488 .flags = IORESOURCE_MEM, 351 .flags = IORESOURCE_MEM,
489 }, { 352 }, {
490 .start = MXC_INT_USB1, 353 .start = MX27_INT_USB1,
491 .end = MXC_INT_USB1, 354 .end = MX27_INT_USB1,
492 .flags = IORESOURCE_IRQ, 355 .flags = IORESOURCE_IRQ,
493 }, 356 },
494}; 357};
@@ -509,12 +372,12 @@ static u64 usbh2_dmamask = DMA_BIT_MASK(32);
509 372
510static struct resource mxc_usbh2_resources[] = { 373static struct resource mxc_usbh2_resources[] = {
511 { 374 {
512 .start = OTG_BASE_ADDR + 0x400, 375 .start = MX27_USBOTG_BASE_ADDR + 0x400,
513 .end = OTG_BASE_ADDR + 0x5ff, 376 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
514 .flags = IORESOURCE_MEM, 377 .flags = IORESOURCE_MEM,
515 }, { 378 }, {
516 .start = MXC_INT_USB2, 379 .start = MX27_INT_USB2,
517 .end = MXC_INT_USB2, 380 .end = MX27_INT_USB2,
518 .flags = IORESOURCE_IRQ, 381 .flags = IORESOURCE_IRQ,
519 }, 382 },
520}; 383};
@@ -531,129 +394,102 @@ struct platform_device mxc_usbh2 = {
531}; 394};
532#endif 395#endif
533 396
534static struct resource imx_ssi_resources0[] = { 397#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
535 { 398 { \
536 .start = SSI1_BASE_ADDR, 399 .name = _name, \
537 .end = SSI1_BASE_ADDR + 0x6F, 400 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
538 .flags = IORESOURCE_MEM, 401 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
539 }, { 402 .flags = IORESOURCE_DMA, \
540 .start = MXC_INT_SSI1, 403 }
541 .end = MXC_INT_SSI1,
542 .flags = IORESOURCE_IRQ,
543 }, {
544 .name = "tx0",
545 .start = DMA_REQ_SSI1_TX0,
546 .end = DMA_REQ_SSI1_TX0,
547 .flags = IORESOURCE_DMA,
548 }, {
549 .name = "rx0",
550 .start = DMA_REQ_SSI1_RX0,
551 .end = DMA_REQ_SSI1_RX0,
552 .flags = IORESOURCE_DMA,
553 }, {
554 .name = "tx1",
555 .start = DMA_REQ_SSI1_TX1,
556 .end = DMA_REQ_SSI1_TX1,
557 .flags = IORESOURCE_DMA,
558 }, {
559 .name = "rx1",
560 .start = DMA_REQ_SSI1_RX1,
561 .end = DMA_REQ_SSI1_RX1,
562 .flags = IORESOURCE_DMA,
563 },
564};
565
566static struct resource imx_ssi_resources1[] = {
567 {
568 .start = SSI2_BASE_ADDR,
569 .end = SSI2_BASE_ADDR + 0x6F,
570 .flags = IORESOURCE_MEM,
571 }, {
572 .start = MXC_INT_SSI2,
573 .end = MXC_INT_SSI2,
574 .flags = IORESOURCE_IRQ,
575 }, {
576 .name = "tx0",
577 .start = DMA_REQ_SSI2_TX0,
578 .end = DMA_REQ_SSI2_TX0,
579 .flags = IORESOURCE_DMA,
580 }, {
581 .name = "rx0",
582 .start = DMA_REQ_SSI2_RX0,
583 .end = DMA_REQ_SSI2_RX0,
584 .flags = IORESOURCE_DMA,
585 }, {
586 .name = "tx1",
587 .start = DMA_REQ_SSI2_TX1,
588 .end = DMA_REQ_SSI2_TX1,
589 .flags = IORESOURCE_DMA,
590 }, {
591 .name = "rx1",
592 .start = DMA_REQ_SSI2_RX1,
593 .end = DMA_REQ_SSI2_RX1,
594 .flags = IORESOURCE_DMA,
595 },
596};
597 404
598struct platform_device imx_ssi_device0 = { 405#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
599 .name = "imx-ssi", 406 static struct resource imx_ssi_resources ## n[] = { \
600 .id = 0, 407 { \
601 .num_resources = ARRAY_SIZE(imx_ssi_resources0), 408 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
602 .resource = imx_ssi_resources0, 409 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
603}; 410 .flags = IORESOURCE_MEM, \
411 }, { \
412 .start = MX2x_INT_SSI1, \
413 .end = MX2x_INT_SSI1, \
414 .flags = IORESOURCE_IRQ, \
415 }, \
416 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
417 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
418 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
419 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
420 }; \
421 \
422 struct platform_device imx_ssi_device ## n = { \
423 .name = "imx-ssi", \
424 .id = n, \
425 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
426 .resource = imx_ssi_resources ## n, \
427 }
604 428
605struct platform_device imx_ssi_device1 = { 429DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
606 .name = "imx-ssi", 430DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
607 .id = 1,
608 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
609 .resource = imx_ssi_resources1,
610};
611 431
612/* GPIO port description */ 432/* GPIO port description */
613static struct mxc_gpio_port imx_gpio_ports[] = { 433#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
614 { 434 { \
615 .chip.label = "gpio-0", 435 .chip.label = "gpio-" #n, \
616 .irq = MXC_INT_GPIO, 436 .irq = _irq, \
617 .base = IO_ADDRESS(GPIO_BASE_ADDR), 437 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
618 .virtual_irq_start = MXC_GPIO_IRQ_START, 438 n * 0x100), \
619 }, { 439 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
620 .chip.label = "gpio-1",
621 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
622 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
623 }, {
624 .chip.label = "gpio-2",
625 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
626 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
627 }, {
628 .chip.label = "gpio-3",
629 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
630 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
631 }, {
632 .chip.label = "gpio-4",
633 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
634 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
635 }, {
636 .chip.label = "gpio-5",
637 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
638 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
639 } 440 }
640}; 441
442#define DEFINE_MXC_GPIO_PORT(SOC, n) \
443 { \
444 .chip.label = "gpio-" #n, \
445 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
446 n * 0x100), \
447 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
448 }
449
450#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
451 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
452 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
453 DEFINE_MXC_GPIO_PORT(SOC, 1), \
454 DEFINE_MXC_GPIO_PORT(SOC, 2), \
455 DEFINE_MXC_GPIO_PORT(SOC, 3), \
456 DEFINE_MXC_GPIO_PORT(SOC, 4), \
457 DEFINE_MXC_GPIO_PORT(SOC, 5), \
458 }
459
460#ifdef CONFIG_MACH_MX21
461DEFINE_MXC_GPIO_PORTS(MX21, imx21);
462#endif
463
464#ifdef CONFIG_MACH_MX27
465DEFINE_MXC_GPIO_PORTS(MX27, imx27);
466#endif
641 467
642int __init mxc_register_gpios(void) 468int __init mxc_register_gpios(void)
643{ 469{
644 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 470#ifdef CONFIG_MACH_MX21
471 if (cpu_is_mx21())
472 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
473 else
474#endif
475#ifdef CONFIG_MACH_MX27
476 if (cpu_is_mx27())
477 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
478 else
479#endif
480 return 0;
645} 481}
646 482
647#ifdef CONFIG_MACH_MX21 483#ifdef CONFIG_MACH_MX21
648static struct resource mx21_usbhc_resources[] = { 484static struct resource mx21_usbhc_resources[] = {
649 { 485 {
650 .start = USBOTG_BASE_ADDR, 486 .start = MX21_BASE_ADDR,
651 .end = USBOTG_BASE_ADDR + 0x1FFF, 487 .end = MX21_BASE_ADDR + 0x1FFF,
652 .flags = IORESOURCE_MEM, 488 .flags = IORESOURCE_MEM,
653 }, 489 },
654 { 490 {
655 .start = MXC_INT_USBHOST, 491 .start = MX21_INT_USBHOST,
656 .end = MXC_INT_USBHOST, 492 .end = MX21_INT_USBHOST,
657 .flags = IORESOURCE_IRQ, 493 .flags = IORESOURCE_IRQ,
658 }, 494 },
659}; 495};
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 00:20:00 -0400