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-rw-r--r--arch/arm/mach-mx2/devices.c604
1 files changed, 273 insertions, 331 deletions
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 50199aff0143..b91e412f7b3e 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -31,6 +31,7 @@
31#include <linux/init.h> 31#include <linux/init.h>
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <linux/gpio.h> 33#include <linux/gpio.h>
34#include <linux/dma-mapping.h>
34 35
35#include <mach/irqs.h> 36#include <mach/irqs.h>
36#include <mach/hardware.h> 37#include <mach/hardware.h>
@@ -46,65 +47,31 @@
46 * - i.MX21: 2 channel 47 * - i.MX21: 2 channel
47 * - i.MX27: 3 channel 48 * - i.MX27: 3 channel
48 */ 49 */
49static struct resource mxc_spi_resources0[] = { 50#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
50 { 51 static struct resource mxc_spi_resources ## n[] = { \
51 .start = CSPI1_BASE_ADDR, 52 { \
52 .end = CSPI1_BASE_ADDR + SZ_4K - 1, 53 .start = baseaddr, \
53 .flags = IORESOURCE_MEM, 54 .end = baseaddr + SZ_4K - 1, \
54 }, { 55 .flags = IORESOURCE_MEM, \
55 .start = MXC_INT_CSPI1, 56 }, { \
56 .end = MXC_INT_CSPI1, 57 .start = irq, \
57 .flags = IORESOURCE_IRQ, 58 .end = irq, \
58 }, 59 .flags = IORESOURCE_IRQ, \
59}; 60 }, \
60 61 }; \
61static struct resource mxc_spi_resources1[] = { 62 \
62 { 63 struct platform_device mxc_spi_device ## n = { \
63 .start = CSPI2_BASE_ADDR, 64 .name = "spi_imx", \
64 .end = CSPI2_BASE_ADDR + SZ_4K - 1, 65 .id = n, \
65 .flags = IORESOURCE_MEM, 66 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
66 }, { 67 .resource = mxc_spi_resources ## n, \
67 .start = MXC_INT_CSPI2, 68 }
68 .end = MXC_INT_CSPI2,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73#ifdef CONFIG_MACH_MX27
74static struct resource mxc_spi_resources2[] = {
75 {
76 .start = CSPI3_BASE_ADDR,
77 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
78 .flags = IORESOURCE_MEM,
79 }, {
80 .start = MXC_INT_CSPI3,
81 .end = MXC_INT_CSPI3,
82 .flags = IORESOURCE_IRQ,
83 },
84};
85#endif
86
87struct platform_device mxc_spi_device0 = {
88 .name = "spi_imx",
89 .id = 0,
90 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
91 .resource = mxc_spi_resources0,
92};
93 69
94struct platform_device mxc_spi_device1 = { 70DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
95 .name = "spi_imx", 71DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
96 .id = 1,
97 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
98 .resource = mxc_spi_resources1,
99};
100 72
101#ifdef CONFIG_MACH_MX27 73#ifdef CONFIG_MACH_MX27
102struct platform_device mxc_spi_device2 = { 74DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
103 .name = "spi_imx",
104 .id = 2,
105 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
106 .resource = mxc_spi_resources2,
107};
108#endif 75#endif
109 76
110/* 77/*
@@ -112,104 +79,34 @@ struct platform_device mxc_spi_device2 = {
112 * - i.MX21: 3 timers 79 * - i.MX21: 3 timers
113 * - i.MX27: 6 timers 80 * - i.MX27: 6 timers
114 */ 81 */
115 82#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
116/* We use gpt0 as system timer, so do not add a device for this one */ 83 static struct resource timer ## n ##_resources[] = { \
117 84 { \
118static struct resource timer1_resources[] = { 85 .start = baseaddr, \
119 { 86 .end = baseaddr + SZ_4K - 1, \
120 .start = GPT2_BASE_ADDR, 87 .flags = IORESOURCE_MEM, \
121 .end = GPT2_BASE_ADDR + 0x17, 88 }, { \
122 .flags = IORESOURCE_MEM, 89 .start = irq, \
123 }, { 90 .end = irq, \
124 .start = MXC_INT_GPT2, 91 .flags = IORESOURCE_IRQ, \
125 .end = MXC_INT_GPT2, 92 } \
126 .flags = IORESOURCE_IRQ, 93 }; \
127 } 94 \
128}; 95 struct platform_device mxc_gpt ## n = { \
129 96 .name = "imx_gpt", \
130struct platform_device mxc_gpt1 = { 97 .id = n, \
131 .name = "imx_gpt", 98 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
132 .id = 1, 99 .resource = timer ## n ## _resources, \
133 .num_resources = ARRAY_SIZE(timer1_resources),
134 .resource = timer1_resources,
135};
136
137static struct resource timer2_resources[] = {
138 {
139 .start = GPT3_BASE_ADDR,
140 .end = GPT3_BASE_ADDR + 0x17,
141 .flags = IORESOURCE_MEM,
142 }, {
143 .start = MXC_INT_GPT3,
144 .end = MXC_INT_GPT3,
145 .flags = IORESOURCE_IRQ,
146 } 100 }
147};
148 101
149struct platform_device mxc_gpt2 = { 102/* We use gpt1 as system timer, so do not add a device for this one */
150 .name = "imx_gpt", 103DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
151 .id = 2, 104DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
152 .num_resources = ARRAY_SIZE(timer2_resources),
153 .resource = timer2_resources,
154};
155 105
156#ifdef CONFIG_MACH_MX27 106#ifdef CONFIG_MACH_MX27
157static struct resource timer3_resources[] = { 107DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
158 { 108DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
159 .start = GPT4_BASE_ADDR, 109DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
160 .end = GPT4_BASE_ADDR + 0x17,
161 .flags = IORESOURCE_MEM,
162 }, {
163 .start = MXC_INT_GPT4,
164 .end = MXC_INT_GPT4,
165 .flags = IORESOURCE_IRQ,
166 }
167};
168
169struct platform_device mxc_gpt3 = {
170 .name = "imx_gpt",
171 .id = 3,
172 .num_resources = ARRAY_SIZE(timer3_resources),
173 .resource = timer3_resources,
174};
175
176static struct resource timer4_resources[] = {
177 {
178 .start = GPT5_BASE_ADDR,
179 .end = GPT5_BASE_ADDR + 0x17,
180 .flags = IORESOURCE_MEM,
181 }, {
182 .start = MXC_INT_GPT5,
183 .end = MXC_INT_GPT5,
184 .flags = IORESOURCE_IRQ,
185 }
186};
187
188struct platform_device mxc_gpt4 = {
189 .name = "imx_gpt",
190 .id = 4,
191 .num_resources = ARRAY_SIZE(timer4_resources),
192 .resource = timer4_resources,
193};
194
195static struct resource timer5_resources[] = {
196 {
197 .start = GPT6_BASE_ADDR,
198 .end = GPT6_BASE_ADDR + 0x17,
199 .flags = IORESOURCE_MEM,
200 }, {
201 .start = MXC_INT_GPT6,
202 .end = MXC_INT_GPT6,
203 .flags = IORESOURCE_IRQ,
204 }
205};
206
207struct platform_device mxc_gpt5 = {
208 .name = "imx_gpt",
209 .id = 5,
210 .num_resources = ARRAY_SIZE(timer5_resources),
211 .resource = timer5_resources,
212};
213#endif 110#endif
214 111
215/* 112/*
@@ -220,9 +117,9 @@ struct platform_device mxc_gpt5 = {
220 */ 117 */
221static struct resource mxc_wdt_resources[] = { 118static struct resource mxc_wdt_resources[] = {
222 { 119 {
223 .start = WDOG_BASE_ADDR, 120 .start = MX2x_WDOG_BASE_ADDR,
224 .end = WDOG_BASE_ADDR + 0x30, 121 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
225 .flags = IORESOURCE_MEM, 122 .flags = IORESOURCE_MEM,
226 }, 123 },
227}; 124};
228 125
@@ -235,8 +132,8 @@ struct platform_device mxc_wdt = {
235 132
236static struct resource mxc_w1_master_resources[] = { 133static struct resource mxc_w1_master_resources[] = {
237 { 134 {
238 .start = OWIRE_BASE_ADDR, 135 .start = MX2x_OWIRE_BASE_ADDR,
239 .end = OWIRE_BASE_ADDR + SZ_4K - 1, 136 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
240 .flags = IORESOURCE_MEM, 137 .flags = IORESOURCE_MEM,
241 }, 138 },
242}; 139};
@@ -248,24 +145,33 @@ struct platform_device mxc_w1_master_device = {
248 .resource = mxc_w1_master_resources, 145 .resource = mxc_w1_master_resources,
249}; 146};
250 147
251static struct resource mxc_nand_resources[] = { 148#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
252 { 149 static struct resource pfx ## _nand_resources[] = { \
253 .start = NFC_BASE_ADDR, 150 { \
254 .end = NFC_BASE_ADDR + 0xfff, 151 .start = baseaddr, \
255 .flags = IORESOURCE_MEM, 152 .end = baseaddr + SZ_4K - 1, \
256 }, { 153 .flags = IORESOURCE_MEM, \
257 .start = MXC_INT_NANDFC, 154 }, { \
258 .end = MXC_INT_NANDFC, 155 .start = irq, \
259 .flags = IORESOURCE_IRQ, 156 .end = irq, \
260 }, 157 .flags = IORESOURCE_IRQ, \
261}; 158 }, \
159 }; \
160 \
161 struct platform_device pfx ## _nand_device = { \
162 .name = "mxc_nand", \
163 .id = 0, \
164 .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
165 .resource = pfx ## _nand_resources, \
166 }
262 167
263struct platform_device mxc_nand_device = { 168#ifdef CONFIG_MACH_MX21
264 .name = "mxc_nand", 169DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
265 .id = 0, 170#endif
266 .num_resources = ARRAY_SIZE(mxc_nand_resources), 171
267 .resource = mxc_nand_resources, 172#ifdef CONFIG_MACH_MX27
268}; 173DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
174#endif
269 175
270/* 176/*
271 * lcdc: 177 * lcdc:
@@ -275,12 +181,12 @@ struct platform_device mxc_nand_device = {
275 */ 181 */
276static struct resource mxc_fb[] = { 182static struct resource mxc_fb[] = {
277 { 183 {
278 .start = LCDC_BASE_ADDR, 184 .start = MX2x_LCDC_BASE_ADDR,
279 .end = LCDC_BASE_ADDR + 0xFFF, 185 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
280 .flags = IORESOURCE_MEM, 186 .flags = IORESOURCE_MEM,
281 }, { 187 }, {
282 .start = MXC_INT_LCDC, 188 .start = MX2x_INT_LCDC,
283 .end = MXC_INT_LCDC, 189 .end = MX2x_INT_LCDC,
284 .flags = IORESOURCE_IRQ, 190 .flags = IORESOURCE_IRQ,
285 } 191 }
286}; 192};
@@ -292,20 +198,20 @@ struct platform_device mxc_fb_device = {
292 .num_resources = ARRAY_SIZE(mxc_fb), 198 .num_resources = ARRAY_SIZE(mxc_fb),
293 .resource = mxc_fb, 199 .resource = mxc_fb,
294 .dev = { 200 .dev = {
295 .coherent_dma_mask = 0xFFFFFFFF, 201 .coherent_dma_mask = DMA_BIT_MASK(32),
296 }, 202 },
297}; 203};
298 204
299#ifdef CONFIG_MACH_MX27 205#ifdef CONFIG_MACH_MX27
300static struct resource mxc_fec_resources[] = { 206static struct resource mxc_fec_resources[] = {
301 { 207 {
302 .start = FEC_BASE_ADDR, 208 .start = MX27_FEC_BASE_ADDR,
303 .end = FEC_BASE_ADDR + 0xfff, 209 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
304 .flags = IORESOURCE_MEM, 210 .flags = IORESOURCE_MEM,
305 }, { 211 }, {
306 .start = MXC_INT_FEC, 212 .start = MX27_INT_FEC,
307 .end = MXC_INT_FEC, 213 .end = MX27_INT_FEC,
308 .flags = IORESOURCE_IRQ, 214 .flags = IORESOURCE_IRQ,
309 }, 215 },
310}; 216};
311 217
@@ -317,55 +223,41 @@ struct platform_device mxc_fec_device = {
317}; 223};
318#endif 224#endif
319 225
320static struct resource mxc_i2c_1_resources[] = { 226#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
321 { 227 static struct resource mxc_i2c_resources ## n[] = { \
322 .start = I2C_BASE_ADDR, 228 { \
323 .end = I2C_BASE_ADDR + 0x0fff, 229 .start = baseaddr, \
324 .flags = IORESOURCE_MEM, 230 .end = baseaddr + SZ_4K - 1, \
325 }, { 231 .flags = IORESOURCE_MEM, \
326 .start = MXC_INT_I2C, 232 }, { \
327 .end = MXC_INT_I2C, 233 .start = irq, \
328 .flags = IORESOURCE_IRQ, 234 .end = irq, \
235 .flags = IORESOURCE_IRQ, \
236 } \
237 }; \
238 \
239 struct platform_device mxc_i2c_device ## n = { \
240 .name = "imx-i2c", \
241 .id = n, \
242 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
243 .resource = mxc_i2c_resources ## n, \
329 } 244 }
330};
331 245
332struct platform_device mxc_i2c_device0 = { 246DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
333 .name = "imx-i2c",
334 .id = 0,
335 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
336 .resource = mxc_i2c_1_resources,
337};
338 247
339#ifdef CONFIG_MACH_MX27 248#ifdef CONFIG_MACH_MX27
340static struct resource mxc_i2c_2_resources[] = { 249DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
341 {
342 .start = I2C2_BASE_ADDR,
343 .end = I2C2_BASE_ADDR + 0x0fff,
344 .flags = IORESOURCE_MEM,
345 }, {
346 .start = MXC_INT_I2C2,
347 .end = MXC_INT_I2C2,
348 .flags = IORESOURCE_IRQ,
349 }
350};
351
352struct platform_device mxc_i2c_device1 = {
353 .name = "imx-i2c",
354 .id = 1,
355 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
356 .resource = mxc_i2c_2_resources,
357};
358#endif 250#endif
359 251
360static struct resource mxc_pwm_resources[] = { 252static struct resource mxc_pwm_resources[] = {
361 { 253 {
362 .start = PWM_BASE_ADDR, 254 .start = MX2x_PWM_BASE_ADDR,
363 .end = PWM_BASE_ADDR + 0x0fff, 255 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
364 .flags = IORESOURCE_MEM, 256 .flags = IORESOURCE_MEM,
365 }, { 257 }, {
366 .start = MXC_INT_PWM, 258 .start = MX2x_INT_PWM,
367 .end = MXC_INT_PWM, 259 .end = MX2x_INT_PWM,
368 .flags = IORESOURCE_IRQ, 260 .flags = IORESOURCE_IRQ,
369 } 261 }
370}; 262};
371 263
@@ -376,81 +268,53 @@ struct platform_device mxc_pwm_device = {
376 .resource = mxc_pwm_resources, 268 .resource = mxc_pwm_resources,
377}; 269};
378 270
379/* 271#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
380 * Resource definition for the MXC SDHC 272 static struct resource mxc_sdhc_resources ## n[] = { \
381 */ 273 { \
382static struct resource mxc_sdhc1_resources[] = { 274 .start = baseaddr, \
383 { 275 .end = baseaddr + SZ_4K - 1, \
384 .start = SDHC1_BASE_ADDR, 276 .flags = IORESOURCE_MEM, \
385 .end = SDHC1_BASE_ADDR + SZ_4K - 1, 277 }, { \
386 .flags = IORESOURCE_MEM, 278 .start = irq, \
387 }, { 279 .end = irq, \
388 .start = MXC_INT_SDHC1, 280 .flags = IORESOURCE_IRQ, \
389 .end = MXC_INT_SDHC1, 281 }, { \
390 .flags = IORESOURCE_IRQ, 282 .start = dmareq, \
391 }, { 283 .end = dmareq, \
392 .start = DMA_REQ_SDHC1, 284 .flags = IORESOURCE_DMA, \
393 .end = DMA_REQ_SDHC1, 285 }, \
394 .flags = IORESOURCE_DMA, 286 }; \
395 }, 287 \
396}; 288 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
397 289 \
398static u64 mxc_sdhc1_dmamask = 0xffffffffUL; 290 struct platform_device mxc_sdhc_device ## n = { \
399 291 .name = "mxc-mmc", \
400struct platform_device mxc_sdhc_device0 = { 292 .id = n, \
401 .name = "mxc-mmc", 293 .dev = { \
402 .id = 0, 294 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
403 .dev = { 295 .coherent_dma_mask = DMA_BIT_MASK(32), \
404 .dma_mask = &mxc_sdhc1_dmamask, 296 }, \
405 .coherent_dma_mask = 0xffffffff, 297 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
406 }, 298 .resource = mxc_sdhc_resources ## n, \
407 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), 299 }
408 .resource = mxc_sdhc1_resources,
409};
410
411static struct resource mxc_sdhc2_resources[] = {
412 {
413 .start = SDHC2_BASE_ADDR,
414 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
415 .flags = IORESOURCE_MEM,
416 }, {
417 .start = MXC_INT_SDHC2,
418 .end = MXC_INT_SDHC2,
419 .flags = IORESOURCE_IRQ,
420 }, {
421 .start = DMA_REQ_SDHC2,
422 .end = DMA_REQ_SDHC2,
423 .flags = IORESOURCE_DMA,
424 },
425};
426 300
427static u64 mxc_sdhc2_dmamask = 0xffffffffUL; 301DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
428 302DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
429struct platform_device mxc_sdhc_device1 = {
430 .name = "mxc-mmc",
431 .id = 1,
432 .dev = {
433 .dma_mask = &mxc_sdhc2_dmamask,
434 .coherent_dma_mask = 0xffffffff,
435 },
436 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
437 .resource = mxc_sdhc2_resources,
438};
439 303
440#ifdef CONFIG_MACH_MX27 304#ifdef CONFIG_MACH_MX27
441static struct resource otg_resources[] = { 305static struct resource otg_resources[] = {
442 { 306 {
443 .start = OTG_BASE_ADDR, 307 .start = MX27_USBOTG_BASE_ADDR,
444 .end = OTG_BASE_ADDR + 0x1ff, 308 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
445 .flags = IORESOURCE_MEM, 309 .flags = IORESOURCE_MEM,
446 }, { 310 }, {
447 .start = MXC_INT_USB3, 311 .start = MX27_INT_USB3,
448 .end = MXC_INT_USB3, 312 .end = MX27_INT_USB3,
449 .flags = IORESOURCE_IRQ, 313 .flags = IORESOURCE_IRQ,
450 }, 314 },
451}; 315};
452 316
453static u64 otg_dmamask = 0xffffffffUL; 317static u64 otg_dmamask = DMA_BIT_MASK(32);
454 318
455/* OTG gadget device */ 319/* OTG gadget device */
456struct platform_device mxc_otg_udc_device = { 320struct platform_device mxc_otg_udc_device = {
@@ -458,7 +322,7 @@ struct platform_device mxc_otg_udc_device = {
458 .id = -1, 322 .id = -1,
459 .dev = { 323 .dev = {
460 .dma_mask = &otg_dmamask, 324 .dma_mask = &otg_dmamask,
461 .coherent_dma_mask = 0xffffffffUL, 325 .coherent_dma_mask = DMA_BIT_MASK(32),
462 }, 326 },
463 .resource = otg_resources, 327 .resource = otg_resources,
464 .num_resources = ARRAY_SIZE(otg_resources), 328 .num_resources = ARRAY_SIZE(otg_resources),
@@ -469,7 +333,7 @@ struct platform_device mxc_otg_host = {
469 .name = "mxc-ehci", 333 .name = "mxc-ehci",
470 .id = 0, 334 .id = 0,
471 .dev = { 335 .dev = {
472 .coherent_dma_mask = 0xffffffff, 336 .coherent_dma_mask = DMA_BIT_MASK(32),
473 .dma_mask = &otg_dmamask, 337 .dma_mask = &otg_dmamask,
474 }, 338 },
475 .resource = otg_resources, 339 .resource = otg_resources,
@@ -478,16 +342,16 @@ struct platform_device mxc_otg_host = {
478 342
479/* USB host 1 */ 343/* USB host 1 */
480 344
481static u64 usbh1_dmamask = 0xffffffffUL; 345static u64 usbh1_dmamask = DMA_BIT_MASK(32);
482 346
483static struct resource mxc_usbh1_resources[] = { 347static struct resource mxc_usbh1_resources[] = {
484 { 348 {
485 .start = OTG_BASE_ADDR + 0x200, 349 .start = MX27_USBOTG_BASE_ADDR + 0x200,
486 .end = OTG_BASE_ADDR + 0x3ff, 350 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
487 .flags = IORESOURCE_MEM, 351 .flags = IORESOURCE_MEM,
488 }, { 352 }, {
489 .start = MXC_INT_USB1, 353 .start = MX27_INT_USB1,
490 .end = MXC_INT_USB1, 354 .end = MX27_INT_USB1,
491 .flags = IORESOURCE_IRQ, 355 .flags = IORESOURCE_IRQ,
492 }, 356 },
493}; 357};
@@ -496,7 +360,7 @@ struct platform_device mxc_usbh1 = {
496 .name = "mxc-ehci", 360 .name = "mxc-ehci",
497 .id = 1, 361 .id = 1,
498 .dev = { 362 .dev = {
499 .coherent_dma_mask = 0xffffffff, 363 .coherent_dma_mask = DMA_BIT_MASK(32),
500 .dma_mask = &usbh1_dmamask, 364 .dma_mask = &usbh1_dmamask,
501 }, 365 },
502 .resource = mxc_usbh1_resources, 366 .resource = mxc_usbh1_resources,
@@ -504,16 +368,16 @@ struct platform_device mxc_usbh1 = {
504}; 368};
505 369
506/* USB host 2 */ 370/* USB host 2 */
507static u64 usbh2_dmamask = 0xffffffffUL; 371static u64 usbh2_dmamask = DMA_BIT_MASK(32);
508 372
509static struct resource mxc_usbh2_resources[] = { 373static struct resource mxc_usbh2_resources[] = {
510 { 374 {
511 .start = OTG_BASE_ADDR + 0x400, 375 .start = MX27_USBOTG_BASE_ADDR + 0x400,
512 .end = OTG_BASE_ADDR + 0x5ff, 376 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
513 .flags = IORESOURCE_MEM, 377 .flags = IORESOURCE_MEM,
514 }, { 378 }, {
515 .start = MXC_INT_USB2, 379 .start = MX27_INT_USB2,
516 .end = MXC_INT_USB2, 380 .end = MX27_INT_USB2,
517 .flags = IORESOURCE_IRQ, 381 .flags = IORESOURCE_IRQ,
518 }, 382 },
519}; 383};
@@ -522,7 +386,7 @@ struct platform_device mxc_usbh2 = {
522 .name = "mxc-ehci", 386 .name = "mxc-ehci",
523 .id = 2, 387 .id = 2,
524 .dev = { 388 .dev = {
525 .coherent_dma_mask = 0xffffffff, 389 .coherent_dma_mask = DMA_BIT_MASK(32),
526 .dma_mask = &usbh2_dmamask, 390 .dma_mask = &usbh2_dmamask,
527 }, 391 },
528 .resource = mxc_usbh2_resources, 392 .resource = mxc_usbh2_resources,
@@ -530,37 +394,115 @@ struct platform_device mxc_usbh2 = {
530}; 394};
531#endif 395#endif
532 396
397#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
398 { \
399 .name = _name, \
400 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
401 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
402 .flags = IORESOURCE_DMA, \
403 }
404
405#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
406 static struct resource imx_ssi_resources ## n[] = { \
407 { \
408 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
409 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
410 .flags = IORESOURCE_MEM, \
411 }, { \
412 .start = MX2x_INT_SSI1, \
413 .end = MX2x_INT_SSI1, \
414 .flags = IORESOURCE_IRQ, \
415 }, \
416 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
417 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
418 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
419 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
420 }; \
421 \
422 struct platform_device imx_ssi_device ## n = { \
423 .name = "imx-ssi", \
424 .id = n, \
425 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
426 .resource = imx_ssi_resources ## n, \
427 }
428
429DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
430DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
431
533/* GPIO port description */ 432/* GPIO port description */
534static struct mxc_gpio_port imx_gpio_ports[] = { 433#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
535 { 434 { \
536 .chip.label = "gpio-0", 435 .chip.label = "gpio-" #n, \
537 .irq = MXC_INT_GPIO, 436 .irq = _irq, \
538 .base = IO_ADDRESS(GPIO_BASE_ADDR), 437 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
539 .virtual_irq_start = MXC_GPIO_IRQ_START, 438 n * 0x100), \
540 }, { 439 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
541 .chip.label = "gpio-1",
542 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
543 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
544 }, {
545 .chip.label = "gpio-2",
546 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
547 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
548 }, {
549 .chip.label = "gpio-3",
550 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
551 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
552 }, {
553 .chip.label = "gpio-4",
554 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
555 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
556 }, {
557 .chip.label = "gpio-5",
558 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
559 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
560 } 440 }
561}; 441
442#define DEFINE_MXC_GPIO_PORT(SOC, n) \
443 { \
444 .chip.label = "gpio-" #n, \
445 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
446 n * 0x100), \
447 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
448 }
449
450#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
451 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
452 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
453 DEFINE_MXC_GPIO_PORT(SOC, 1), \
454 DEFINE_MXC_GPIO_PORT(SOC, 2), \
455 DEFINE_MXC_GPIO_PORT(SOC, 3), \
456 DEFINE_MXC_GPIO_PORT(SOC, 4), \
457 DEFINE_MXC_GPIO_PORT(SOC, 5), \
458 }
459
460#ifdef CONFIG_MACH_MX21
461DEFINE_MXC_GPIO_PORTS(MX21, imx21);
462#endif
463
464#ifdef CONFIG_MACH_MX27
465DEFINE_MXC_GPIO_PORTS(MX27, imx27);
466#endif
562 467
563int __init mxc_register_gpios(void) 468int __init mxc_register_gpios(void)
564{ 469{
565 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 470#ifdef CONFIG_MACH_MX21
471 if (cpu_is_mx21())
472 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
473 else
474#endif
475#ifdef CONFIG_MACH_MX27
476 if (cpu_is_mx27())
477 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
478 else
479#endif
480 return 0;
566} 481}
482
483#ifdef CONFIG_MACH_MX21
484static struct resource mx21_usbhc_resources[] = {
485 {
486 .start = MX21_BASE_ADDR,
487 .end = MX21_BASE_ADDR + 0x1FFF,
488 .flags = IORESOURCE_MEM,
489 },
490 {
491 .start = MX21_INT_USBHOST,
492 .end = MX21_INT_USBHOST,
493 .flags = IORESOURCE_IRQ,
494 },
495};
496
497struct platform_device mx21_usbhc_device = {
498 .name = "imx21-hcd",
499 .id = 0,
500 .dev = {
501 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
502 .coherent_dma_mask = DMA_BIT_MASK(32),
503 },
504 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
505 .resource = mx21_usbhc_resources,
506};
507#endif
508
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 09:24:53 -0400