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-rw-r--r--arch/arm/mach-mv78xx0/Kconfig13
-rw-r--r--arch/arm/mach-mv78xx0/Makefile2
-rw-r--r--arch/arm/mach-mv78xx0/Makefile.boot3
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c156
-rw-r--r--arch/arm/mach-mv78xx0/common.c754
-rw-r--r--arch/arm/mach-mv78xx0/common.h49
-rw-r--r--arch/arm/mach-mv78xx0/db78x00-bp-setup.c94
-rw-r--r--arch/arm/mach-mv78xx0/irq.c22
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c312
9 files changed, 1405 insertions, 0 deletions
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
new file mode 100644
index 000000000000..d83cb86837db
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -0,0 +1,13 @@
1if ARCH_MV78XX0
2
3menu "Marvell MV78xx0 Implementations"
4
5config MACH_DB78X00_BP
6 bool "Marvell DB-78x00-BP Development Board"
7 help
8 Say 'Y' here if you want your kernel to support the
9 Marvell DB-78x00-BP Development Board.
10
11endmenu
12
13endif
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
new file mode 100644
index 000000000000..ec16c05c3b1b
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -0,0 +1,2 @@
1obj-y += common.o addr-map.o irq.o pcie.o
2obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o
diff --git a/arch/arm/mach-mv78xx0/Makefile.boot b/arch/arm/mach-mv78xx0/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
new file mode 100644
index 000000000000..4004b672a2eb
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -0,0 +1,156 @@
1/*
2 * arch/arm/mach-mv78xx0/addr-map.c
3 *
4 * Address map functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <asm/io.h>
15#include "common.h"
16
17/*
18 * Generic Address Decode Windows bit settings
19 */
20#define TARGET_DDR 0
21#define TARGET_DEV_BUS 1
22#define TARGET_PCIE0 4
23#define TARGET_PCIE1 8
24#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
25#define ATTR_DEV_SPI_ROM 0x1f
26#define ATTR_DEV_BOOT 0x2f
27#define ATTR_DEV_CS3 0x37
28#define ATTR_DEV_CS2 0x3b
29#define ATTR_DEV_CS1 0x3d
30#define ATTR_DEV_CS0 0x3e
31#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l)))
32#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
33
34/*
35 * Helpers to get DDR bank info
36 */
37#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
38#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
39
40/*
41 * CPU Address Decode Windows registers
42 */
43#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
44#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
45#define WIN_CTRL_OFF 0x0000
46#define WIN_BASE_OFF 0x0004
47#define WIN_REMAP_LO_OFF 0x0008
48#define WIN_REMAP_HI_OFF 0x000c
49
50
51struct mbus_dram_target_info mv78xx0_mbus_dram_info;
52
53static void __init __iomem *win_cfg_base(int win)
54{
55 /*
56 * Find the control register base address for this window.
57 *
58 * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
59 * MBUS bridge depending on which CPU core we're running on,
60 * so we don't need to take that into account here.
61 */
62
63 return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
64}
65
66static int __init cpu_win_can_remap(int win)
67{
68 if (win < 8)
69 return 1;
70
71 return 0;
72}
73
74static void __init setup_cpu_win(int win, u32 base, u32 size,
75 u8 target, u8 attr, int remap)
76{
77 void __iomem *addr = win_cfg_base(win);
78 u32 ctrl;
79
80 base &= 0xffff0000;
81 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
82
83 writel(base, addr + WIN_BASE_OFF);
84 writel(ctrl, addr + WIN_CTRL_OFF);
85 if (cpu_win_can_remap(win)) {
86 if (remap < 0)
87 remap = base;
88
89 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
90 writel(0, addr + WIN_REMAP_HI_OFF);
91 }
92}
93
94void __init mv78xx0_setup_cpu_mbus(void)
95{
96 void __iomem *addr;
97 int i;
98 int cs;
99
100 /*
101 * First, disable and clear windows.
102 */
103 for (i = 0; i < 14; i++) {
104 addr = win_cfg_base(i);
105
106 writel(0, addr + WIN_BASE_OFF);
107 writel(0, addr + WIN_CTRL_OFF);
108 if (cpu_win_can_remap(i)) {
109 writel(0, addr + WIN_REMAP_LO_OFF);
110 writel(0, addr + WIN_REMAP_HI_OFF);
111 }
112 }
113
114 /*
115 * Setup MBUS dram target info.
116 */
117 mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
118
119 if (mv78xx0_core_index() == 0)
120 addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
121 else
122 addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
123
124 for (i = 0, cs = 0; i < 4; i++) {
125 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
126 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
127
128 /*
129 * Chip select enabled?
130 */
131 if (size & 1) {
132 struct mbus_dram_window *w;
133
134 w = &mv78xx0_mbus_dram_info.cs[cs++];
135 w->cs_index = i;
136 w->mbus_attr = 0xf & ~(1 << i);
137 w->base = base & 0xffff0000;
138 w->size = (size | 0x0000ffff) + 1;
139 }
140 }
141 mv78xx0_mbus_dram_info.num_cs = cs;
142}
143
144void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
145 int maj, int min)
146{
147 setup_cpu_win(window, base, size, TARGET_PCIE(maj),
148 ATTR_PCIE_IO(min), -1);
149}
150
151void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
152 int maj, int min)
153{
154 setup_cpu_win(window, base, size, TARGET_PCIE(maj),
155 ATTR_PCIE_MEM(min), -1);
156}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
new file mode 100644
index 000000000000..d27b83b7bf62
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -0,0 +1,754 @@
1/*
2 * arch/arm/mach-mv78xx0/common.c
3 *
4 * Core functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/ata_platform.h>
18#include <asm/mach/map.h>
19#include <asm/mach/time.h>
20#include <asm/arch/mv78xx0.h>
21#include <asm/plat-orion/cache-feroceon-l2.h>
22#include <asm/plat-orion/ehci-orion.h>
23#include <asm/plat-orion/orion_nand.h>
24#include <asm/plat-orion/time.h>
25#include "common.h"
26
27
28/*****************************************************************************
29 * Common bits
30 ****************************************************************************/
31int mv78xx0_core_index(void)
32{
33 u32 extra;
34
35 /*
36 * Read Extra Features register.
37 */
38 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
39
40 return !!(extra & 0x00004000);
41}
42
43static int get_hclk(void)
44{
45 int hclk;
46
47 /*
48 * HCLK tick rate is configured by DEV_D[7:5] pins.
49 */
50 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
51 case 0:
52 hclk = 166666667;
53 break;
54 case 1:
55 hclk = 200000000;
56 break;
57 case 2:
58 hclk = 266666667;
59 break;
60 case 3:
61 hclk = 333333333;
62 break;
63 case 4:
64 hclk = 400000000;
65 break;
66 default:
67 panic("unknown HCLK PLL setting: %.8x\n",
68 readl(SAMPLE_AT_RESET_LOW));
69 }
70
71 return hclk;
72}
73
74static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
75{
76 u32 cfg;
77
78 /*
79 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
80 * PCLK/L2CLK by bits [19:14].
81 */
82 if (core_index == 0) {
83 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
84 } else {
85 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
86 }
87
88 /*
89 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
90 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
91 */
92 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
93
94 /*
95 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
96 * ratio (1, 2, 3).
97 */
98 *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
99}
100
101static int get_tclk(void)
102{
103 int tclk;
104
105 /*
106 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
107 */
108 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
109 case 1:
110 tclk = 166666667;
111 break;
112 case 3:
113 tclk = 200000000;
114 break;
115 default:
116 panic("unknown TCLK PLL setting: %.8x\n",
117 readl(SAMPLE_AT_RESET_HIGH));
118 }
119
120 return tclk;
121}
122
123
124/*****************************************************************************
125 * I/O Address Mapping
126 ****************************************************************************/
127static struct map_desc mv78xx0_io_desc[] __initdata = {
128 {
129 .virtual = MV78XX0_CORE_REGS_VIRT_BASE,
130 .pfn = 0,
131 .length = MV78XX0_CORE_REGS_SIZE,
132 .type = MT_DEVICE,
133 }, {
134 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
135 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
136 .length = MV78XX0_PCIE_IO_SIZE * 8,
137 .type = MT_DEVICE,
138 }, {
139 .virtual = MV78XX0_REGS_VIRT_BASE,
140 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
141 .length = MV78XX0_REGS_SIZE,
142 .type = MT_DEVICE,
143 },
144};
145
146void __init mv78xx0_map_io(void)
147{
148 unsigned long phys;
149
150 /*
151 * Map the right set of per-core registers depending on
152 * which core we are running on.
153 */
154 if (mv78xx0_core_index() == 0) {
155 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
156 } else {
157 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
158 }
159 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
160
161 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
162}
163
164
165/*****************************************************************************
166 * EHCI
167 ****************************************************************************/
168static struct orion_ehci_data mv78xx0_ehci_data = {
169 .dram = &mv78xx0_mbus_dram_info,
170};
171
172static u64 ehci_dmamask = 0xffffffffUL;
173
174
175/*****************************************************************************
176 * EHCI0
177 ****************************************************************************/
178static struct resource mv78xx0_ehci0_resources[] = {
179 {
180 .start = USB0_PHYS_BASE,
181 .end = USB0_PHYS_BASE + 0x0fff,
182 .flags = IORESOURCE_MEM,
183 }, {
184 .start = IRQ_MV78XX0_USB_0,
185 .end = IRQ_MV78XX0_USB_0,
186 .flags = IORESOURCE_IRQ,
187 },
188};
189
190static struct platform_device mv78xx0_ehci0 = {
191 .name = "orion-ehci",
192 .id = 0,
193 .dev = {
194 .dma_mask = &ehci_dmamask,
195 .coherent_dma_mask = 0xffffffff,
196 .platform_data = &mv78xx0_ehci_data,
197 },
198 .resource = mv78xx0_ehci0_resources,
199 .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
200};
201
202void __init mv78xx0_ehci0_init(void)
203{
204 platform_device_register(&mv78xx0_ehci0);
205}
206
207
208/*****************************************************************************
209 * EHCI1
210 ****************************************************************************/
211static struct resource mv78xx0_ehci1_resources[] = {
212 {
213 .start = USB1_PHYS_BASE,
214 .end = USB1_PHYS_BASE + 0x0fff,
215 .flags = IORESOURCE_MEM,
216 }, {
217 .start = IRQ_MV78XX0_USB_1,
218 .end = IRQ_MV78XX0_USB_1,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223static struct platform_device mv78xx0_ehci1 = {
224 .name = "orion-ehci",
225 .id = 1,
226 .dev = {
227 .dma_mask = &ehci_dmamask,
228 .coherent_dma_mask = 0xffffffff,
229 .platform_data = &mv78xx0_ehci_data,
230 },
231 .resource = mv78xx0_ehci1_resources,
232 .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
233};
234
235void __init mv78xx0_ehci1_init(void)
236{
237 platform_device_register(&mv78xx0_ehci1);
238}
239
240
241/*****************************************************************************
242 * EHCI2
243 ****************************************************************************/
244static struct resource mv78xx0_ehci2_resources[] = {
245 {
246 .start = USB2_PHYS_BASE,
247 .end = USB2_PHYS_BASE + 0x0fff,
248 .flags = IORESOURCE_MEM,
249 }, {
250 .start = IRQ_MV78XX0_USB_2,
251 .end = IRQ_MV78XX0_USB_2,
252 .flags = IORESOURCE_IRQ,
253 },
254};
255
256static struct platform_device mv78xx0_ehci2 = {
257 .name = "orion-ehci",
258 .id = 2,
259 .dev = {
260 .dma_mask = &ehci_dmamask,
261 .coherent_dma_mask = 0xffffffff,
262 .platform_data = &mv78xx0_ehci_data,
263 },
264 .resource = mv78xx0_ehci2_resources,
265 .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
266};
267
268void __init mv78xx0_ehci2_init(void)
269{
270 platform_device_register(&mv78xx0_ehci2);
271}
272
273
274/*****************************************************************************
275 * GE00
276 ****************************************************************************/
277struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
278 .t_clk = 0,
279 .dram = &mv78xx0_mbus_dram_info,
280};
281
282static struct resource mv78xx0_ge00_shared_resources[] = {
283 {
284 .name = "ge00 base",
285 .start = GE00_PHYS_BASE + 0x2000,
286 .end = GE00_PHYS_BASE + 0x3fff,
287 .flags = IORESOURCE_MEM,
288 },
289};
290
291static struct platform_device mv78xx0_ge00_shared = {
292 .name = MV643XX_ETH_SHARED_NAME,
293 .id = 0,
294 .dev = {
295 .platform_data = &mv78xx0_ge00_shared_data,
296 },
297 .num_resources = 1,
298 .resource = mv78xx0_ge00_shared_resources,
299};
300
301static struct resource mv78xx0_ge00_resources[] = {
302 {
303 .name = "ge00 irq",
304 .start = IRQ_MV78XX0_GE00_SUM,
305 .end = IRQ_MV78XX0_GE00_SUM,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
310static struct platform_device mv78xx0_ge00 = {
311 .name = MV643XX_ETH_NAME,
312 .id = 0,
313 .num_resources = 1,
314 .resource = mv78xx0_ge00_resources,
315};
316
317void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
318{
319 eth_data->shared = &mv78xx0_ge00_shared;
320 mv78xx0_ge00.dev.platform_data = eth_data;
321
322 platform_device_register(&mv78xx0_ge00_shared);
323 platform_device_register(&mv78xx0_ge00);
324}
325
326
327/*****************************************************************************
328 * GE01
329 ****************************************************************************/
330struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
331 .t_clk = 0,
332 .dram = &mv78xx0_mbus_dram_info,
333};
334
335static struct resource mv78xx0_ge01_shared_resources[] = {
336 {
337 .name = "ge01 base",
338 .start = GE01_PHYS_BASE + 0x2000,
339 .end = GE01_PHYS_BASE + 0x3fff,
340 .flags = IORESOURCE_MEM,
341 },
342};
343
344static struct platform_device mv78xx0_ge01_shared = {
345 .name = MV643XX_ETH_SHARED_NAME,
346 .id = 1,
347 .dev = {
348 .platform_data = &mv78xx0_ge01_shared_data,
349 },
350 .num_resources = 1,
351 .resource = mv78xx0_ge01_shared_resources,
352};
353
354static struct resource mv78xx0_ge01_resources[] = {
355 {
356 .name = "ge01 irq",
357 .start = IRQ_MV78XX0_GE01_SUM,
358 .end = IRQ_MV78XX0_GE01_SUM,
359 .flags = IORESOURCE_IRQ,
360 },
361};
362
363static struct platform_device mv78xx0_ge01 = {
364 .name = MV643XX_ETH_NAME,
365 .id = 1,
366 .num_resources = 1,
367 .resource = mv78xx0_ge01_resources,
368};
369
370void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
371{
372 eth_data->shared = &mv78xx0_ge01_shared;
373 eth_data->shared_smi = &mv78xx0_ge00_shared;
374 mv78xx0_ge01.dev.platform_data = eth_data;
375
376 platform_device_register(&mv78xx0_ge01_shared);
377 platform_device_register(&mv78xx0_ge01);
378}
379
380
381/*****************************************************************************
382 * GE10
383 ****************************************************************************/
384struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
385 .t_clk = 0,
386 .dram = &mv78xx0_mbus_dram_info,
387};
388
389static struct resource mv78xx0_ge10_shared_resources[] = {
390 {
391 .name = "ge10 base",
392 .start = GE10_PHYS_BASE + 0x2000,
393 .end = GE10_PHYS_BASE + 0x3fff,
394 .flags = IORESOURCE_MEM,
395 },
396};
397
398static struct platform_device mv78xx0_ge10_shared = {
399 .name = MV643XX_ETH_SHARED_NAME,
400 .id = 2,
401 .dev = {
402 .platform_data = &mv78xx0_ge10_shared_data,
403 },
404 .num_resources = 1,
405 .resource = mv78xx0_ge10_shared_resources,
406};
407
408static struct resource mv78xx0_ge10_resources[] = {
409 {
410 .name = "ge10 irq",
411 .start = IRQ_MV78XX0_GE10_SUM,
412 .end = IRQ_MV78XX0_GE10_SUM,
413 .flags = IORESOURCE_IRQ,
414 },
415};
416
417static struct platform_device mv78xx0_ge10 = {
418 .name = MV643XX_ETH_NAME,
419 .id = 2,
420 .num_resources = 1,
421 .resource = mv78xx0_ge10_resources,
422};
423
424void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
425{
426 eth_data->shared = &mv78xx0_ge10_shared;
427 eth_data->shared_smi = &mv78xx0_ge00_shared;
428 mv78xx0_ge10.dev.platform_data = eth_data;
429
430 platform_device_register(&mv78xx0_ge10_shared);
431 platform_device_register(&mv78xx0_ge10);
432}
433
434
435/*****************************************************************************
436 * GE11
437 ****************************************************************************/
438struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
439 .t_clk = 0,
440 .dram = &mv78xx0_mbus_dram_info,
441};
442
443static struct resource mv78xx0_ge11_shared_resources[] = {
444 {
445 .name = "ge11 base",
446 .start = GE11_PHYS_BASE + 0x2000,
447 .end = GE11_PHYS_BASE + 0x3fff,
448 .flags = IORESOURCE_MEM,
449 },
450};
451
452static struct platform_device mv78xx0_ge11_shared = {
453 .name = MV643XX_ETH_SHARED_NAME,
454 .id = 3,
455 .dev = {
456 .platform_data = &mv78xx0_ge11_shared_data,
457 },
458 .num_resources = 1,
459 .resource = mv78xx0_ge11_shared_resources,
460};
461
462static struct resource mv78xx0_ge11_resources[] = {
463 {
464 .name = "ge11 irq",
465 .start = IRQ_MV78XX0_GE11_SUM,
466 .end = IRQ_MV78XX0_GE11_SUM,
467 .flags = IORESOURCE_IRQ,
468 },
469};
470
471static struct platform_device mv78xx0_ge11 = {
472 .name = MV643XX_ETH_NAME,
473 .id = 3,
474 .num_resources = 1,
475 .resource = mv78xx0_ge11_resources,
476};
477
478void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
479{
480 eth_data->shared = &mv78xx0_ge11_shared;
481 eth_data->shared_smi = &mv78xx0_ge00_shared;
482 mv78xx0_ge11.dev.platform_data = eth_data;
483
484 platform_device_register(&mv78xx0_ge11_shared);
485 platform_device_register(&mv78xx0_ge11);
486}
487
488
489/*****************************************************************************
490 * SATA
491 ****************************************************************************/
492static struct resource mv78xx0_sata_resources[] = {
493 {
494 .name = "sata base",
495 .start = SATA_PHYS_BASE,
496 .end = SATA_PHYS_BASE + 0x5000 - 1,
497 .flags = IORESOURCE_MEM,
498 }, {
499 .name = "sata irq",
500 .start = IRQ_MV78XX0_SATA,
501 .end = IRQ_MV78XX0_SATA,
502 .flags = IORESOURCE_IRQ,
503 },
504};
505
506static struct platform_device mv78xx0_sata = {
507 .name = "sata_mv",
508 .id = 0,
509 .dev = {
510 .coherent_dma_mask = 0xffffffff,
511 },
512 .num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
513 .resource = mv78xx0_sata_resources,
514};
515
516void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
517{
518 sata_data->dram = &mv78xx0_mbus_dram_info;
519 mv78xx0_sata.dev.platform_data = sata_data;
520 platform_device_register(&mv78xx0_sata);
521}
522
523
524/*****************************************************************************
525 * UART0
526 ****************************************************************************/
527static struct plat_serial8250_port mv78xx0_uart0_data[] = {
528 {
529 .mapbase = UART0_PHYS_BASE,
530 .membase = (char *)UART0_VIRT_BASE,
531 .irq = IRQ_MV78XX0_UART_0,
532 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
533 .iotype = UPIO_MEM,
534 .regshift = 2,
535 .uartclk = 0,
536 }, {
537 },
538};
539
540static struct resource mv78xx0_uart0_resources[] = {
541 {
542 .start = UART0_PHYS_BASE,
543 .end = UART0_PHYS_BASE + 0xff,
544 .flags = IORESOURCE_MEM,
545 }, {
546 .start = IRQ_MV78XX0_UART_0,
547 .end = IRQ_MV78XX0_UART_0,
548 .flags = IORESOURCE_IRQ,
549 },
550};
551
552static struct platform_device mv78xx0_uart0 = {
553 .name = "serial8250",
554 .id = 0,
555 .dev = {
556 .platform_data = mv78xx0_uart0_data,
557 },
558 .resource = mv78xx0_uart0_resources,
559 .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
560};
561
562void __init mv78xx0_uart0_init(void)
563{
564 platform_device_register(&mv78xx0_uart0);
565}
566
567
568/*****************************************************************************
569 * UART1
570 ****************************************************************************/
571static struct plat_serial8250_port mv78xx0_uart1_data[] = {
572 {
573 .mapbase = UART1_PHYS_BASE,
574 .membase = (char *)UART1_VIRT_BASE,
575 .irq = IRQ_MV78XX0_UART_1,
576 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
577 .iotype = UPIO_MEM,
578 .regshift = 2,
579 .uartclk = 0,
580 }, {
581 },
582};
583
584static struct resource mv78xx0_uart1_resources[] = {
585 {
586 .start = UART1_PHYS_BASE,
587 .end = UART1_PHYS_BASE + 0xff,
588 .flags = IORESOURCE_MEM,
589 }, {
590 .start = IRQ_MV78XX0_UART_1,
591 .end = IRQ_MV78XX0_UART_1,
592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device mv78xx0_uart1 = {
597 .name = "serial8250",
598 .id = 1,
599 .dev = {
600 .platform_data = mv78xx0_uart1_data,
601 },
602 .resource = mv78xx0_uart1_resources,
603 .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
604};
605
606void __init mv78xx0_uart1_init(void)
607{
608 platform_device_register(&mv78xx0_uart1);
609}
610
611
612/*****************************************************************************
613 * UART2
614 ****************************************************************************/
615static struct plat_serial8250_port mv78xx0_uart2_data[] = {
616 {
617 .mapbase = UART2_PHYS_BASE,
618 .membase = (char *)UART2_VIRT_BASE,
619 .irq = IRQ_MV78XX0_UART_2,
620 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
621 .iotype = UPIO_MEM,
622 .regshift = 2,
623 .uartclk = 0,
624 }, {
625 },
626};
627
628static struct resource mv78xx0_uart2_resources[] = {
629 {
630 .start = UART2_PHYS_BASE,
631 .end = UART2_PHYS_BASE + 0xff,
632 .flags = IORESOURCE_MEM,
633 }, {
634 .start = IRQ_MV78XX0_UART_2,
635 .end = IRQ_MV78XX0_UART_2,
636 .flags = IORESOURCE_IRQ,
637 },
638};
639
640static struct platform_device mv78xx0_uart2 = {
641 .name = "serial8250",
642 .id = 2,
643 .dev = {
644 .platform_data = mv78xx0_uart2_data,
645 },
646 .resource = mv78xx0_uart2_resources,
647 .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
648};
649
650void __init mv78xx0_uart2_init(void)
651{
652 platform_device_register(&mv78xx0_uart2);
653}
654
655
656/*****************************************************************************
657 * UART3
658 ****************************************************************************/
659static struct plat_serial8250_port mv78xx0_uart3_data[] = {
660 {
661 .mapbase = UART3_PHYS_BASE,
662 .membase = (char *)UART3_VIRT_BASE,
663 .irq = IRQ_MV78XX0_UART_3,
664 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
665 .iotype = UPIO_MEM,
666 .regshift = 2,
667 .uartclk = 0,
668 }, {
669 },
670};
671
672static struct resource mv78xx0_uart3_resources[] = {
673 {
674 .start = UART3_PHYS_BASE,
675 .end = UART3_PHYS_BASE + 0xff,
676 .flags = IORESOURCE_MEM,
677 }, {
678 .start = IRQ_MV78XX0_UART_3,
679 .end = IRQ_MV78XX0_UART_3,
680 .flags = IORESOURCE_IRQ,
681 },
682};
683
684static struct platform_device mv78xx0_uart3 = {
685 .name = "serial8250",
686 .id = 3,
687 .dev = {
688 .platform_data = mv78xx0_uart3_data,
689 },
690 .resource = mv78xx0_uart3_resources,
691 .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
692};
693
694void __init mv78xx0_uart3_init(void)
695{
696 platform_device_register(&mv78xx0_uart3);
697}
698
699
700/*****************************************************************************
701 * Time handling
702 ****************************************************************************/
703static void mv78xx0_timer_init(void)
704{
705 orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
706}
707
708struct sys_timer mv78xx0_timer = {
709 .init = mv78xx0_timer_init,
710};
711
712
713/*****************************************************************************
714 * General
715 ****************************************************************************/
716static int __init is_l2_writethrough(void)
717{
718 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
719}
720
721void __init mv78xx0_init(void)
722{
723 int core_index;
724 int hclk;
725 int pclk;
726 int l2clk;
727 int tclk;
728
729 core_index = mv78xx0_core_index();
730 hclk = get_hclk();
731 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
732 tclk = get_tclk();
733
734 printk(KERN_INFO "MV78xx0 core #%d, ", core_index);
735 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
736 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
737 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
738 printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
739
740 mv78xx0_setup_cpu_mbus();
741
742#ifdef CONFIG_CACHE_FEROCEON_L2
743 feroceon_l2_init(is_l2_writethrough());
744#endif
745
746 mv78xx0_ge00_shared_data.t_clk = tclk;
747 mv78xx0_ge01_shared_data.t_clk = tclk;
748 mv78xx0_ge10_shared_data.t_clk = tclk;
749 mv78xx0_ge11_shared_data.t_clk = tclk;
750 mv78xx0_uart0_data[0].uartclk = tclk;
751 mv78xx0_uart1_data[0].uartclk = tclk;
752 mv78xx0_uart2_data[0].uartclk = tclk;
753 mv78xx0_uart3_data[0].uartclk = tclk;
754}
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
new file mode 100644
index 000000000000..78af5de319dd
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/mach-mv78xx0/common.h
3 *
4 * Core functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ARCH_MV78XX0_COMMON_H
12#define __ARCH_MV78XX0_COMMON_H
13
14struct mv643xx_eth_platform_data;
15struct mv_sata_platform_data;
16
17/*
18 * Basic MV78xx0 init functions used early by machine-setup.
19 */
20int mv78xx0_core_index(void);
21void mv78xx0_map_io(void);
22void mv78xx0_init(void);
23void mv78xx0_init_irq(void);
24
25extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
26void mv78xx0_setup_cpu_mbus(void);
27void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
28 int maj, int min);
29void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
30 int maj, int min);
31
32void mv78xx0_ehci0_init(void);
33void mv78xx0_ehci1_init(void);
34void mv78xx0_ehci2_init(void);
35void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data);
36void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data);
37void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data);
38void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data);
39void mv78xx0_pcie_init(int init_port0, int init_port1);
40void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data);
41void mv78xx0_uart0_init(void);
42void mv78xx0_uart1_init(void);
43void mv78xx0_uart2_init(void);
44void mv78xx0_uart3_init(void);
45
46extern struct sys_timer mv78xx0_timer;
47
48
49#endif
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
new file mode 100644
index 000000000000..0c93d19193df
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -0,0 +1,94 @@
1/*
2 * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
3 *
4 * Marvell DB-78x00-BP Development Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/ata_platform.h>
15#include <linux/mv643xx_eth.h>
16#include <asm/arch/mv78xx0.h>
17#include <asm/mach-types.h>
18#include <asm/mach/arch.h>
19#include "common.h"
20
21static struct mv643xx_eth_platform_data db78x00_ge00_data = {
22 .phy_addr = 8,
23};
24
25static struct mv643xx_eth_platform_data db78x00_ge01_data = {
26 .phy_addr = 9,
27};
28
29static struct mv643xx_eth_platform_data db78x00_ge10_data = {
30 .phy_addr = -1,
31};
32
33static struct mv643xx_eth_platform_data db78x00_ge11_data = {
34 .phy_addr = -1,
35};
36
37static struct mv_sata_platform_data db78x00_sata_data = {
38 .n_ports = 2,
39};
40
41static void __init db78x00_init(void)
42{
43 /*
44 * Basic MV78xx0 setup. Needs to be called early.
45 */
46 mv78xx0_init();
47
48 /*
49 * Partition on-chip peripherals between the two CPU cores.
50 */
51 if (mv78xx0_core_index() == 0) {
52 mv78xx0_ehci0_init();
53 mv78xx0_ehci1_init();
54 mv78xx0_ehci2_init();
55 mv78xx0_ge00_init(&db78x00_ge00_data);
56 mv78xx0_ge01_init(&db78x00_ge01_data);
57 mv78xx0_ge10_init(&db78x00_ge10_data);
58 mv78xx0_ge11_init(&db78x00_ge11_data);
59 mv78xx0_sata_init(&db78x00_sata_data);
60 mv78xx0_uart0_init();
61 mv78xx0_uart2_init();
62 } else {
63 mv78xx0_uart1_init();
64 mv78xx0_uart3_init();
65 }
66}
67
68static int __init db78x00_pci_init(void)
69{
70 if (machine_is_db78x00_bp()) {
71 /*
72 * Assign the x16 PCIe slot on the board to CPU core
73 * #0, and let CPU core #1 have the four x1 slots.
74 */
75 if (mv78xx0_core_index() == 0)
76 mv78xx0_pcie_init(0, 1);
77 else
78 mv78xx0_pcie_init(1, 0);
79 }
80
81 return 0;
82}
83subsys_initcall(db78x00_pci_init);
84
85MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
86 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
87 .phys_io = MV78XX0_REGS_PHYS_BASE,
88 .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
89 .boot_params = 0x00000100,
90 .init_machine = db78x00_init,
91 .map_io = mv78xx0_map_io,
92 .init_irq = mv78xx0_init_irq,
93 .timer = &mv78xx0_timer,
94MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
new file mode 100644
index 000000000000..60f4ee4d4532
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -0,0 +1,22 @@
1/*
2 * arch/arm/mach-mv78xx0/irq.c
3 *
4 * MV78xx0 IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/pci.h>
14#include <asm/arch/mv78xx0.h>
15#include <asm/plat-orion/irq.h>
16#include "common.h"
17
18void __init mv78xx0_init_irq(void)
19{
20 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
21 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
22}
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
new file mode 100644
index 000000000000..b78e1443159f
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -0,0 +1,312 @@
1/*
2 * arch/arm/mach-mv78xx0/pcie.c
3 *
4 * PCIe functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <asm/mach/pci.h>
15#include <asm/plat-orion/pcie.h>
16#include "common.h"
17
18struct pcie_port {
19 u8 maj;
20 u8 min;
21 u8 root_bus_nr;
22 void __iomem *base;
23 spinlock_t conf_lock;
24 char io_space_name[16];
25 char mem_space_name[16];
26 struct resource res[2];
27};
28
29static struct pcie_port pcie_port[8];
30static int num_pcie_ports;
31static struct resource pcie_io_space;
32static struct resource pcie_mem_space;
33
34
35static void __init mv78xx0_pcie_preinit(void)
36{
37 int i;
38 u32 size_each;
39 u32 start;
40 int win;
41
42 pcie_io_space.name = "PCIe I/O Space";
43 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
44 pcie_io_space.end =
45 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
46 pcie_io_space.flags = IORESOURCE_IO;
47 if (request_resource(&iomem_resource, &pcie_io_space))
48 panic("can't allocate PCIe I/O space");
49
50 pcie_mem_space.name = "PCIe MEM Space";
51 pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
52 pcie_mem_space.end =
53 MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
54 pcie_mem_space.flags = IORESOURCE_MEM;
55 if (request_resource(&iomem_resource, &pcie_mem_space))
56 panic("can't allocate PCIe MEM space");
57
58 for (i = 0; i < num_pcie_ports; i++) {
59 struct pcie_port *pp = pcie_port + i;
60
61 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
62 "PCIe %d.%d I/O", pp->maj, pp->min);
63 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
64 pp->res[0].name = pp->io_space_name;
65 pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
66 pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
67 pp->res[0].flags = IORESOURCE_IO;
68
69 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
70 "PCIe %d.%d MEM", pp->maj, pp->min);
71 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
72 pp->res[1].name = pp->mem_space_name;
73 pp->res[1].flags = IORESOURCE_MEM;
74 }
75
76 switch (num_pcie_ports) {
77 case 0:
78 size_each = 0;
79 break;
80
81 case 1:
82 size_each = 0x30000000;
83 break;
84
85 case 2 ... 3:
86 size_each = 0x10000000;
87 break;
88
89 case 4 ... 6:
90 size_each = 0x08000000;
91 break;
92
93 case 7:
94 size_each = 0x04000000;
95 break;
96
97 default:
98 panic("invalid number of PCIe ports");
99 }
100
101 start = MV78XX0_PCIE_MEM_PHYS_BASE;
102 for (i = 0; i < num_pcie_ports; i++) {
103 struct pcie_port *pp = pcie_port + i;
104
105 pp->res[1].start = start;
106 pp->res[1].end = start + size_each - 1;
107 start += size_each;
108 }
109
110 for (i = 0; i < num_pcie_ports; i++) {
111 struct pcie_port *pp = pcie_port + i;
112
113 if (request_resource(&pcie_io_space, &pp->res[0]))
114 panic("can't allocate PCIe I/O sub-space");
115
116 if (request_resource(&pcie_mem_space, &pp->res[1]))
117 panic("can't allocate PCIe MEM sub-space");
118 }
119
120 win = 0;
121 for (i = 0; i < num_pcie_ports; i++) {
122 struct pcie_port *pp = pcie_port + i;
123
124 mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
125 pp->res[0].end - pp->res[0].start + 1,
126 pp->maj, pp->min);
127
128 mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
129 pp->res[1].end - pp->res[1].start + 1,
130 pp->maj, pp->min);
131 }
132}
133
134static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
135{
136 struct pcie_port *pp;
137
138 if (nr >= num_pcie_ports)
139 return 0;
140
141 pp = &pcie_port[nr];
142 pp->root_bus_nr = sys->busnr;
143
144 /*
145 * Generic PCIe unit setup.
146 */
147 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
148 orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
149
150 sys->resource[0] = &pp->res[0];
151 sys->resource[1] = &pp->res[1];
152 sys->resource[2] = NULL;
153
154 return 1;
155}
156
157static struct pcie_port *bus_to_port(int bus)
158{
159 int i;
160
161 for (i = num_pcie_ports - 1; i >= 0; i--) {
162 int rbus = pcie_port[i].root_bus_nr;
163 if (rbus != -1 && rbus <= bus)
164 break;
165 }
166
167 return i >= 0 ? pcie_port + i : NULL;
168}
169
170static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
171{
172 /*
173 * Don't go out when trying to access nonexisting devices
174 * on the local bus.
175 */
176 if (bus == pp->root_bus_nr && dev > 1)
177 return 0;
178
179 return 1;
180}
181
182static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
183 int size, u32 *val)
184{
185 struct pcie_port *pp = bus_to_port(bus->number);
186 unsigned long flags;
187 int ret;
188
189 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
190 *val = 0xffffffff;
191 return PCIBIOS_DEVICE_NOT_FOUND;
192 }
193
194 spin_lock_irqsave(&pp->conf_lock, flags);
195 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
196 spin_unlock_irqrestore(&pp->conf_lock, flags);
197
198 return ret;
199}
200
201static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
202 int where, int size, u32 val)
203{
204 struct pcie_port *pp = bus_to_port(bus->number);
205 unsigned long flags;
206 int ret;
207
208 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
209 return PCIBIOS_DEVICE_NOT_FOUND;
210
211 spin_lock_irqsave(&pp->conf_lock, flags);
212 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
213 spin_unlock_irqrestore(&pp->conf_lock, flags);
214
215 return ret;
216}
217
218static struct pci_ops pcie_ops = {
219 .read = pcie_rd_conf,
220 .write = pcie_wr_conf,
221};
222
223static void __devinit rc_pci_fixup(struct pci_dev *dev)
224{
225 /*
226 * Prevent enumeration of root complex.
227 */
228 if (dev->bus->parent == NULL && dev->devfn == 0) {
229 int i;
230
231 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
232 dev->resource[i].start = 0;
233 dev->resource[i].end = 0;
234 dev->resource[i].flags = 0;
235 }
236 }
237}
238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
239
240static struct pci_bus __init *
241mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
242{
243 struct pci_bus *bus;
244
245 if (nr < num_pcie_ports) {
246 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
247 } else {
248 bus = NULL;
249 BUG();
250 }
251
252 return bus;
253}
254
255static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
256{
257 struct pcie_port *pp = bus_to_port(dev->bus->number);
258
259 return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
260}
261
262static struct hw_pci mv78xx0_pci __initdata = {
263 .nr_controllers = 8,
264 .preinit = mv78xx0_pcie_preinit,
265 .swizzle = pci_std_swizzle,
266 .setup = mv78xx0_pcie_setup,
267 .scan = mv78xx0_pcie_scan_bus,
268 .map_irq = mv78xx0_pcie_map_irq,
269};
270
271static void __init add_pcie_port(int maj, int min, unsigned long base)
272{
273 printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
274
275 if (orion_pcie_link_up((void __iomem *)base)) {
276 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
277
278 printk("link up\n");
279
280 pp->maj = maj;
281 pp->min = min;
282 pp->root_bus_nr = -1;
283 pp->base = (void __iomem *)base;
284 spin_lock_init(&pp->conf_lock);
285 memset(pp->res, 0, sizeof(pp->res));
286 } else {
287 printk("link down, ignoring\n");
288 }
289}
290
291void __init mv78xx0_pcie_init(int init_port0, int init_port1)
292{
293 if (init_port0) {
294 add_pcie_port(0, 0, PCIE00_VIRT_BASE);
295 if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
296 add_pcie_port(0, 1, PCIE01_VIRT_BASE);
297 add_pcie_port(0, 2, PCIE02_VIRT_BASE);
298 add_pcie_port(0, 3, PCIE03_VIRT_BASE);
299 }
300 }
301
302 if (init_port1) {
303 add_pcie_port(1, 0, PCIE10_VIRT_BASE);
304 if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
305 add_pcie_port(1, 1, PCIE11_VIRT_BASE);
306 add_pcie_port(1, 2, PCIE12_VIRT_BASE);
307 add_pcie_port(1, 3, PCIE13_VIRT_BASE);
308 }
309 }
310
311 pci_common_init(&mv78xx0_pci);
312}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 18:41:11 -0500