2 files changed, 296 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
new file mode 100644
index 000000000000..c7f083c53d4b
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,293 @@
+/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Code Aurora nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef __ASM_ARCH_MSM_IRQS_8960_H
+#define __ASM_ARCH_MSM_IRQS_8960_H
+/* MSM ACPU Interrupt Numbers */
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+   16-31: PPI (private peripheral interrupts)
+   32+:   SPI (shared peripheral interrupts) */
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+#define INT_VGIC                                (GIC_PPI_START + 0)
+#define INT_DEBUG_TIMER_EXP                     (GIC_PPI_START + 1)
+#define INT_GP_TIMER_EXP                        (GIC_PPI_START + 2)
+#define INT_GP_TIMER2_EXP                       (GIC_PPI_START + 3)
+#define WDT0_ACCSCSSNBARK_INT                   (GIC_PPI_START + 4)
+#define WDT1_ACCSCSSNBARK_INT                   (GIC_PPI_START + 5)
+#define AVS_SVICINT                             (GIC_PPI_START + 6)
+#define AVS_SVICINTSWDONE                       (GIC_PPI_START + 7)
+#define CPU_DBGCPUXCOMMRXFULL                   (GIC_PPI_START + 8)
+#define CPU_DBGCPUXCOMMTXEMPTY                  (GIC_PPI_START + 9)
+#define CPU_SICCPUXPERFMONIRPTREQ               (GIC_PPI_START + 10)
+#define SC_AVSCPUXDOWN                          (GIC_PPI_START + 11)
+#define SC_AVSCPUXUP                            (GIC_PPI_START + 12)
+#define SC_SICCPUXACGIRPTREQ                    (GIC_PPI_START + 13)
+#define SC_SICCPUXEXTFAULTIRPTREQ               (GIC_PPI_START + 14)
+/* PPI 15 is unused */
+#define SC_SICMPUIRPTREQ                        (GIC_SPI_START + 0)
+#define SC_SICL2IRPTREQ                         (GIC_SPI_START + 1)
+#define SC_SICL2PERFMONIRPTREQ                  (GIC_SPI_START + 2)
+#define SC_SICAGCIRPTREQ                        (GIC_SPI_START + 3)
+#define TLMM_APCC_DIR_CONN_IRQ_0                (GIC_SPI_START + 4)
+#define TLMM_APCC_DIR_CONN_IRQ_1                (GIC_SPI_START + 5)
+#define TLMM_APCC_DIR_CONN_IRQ_2                (GIC_SPI_START + 6)
+#define TLMM_APCC_DIR_CONN_IRQ_3                (GIC_SPI_START + 7)
+#define TLMM_APCC_DIR_CONN_IRQ_4                (GIC_SPI_START + 8)
+#define TLMM_APCC_DIR_CONN_IRQ_5                (GIC_SPI_START + 9)
+#define TLMM_APCC_DIR_CONN_IRQ_6                (GIC_SPI_START + 10)
+#define TLMM_APCC_DIR_CONN_IRQ_7                (GIC_SPI_START + 11)
+#define TLMM_APCC_DIR_CONN_IRQ_8                (GIC_SPI_START + 12)
+#define TLMM_APCC_DIR_CONN_IRQ_9                (GIC_SPI_START + 13)
+#define PM8921_SEC_IRQ_103                      (GIC_SPI_START + 14)
+#define PM8018_SEC_IRQ_106                      (GIC_SPI_START + 15)
+#define TLMM_APCC_SUMMARY_IRQ                   (GIC_SPI_START + 16)
+#define SPDM_RT_1_IRQ                           (GIC_SPI_START + 17)
+#define SPDM_DIAG_IRQ                           (GIC_SPI_START + 18)
+#define RPM_APCC_CPU0_GP_HIGH_IRQ               (GIC_SPI_START + 19)
+#define RPM_APCC_CPU0_GP_MEDIUM_IRQ             (GIC_SPI_START + 20)
+#define RPM_APCC_CPU0_GP_LOW_IRQ                (GIC_SPI_START + 21)
+#define RPM_APCC_CPU0_WAKE_UP_IRQ               (GIC_SPI_START + 22)
+#define RPM_APCC_CPU1_GP_HIGH_IRQ               (GIC_SPI_START + 23)
+#define RPM_APCC_CPU1_GP_MEDIUM_IRQ             (GIC_SPI_START + 24)
+#define RPM_APCC_CPU1_GP_LOW_IRQ                (GIC_SPI_START + 25)
+#define RPM_APCC_CPU1_WAKE_UP_IRQ               (GIC_SPI_START + 26)
+#define SSBI2_2_SC_CPU0_SECURE_IRQ              (GIC_SPI_START + 27)
+#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ          (GIC_SPI_START + 28)
+#define SSBI2_1_SC_CPU0_SECURE_IRQ              (GIC_SPI_START + 29)
+#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ          (GIC_SPI_START + 30)
+#define MSMC_SC_SEC_CE_IRQ                      (GIC_SPI_START + 31)
+#define MSMC_SC_PRI_CE_IRQ                      (GIC_SPI_START + 32)
+#define SLIMBUS0_CORE_EE1_IRQ                   (GIC_SPI_START + 33)
+#define SLIMBUS0_BAM_EE1_IRQ                    (GIC_SPI_START + 34)
+#define Q6FW_WDOG_EXPIRED_IRQ                   (GIC_SPI_START + 35)
+#define Q6SW_WDOG_EXPIRED_IRQ                   (GIC_SPI_START + 36)
+#define MSS_TO_APPS_IRQ_0                       (GIC_SPI_START + 37)
+#define MSS_TO_APPS_IRQ_1                       (GIC_SPI_START + 38)
+#define MSS_TO_APPS_IRQ_2                       (GIC_SPI_START + 39)
+#define MSS_TO_APPS_IRQ_3                       (GIC_SPI_START + 40)
+#define MSS_TO_APPS_IRQ_4                       (GIC_SPI_START + 41)
+#define MSS_TO_APPS_IRQ_5                       (GIC_SPI_START + 42)
+#define MSS_TO_APPS_IRQ_6                       (GIC_SPI_START + 43)
+#define MSS_TO_APPS_IRQ_7                       (GIC_SPI_START + 44)
+#define MSS_TO_APPS_IRQ_8                       (GIC_SPI_START + 45)
+#define MSS_TO_APPS_IRQ_9                       (GIC_SPI_START + 46)
+#define VPE_IRQ                                 (GIC_SPI_START + 47)
+#define VFE_IRQ                                 (GIC_SPI_START + 48)
+#define VCODEC_IRQ                              (GIC_SPI_START + 49)
+#define TV_ENC_IRQ                              (GIC_SPI_START + 50)
+#define SMMU_VPE_CB_SC_SECURE_IRQ               (GIC_SPI_START + 51)
+#define SMMU_VPE_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 52)
+#define SMMU_VFE_CB_SC_SECURE_IRQ               (GIC_SPI_START + 53)
+#define SMMU_VFE_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 54)
+#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ          (GIC_SPI_START + 55)
+#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ      (GIC_SPI_START + 56)
+#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ          (GIC_SPI_START + 57)
+#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ      (GIC_SPI_START + 58)
+#define SMMU_ROT_CB_SC_SECURE_IRQ               (GIC_SPI_START + 59)
+#define SMMU_ROT_CB_SC_NON_SECURE_IRQ           (GIC_SPI_START + 60)
+#define SMMU_MDP1_CB_SC_SECURE_IRQ              (GIC_SPI_START + 61)
+#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ          (GIC_SPI_START + 62)
+#define SMMU_MDP0_CB_SC_SECURE_IRQ              (GIC_SPI_START + 63)
+#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ          (GIC_SPI_START + 64)
+#define SMMU_JPEGD_CB_SC_SECURE_IRQ             (GIC_SPI_START + 65)
+#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 66)
+#define SMMU_IJPEG_CB_SC_SECURE_IRQ             (GIC_SPI_START + 67)
+#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 68)
+#define SMMU_GFX3D_CB_SC_SECURE_IRQ             (GIC_SPI_START + 69)
+#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ         (GIC_SPI_START + 70)
+#define SMMU_GFX2D0_CB_SC_SECURE_IRQ            (GIC_SPI_START + 71)
+#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 72)
+#define ROT_IRQ                                 (GIC_SPI_START + 73)
+#define MMSS_FABRIC_IRQ                         (GIC_SPI_START + 74)
+#define MDP_IRQ                                 (GIC_SPI_START + 75)
+#define JPEGD_IRQ                               (GIC_SPI_START + 76)
+#define JPEG_IRQ                                (GIC_SPI_START + 77)
+#define MMSS_IMEM_IRQ                           (GIC_SPI_START + 78)
+#define HDMI_IRQ                                (GIC_SPI_START + 79)
+#define GFX3D_IRQ                               (GIC_SPI_START + 80)
+#define GFX2D0_IRQ                              (GIC_SPI_START + 81)
+#define DSI1_IRQ                                (GIC_SPI_START + 82)
+#define CSI_1_IRQ                               (GIC_SPI_START + 83)
+#define CSI_0_IRQ                               (GIC_SPI_START + 84)
+#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ            (GIC_SPI_START + 85)
+#define LPASS_SCSS_MIDI_IRQ                     (GIC_SPI_START + 86)
+#define LPASS_Q6SS_WDOG_EXPIRED                 (GIC_SPI_START + 87)
+#define LPASS_SCSS_GP_LOW_IRQ                   (GIC_SPI_START + 88)
+#define LPASS_SCSS_GP_MEDIUM_IRQ                (GIC_SPI_START + 89)
+#define LPASS_SCSS_GP_HIGH_IRQ                  (GIC_SPI_START + 90)
+#define TOP_IMEM_IRQ                            (GIC_SPI_START + 91)
+#define FABRIC_SYS_IRQ                          (GIC_SPI_START + 92)
+#define FABRIC_APPS_IRQ                         (GIC_SPI_START + 93)
+#define USB1_HS_BAM_IRQ                         (GIC_SPI_START + 94)
+#define SDC4_BAM_IRQ                            (GIC_SPI_START + 95)
+#define SDC3_BAM_IRQ                            (GIC_SPI_START + 96)
+#define SDC2_BAM_IRQ                            (GIC_SPI_START + 97)
+#define SDC1_BAM_IRQ                            (GIC_SPI_START + 98)
+#define FABRIC_SPS_IRQ                          (GIC_SPI_START + 99)
+#define USB1_HS_IRQ                             (GIC_SPI_START + 100)
+#define SDC4_IRQ_0                              (GIC_SPI_START + 101)
+#define SDC3_IRQ_0                              (GIC_SPI_START + 102)
+#define SDC2_IRQ_0                              (GIC_SPI_START + 103)
+#define SDC1_IRQ_0                              (GIC_SPI_START + 104)
+#define SPS_BAM_DMA_IRQ                         (GIC_SPI_START + 105)
+#define SPS_SEC_VIOL_IRQ                        (GIC_SPI_START + 106)
+#define SPS_MTI_0                               (GIC_SPI_START + 107)
+#define SPS_MTI_1                               (GIC_SPI_START + 108)
+#define SPS_MTI_2                               (GIC_SPI_START + 109)
+#define SPS_MTI_3                               (GIC_SPI_START + 110)
+#define SPS_MTI_4                               (GIC_SPI_START + 111)
+#define SPS_MTI_5                               (GIC_SPI_START + 112)
+#define SPS_MTI_6                               (GIC_SPI_START + 113)
+#define SPS_MTI_7                               (GIC_SPI_START + 114)
+#define SPS_MTI_8                               (GIC_SPI_START + 115)
+#define SPS_MTI_9                               (GIC_SPI_START + 116)
+#define SPS_MTI_10                              (GIC_SPI_START + 117)
+#define SPS_MTI_11                              (GIC_SPI_START + 118)
+#define SPS_MTI_12                              (GIC_SPI_START + 119)
+#define SPS_MTI_13                              (GIC_SPI_START + 120)
+#define SPS_MTI_14                              (GIC_SPI_START + 121)
+#define SPS_MTI_15                              (GIC_SPI_START + 122)
+#define SPS_MTI_16                              (GIC_SPI_START + 123)
+#define SPS_MTI_17                              (GIC_SPI_START + 124)
+#define SPS_MTI_18                              (GIC_SPI_START + 125)
+#define SPS_MTI_19                              (GIC_SPI_START + 126)
+#define SPS_MTI_20                              (GIC_SPI_START + 127)
+#define SPS_MTI_21                              (GIC_SPI_START + 128)
+#define SPS_MTI_22                              (GIC_SPI_START + 129)
+#define SPS_MTI_23                              (GIC_SPI_START + 130)
+#define SPS_MTI_24                              (GIC_SPI_START + 131)
+#define SPS_MTI_25                              (GIC_SPI_START + 132)
+#define SPS_MTI_26                              (GIC_SPI_START + 133)
+#define SPS_MTI_27                              (GIC_SPI_START + 134)
+#define SPS_MTI_28                              (GIC_SPI_START + 135)
+#define SPS_MTI_29                              (GIC_SPI_START + 136)
+#define SPS_MTI_30                              (GIC_SPI_START + 137)
+#define SPS_MTI_31                              (GIC_SPI_START + 138)
+#define CSIPHY_4LN_IRQ                          (GIC_SPI_START + 139)
+#define CSIPHY_2LN_IRQ                          (GIC_SPI_START + 140)
+#define USB2_IRQ                                (GIC_SPI_START + 141)
+#define USB1_IRQ                                (GIC_SPI_START + 142)
+#define TSSC_SSBI_IRQ                           (GIC_SPI_START + 143)
+#define TSSC_SAMPLE_IRQ                         (GIC_SPI_START + 144)
+#define TSSC_PENUP_IRQ                          (GIC_SPI_START + 145)
+#define GSBI1_UARTDM_IRQ                        (GIC_SPI_START + 146)
+#define GSBI1_QUP_IRQ                           (GIC_SPI_START + 147)
+#define GSBI2_UARTDM_IRQ                        (GIC_SPI_START + 148)
+#define GSBI2_QUP_IRQ                           (GIC_SPI_START + 149)
+#define GSBI3_UARTDM_IRQ                        (GIC_SPI_START + 150)
+#define GSBI3_QUP_IRQ                           (GIC_SPI_START + 151)
+#define GSBI4_UARTDM_IRQ                        (GIC_SPI_START + 152)
+#define GSBI4_QUP_IRQ                           (GIC_SPI_START + 153)
+#define GSBI5_UARTDM_IRQ                        (GIC_SPI_START + 154)
+#define GSBI5_QUP_IRQ                           (GIC_SPI_START + 155)
+#define GSBI6_UARTDM_IRQ                        (GIC_SPI_START + 156)
+#define GSBI6_QUP_IRQ                           (GIC_SPI_START + 157)
+#define GSBI7_UARTDM_IRQ                        (GIC_SPI_START + 158)
+#define GSBI7_QUP_IRQ                           (GIC_SPI_START + 159)
+#define GSBI8_UARTDM_IRQ                        (GIC_SPI_START + 160)
+#define GSBI8_QUP_IRQ                           (GIC_SPI_START + 161)
+#define TSIF_TSPP_IRQ                           (GIC_SPI_START + 162)
+#define TSIF_BAM_IRQ                            (GIC_SPI_START + 163)
+#define TSIF2_IRQ                               (GIC_SPI_START + 164)
+#define TSIF1_IRQ                               (GIC_SPI_START + 165)
+#define DSI2_IRQ                                (GIC_SPI_START + 166)
+#define ISPIF_IRQ                               (GIC_SPI_START + 167)
+#define MSMC_SC_SEC_TMR_IRQ                     (GIC_SPI_START + 168)
+#define MSMC_SC_SEC_WDOG_BARK_IRQ               (GIC_SPI_START + 169)
+#define INT_ADM0_SCSS_0_IRQ                     (GIC_SPI_START + 170)
+#define INT_ADM0_SCSS_1_IRQ                     (GIC_SPI_START + 171)
+#define INT_ADM0_SCSS_2_IRQ                     (GIC_SPI_START + 172)
+#define INT_ADM0_SCSS_3_IRQ                     (GIC_SPI_START + 173)
+#define CC_SCSS_WDT1CPU1BITEEXPIRED             (GIC_SPI_START + 174)
+#define CC_SCSS_WDT1CPU0BITEEXPIRED             (GIC_SPI_START + 175)
+#define CC_SCSS_WDT0CPU1BITEEXPIRED             (GIC_SPI_START + 176)
+#define CC_SCSS_WDT0CPU0BITEEXPIRED             (GIC_SPI_START + 177)
+#define TSENS_UPPER_LOWER_INT                   (GIC_SPI_START + 178)
+#define SSBI2_2_SC_CPU1_SECURE_INT              (GIC_SPI_START + 179)
+#define SSBI2_2_SC_CPU1_NON_SECURE_INT          (GIC_SPI_START + 180)
+#define SSBI2_1_SC_CPU1_SECURE_INT              (GIC_SPI_START + 181)
+#define SSBI2_1_SC_CPU1_NON_SECURE_INT          (GIC_SPI_START + 182)
+#define XPU_SUMMARY_IRQ                         (GIC_SPI_START + 183)
+#define BUS_EXCEPTION_SUMMARY_IRQ               (GIC_SPI_START + 184)
+#define HSDDRX_EBI1CH0_IRQ                      (GIC_SPI_START + 185)
+#define HSDDRX_EBI1CH1_IRQ                      (GIC_SPI_START + 186)
+#define SDC5_BAM_IRQ                            (GIC_SPI_START + 187)
+#define SDC5_IRQ_0                              (GIC_SPI_START + 188)
+#define GSBI9_UARTDM_IRQ                        (GIC_SPI_START + 189)
+#define GSBI9_QUP_IRQ                           (GIC_SPI_START + 190)
+#define GSBI10_UARTDM_IRQ                       (GIC_SPI_START + 191)
+#define GSBI10_QUP_IRQ                          (GIC_SPI_START + 192)
+#define GSBI11_UARTDM_IRQ                       (GIC_SPI_START + 193)
+#define GSBI11_QUP_IRQ                          (GIC_SPI_START + 194)
+#define GSBI12_UARTDM_IRQ                       (GIC_SPI_START + 195)
+#define GSBI12_QUP_IRQ                          (GIC_SPI_START + 196)
+#define RIVA_APSS_LTECOEX_IRQ                   (GIC_SPI_START + 197)
+#define RIVA_APSS_SPARE_IRQ                     (GIC_SPI_START + 198)
+#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ       (GIC_SPI_START + 199)
+#define RIVA_ASS_RESET_DONE_IRQ                 (GIC_SPI_START + 200)
+#define RIVA_APSS_ASIC_IRQ                      (GIC_SPI_START + 201)
+#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ        (GIC_SPI_START + 202)
+#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ       (GIC_SPI_START + 203)
+#define RIVA_APPS_WLAM_SMSM_IRQ                 (GIC_SPI_START + 204)
+#define RIVA_APPS_LOG_CTRL_IRQ                  (GIC_SPI_START + 205)
+#define RIVA_APPS_FM_CTRL_IRQ                   (GIC_SPI_START + 206)
+#define RIVA_APPS_HCI_IRQ                       (GIC_SPI_START + 207)
+#define RIVA_APPS_WLAN_CTRL_IRQ                 (GIC_SPI_START + 208)
+#define A2_BAM_IRQ                              (GIC_SPI_START + 209)
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ            (GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ        (GIC_SPI_START + 211)
+#define GFX2D1_IRQ                              (GIC_SPI_START + 212)
+#define PPSS_WDOG_TIMER_IRQ                     (GIC_SPI_START + 213)
+#define SPS_SLIMBUS_CORE_EE0_IRQ                (GIC_SPI_START + 214)
+#define SPS_SLIMBUS_BAM_EE0_IRQ                 (GIC_SPI_START + 215)
+#define QDSS_ETB_IRQ                            (GIC_SPI_START + 216)
+#define QDSS_CTI2KPSS_CPU1_IRQ                  (GIC_SPI_START + 217)
+#define QDSS_CTI2KPSS_CPU0_IRQ                  (GIC_SPI_START + 218)
+#define TLMM_APCC_DIR_CONN_IRQ_16               (GIC_SPI_START + 219)
+#define TLMM_APCC_DIR_CONN_IRQ_17               (GIC_SPI_START + 220)
+#define TLMM_APCC_DIR_CONN_IRQ_18               (GIC_SPI_START + 221)
+#define TLMM_APCC_DIR_CONN_IRQ_19               (GIC_SPI_START + 222)
+#define TLMM_APCC_DIR_CONN_IRQ_20               (GIC_SPI_START + 223)
+#define TLMM_APCC_DIR_CONN_IRQ_21               (GIC_SPI_START + 224)
+#define PM8921_SEC_IRQ_104                      (GIC_SPI_START + 225)
+#define PM8018_SEC_IRQ_107                      (GIC_SPI_START + 226)
+/* For now, use the maximum number of interrupts until a pending GIC issue
+ * is sorted out */
+#define NR_MSM_IRQS 1020
+#define NR_BOARD_IRQS 0
+#define NR_GPIO_IRQS 0
+#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8679a4564744..3cd78b165abb 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,9 @@
 #include "sirc.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "irqs-8x60.h"
+#elif defined(CONFIG_ARCH_MSM8960)
+/* TODO: Make these not generic. */
+#include "irqs-8960.h"
 #elif defined(CONFIG_ARCH_MSM_ARM11)
 #include "irqs-7x00.h"
 #else

diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h new file mode 100644 index 000000000000..c7f083c53d4b --- /dev/null +++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,293 @@
		1	/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
		2	*
		3	* Redistribution and use in source and binary forms, with or without
		4	* modification, are permitted provided that the following conditions are met:
		5	* * Redistributions of source code must retain the above copyright
		6	* notice, this list of conditions and the following disclaimer.
		7	* * Redistributions in binary form must reproduce the above copyright
		8	* notice, this list of conditions and the following disclaimer in the
		9	* documentation and/or other materials provided with the distribution.
		10	* * Neither the name of Code Aurora nor
		11	* the names of its contributors may be used to endorse or promote
		12	* products derived from this software without specific prior written
		13	* permission.
		14	*
		15	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		16	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
		17	* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
		18	* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
		19	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
		20	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
		21	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
		22	* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
		23	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
		24	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
		25	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
		26	*
		27	*/
		28
		29	#ifndef __ASM_ARCH_MSM_IRQS_8960_H
		30	#define __ASM_ARCH_MSM_IRQS_8960_H
		31
		32	/* MSM ACPU Interrupt Numbers */
		33
		34	/* 0-15: STI/SGI (software triggered/generated interrupts)
		35	16-31: PPI (private peripheral interrupts)
		36	32+: SPI (shared peripheral interrupts) */
		37
		38	#define GIC_PPI_START 16
		39	#define GIC_SPI_START 32
		40
		41	#define INT_VGIC (GIC_PPI_START + 0)
		42	#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
		43	#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
		44	#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
		45	#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
		46	#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
		47	#define AVS_SVICINT (GIC_PPI_START + 6)
		48	#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
		49	#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
		50	#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
		51	#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10)
		52	#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
		53	#define SC_AVSCPUXUP (GIC_PPI_START + 12)
		54	#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
		55	#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
		56	/* PPI 15 is unused */
		57
		58	#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
		59	#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
		60	#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2)
		61	#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3)
		62	#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
		63	#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
		64	#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
		65	#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
		66	#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
		67	#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
		68	#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
		69	#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
		70	#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
		71	#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
		72	#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14)
		73	#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15)
		74	#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16)
		75	#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
		76	#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
		77	#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
		78	#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
		79	#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
		80	#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
		81	#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
		82	#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
		83	#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
		84	#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
		85	#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27)
		86	#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28)
		87	#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
		88	#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
		89	#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
		90	#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
		91	#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
		92	#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
		93	#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
		94	#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
		95	#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
		96	#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
		97	#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
		98	#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
		99	#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
		100	#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
		101	#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
		102	#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
		103	#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
		104	#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
		105	#define VPE_IRQ (GIC_SPI_START + 47)
		106	#define VFE_IRQ (GIC_SPI_START + 48)
		107	#define VCODEC_IRQ (GIC_SPI_START + 49)
		108	#define TV_ENC_IRQ (GIC_SPI_START + 50)
		109	#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
		110	#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
		111	#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
		112	#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
		113	#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
		114	#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
		115	#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
		116	#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
		117	#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
		118	#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
		119	#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
		120	#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
		121	#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
		122	#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
		123	#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
		124	#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
		125	#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
		126	#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
		127	#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
		128	#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
		129	#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
		130	#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
		131	#define ROT_IRQ (GIC_SPI_START + 73)
		132	#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
		133	#define MDP_IRQ (GIC_SPI_START + 75)
		134	#define JPEGD_IRQ (GIC_SPI_START + 76)
		135	#define JPEG_IRQ (GIC_SPI_START + 77)
		136	#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
		137	#define HDMI_IRQ (GIC_SPI_START + 79)
		138	#define GFX3D_IRQ (GIC_SPI_START + 80)
		139	#define GFX2D0_IRQ (GIC_SPI_START + 81)
		140	#define DSI1_IRQ (GIC_SPI_START + 82)
		141	#define CSI_1_IRQ (GIC_SPI_START + 83)
		142	#define CSI_0_IRQ (GIC_SPI_START + 84)
		143	#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
		144	#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
		145	#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
		146	#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
		147	#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
		148	#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
		149	#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
		150	#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
		151	#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
		152	#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
		153	#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
		154	#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
		155	#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
		156	#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
		157	#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
		158	#define USB1_HS_IRQ (GIC_SPI_START + 100)
		159	#define SDC4_IRQ_0 (GIC_SPI_START + 101)
		160	#define SDC3_IRQ_0 (GIC_SPI_START + 102)
		161	#define SDC2_IRQ_0 (GIC_SPI_START + 103)
		162	#define SDC1_IRQ_0 (GIC_SPI_START + 104)
		163	#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
		164	#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
		165	#define SPS_MTI_0 (GIC_SPI_START + 107)
		166	#define SPS_MTI_1 (GIC_SPI_START + 108)
		167	#define SPS_MTI_2 (GIC_SPI_START + 109)
		168	#define SPS_MTI_3 (GIC_SPI_START + 110)
		169	#define SPS_MTI_4 (GIC_SPI_START + 111)
		170	#define SPS_MTI_5 (GIC_SPI_START + 112)
		171	#define SPS_MTI_6 (GIC_SPI_START + 113)
		172	#define SPS_MTI_7 (GIC_SPI_START + 114)
		173	#define SPS_MTI_8 (GIC_SPI_START + 115)
		174	#define SPS_MTI_9 (GIC_SPI_START + 116)
		175	#define SPS_MTI_10 (GIC_SPI_START + 117)
		176	#define SPS_MTI_11 (GIC_SPI_START + 118)
		177	#define SPS_MTI_12 (GIC_SPI_START + 119)
		178	#define SPS_MTI_13 (GIC_SPI_START + 120)
		179	#define SPS_MTI_14 (GIC_SPI_START + 121)
		180	#define SPS_MTI_15 (GIC_SPI_START + 122)
		181	#define SPS_MTI_16 (GIC_SPI_START + 123)
		182	#define SPS_MTI_17 (GIC_SPI_START + 124)
		183	#define SPS_MTI_18 (GIC_SPI_START + 125)
		184	#define SPS_MTI_19 (GIC_SPI_START + 126)
		185	#define SPS_MTI_20 (GIC_SPI_START + 127)
		186	#define SPS_MTI_21 (GIC_SPI_START + 128)
		187	#define SPS_MTI_22 (GIC_SPI_START + 129)
		188	#define SPS_MTI_23 (GIC_SPI_START + 130)
		189	#define SPS_MTI_24 (GIC_SPI_START + 131)
		190	#define SPS_MTI_25 (GIC_SPI_START + 132)
		191	#define SPS_MTI_26 (GIC_SPI_START + 133)
		192	#define SPS_MTI_27 (GIC_SPI_START + 134)
		193	#define SPS_MTI_28 (GIC_SPI_START + 135)
		194	#define SPS_MTI_29 (GIC_SPI_START + 136)
		195	#define SPS_MTI_30 (GIC_SPI_START + 137)
		196	#define SPS_MTI_31 (GIC_SPI_START + 138)
		197	#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139)
		198	#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140)
		199	#define USB2_IRQ (GIC_SPI_START + 141)
		200	#define USB1_IRQ (GIC_SPI_START + 142)
		201	#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
		202	#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
		203	#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
		204	#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
		205	#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
		206	#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
		207	#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
		208	#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
		209	#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
		210	#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
		211	#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
		212	#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
		213	#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
		214	#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156)
		215	#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
		216	#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158)
		217	#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
		218	#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160)
		219	#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
		220	#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
		221	#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
		222	#define TSIF2_IRQ (GIC_SPI_START + 164)
		223	#define TSIF1_IRQ (GIC_SPI_START + 165)
		224	#define DSI2_IRQ (GIC_SPI_START + 166)
		225	#define ISPIF_IRQ (GIC_SPI_START + 167)
		226	#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
		227	#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
		228	#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170)
		229	#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171)
		230	#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172)
		231	#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173)
		232	#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
		233	#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
		234	#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
		235	#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
		236	#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
		237	#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
		238	#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
		239	#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
		240	#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
		241	#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
		242	#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
		243	#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
		244	#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186)
		245	#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
		246	#define SDC5_IRQ_0 (GIC_SPI_START + 188)
		247	#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189)
		248	#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
		249	#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191)
		250	#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
		251	#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193)
		252	#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
		253	#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195)
		254	#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
		255	#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197)
		256	#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198)
		257	#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199)
		258	#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200)
		259	#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201)
		260	#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202)
		261	#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203)
		262	#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204)
		263	#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205)
		264	#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206)
		265	#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207)
		266	#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208)
		267	#define A2_BAM_IRQ (GIC_SPI_START + 209)
		268	#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
		269	#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
		270	#define GFX2D1_IRQ (GIC_SPI_START + 212)
		271	#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213)
		272	#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214)
		273	#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215)
		274	#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
		275	#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217)
		276	#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
		277	#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
		278	#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
		279	#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
		280	#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
		281	#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
		282	#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
		283	#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
		284	#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
		285
		286	/* For now, use the maximum number of interrupts until a pending GIC issue
		287	* is sorted out */
		288	#define NR_MSM_IRQS 1020
		289	#define NR_BOARD_IRQS 0
		290	#define NR_GPIO_IRQS 0
		291
		292	#endif
		293


diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h index 8679a4564744..3cd78b165abb 100644 --- a/arch/arm/mach-msm/include/mach/irqs.h +++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,9 @@
26	#include "sirc.h"	26	#include "sirc.h"
27	#elif defined(CONFIG_ARCH_MSM8X60)	27	#elif defined(CONFIG_ARCH_MSM8X60)
28	#include "irqs-8x60.h"	28	#include "irqs-8x60.h"
		29	#elif defined(CONFIG_ARCH_MSM8960)
		30	/* TODO: Make these not generic. */
		31	#include "irqs-8960.h"
29	#elif defined(CONFIG_ARCH_MSM_ARM11)	32	#elif defined(CONFIG_ARCH_MSM_ARM11)
30	#include "irqs-7x00.h"	33	#include "irqs-7x00.h"
31	#else	34	#else