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-rw-r--r--arch/arm/mach-msm/include/mach/cpu.h54
-rw-r--r--arch/arm/mach-msm/include/mach/io.h1
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8960.h293
-rw-r--r--arch/arm/mach-msm/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-msm/include/mach/memory.h2
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x00.h10
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x30.h14
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8960.h48
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h14
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h25
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h9
11 files changed, 427 insertions, 46 deletions
diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
new file mode 100644
index 000000000000..a9481b08d5c7
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/cpu.h
@@ -0,0 +1,54 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
19#define __ARCH_ARM_MACH_MSM_CPU_H__
20
21/* TODO: For now, only one CPU can be compiled at a time. */
22
23#define cpu_is_msm7x01() 0
24#define cpu_is_msm7x30() 0
25#define cpu_is_qsd8x50() 0
26#define cpu_is_msm8x60() 0
27#define cpu_is_msm8960() 0
28
29#ifdef CONFIG_ARCH_MSM7X00A
30# undef cpu_is_msm7x01
31# define cpu_is_msm7x01() 1
32#endif
33
34#ifdef CONFIG_ARCH_MSM7X30
35# undef cpu_is_msm7x30
36# define cpu_is_msm7x30() 1
37#endif
38
39#ifdef CONFIG_ARCH_QSD8X50
40# undef cpu_is_qsd8x50
41# define cpu_is_qsd8x50() 1
42#endif
43
44#ifdef CONFIG_ARCH_MSM8X60
45# undef cpu_is_msm8x60
46# define cpu_is_msm8x60() 1
47#endif
48
49#ifdef CONFIG_ARCH_MSM8960
50# undef cpu_is_msm8960
51# define cpu_is_msm8960() 1
52#endif
53
54#endif
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 7386e732baad..dc1b928745e9 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
29void msm_map_qsd8x50_io(void); 29void msm_map_qsd8x50_io(void);
30void msm_map_msm7x30_io(void); 30void msm_map_msm7x30_io(void);
31void msm_map_msm8x60_io(void); 31void msm_map_msm8x60_io(void);
32void msm_map_msm8960_io(void);
32 33
33extern unsigned int msm_shared_ram_phys; 34extern unsigned int msm_shared_ram_phys;
34 35
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
new file mode 100644
index 000000000000..c7f083c53d4b
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,293 @@
1/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Code Aurora nor
11 * the names of its contributors may be used to endorse or promote
12 * products derived from this software without specific prior written
13 * permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
19 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29#ifndef __ASM_ARCH_MSM_IRQS_8960_H
30#define __ASM_ARCH_MSM_IRQS_8960_H
31
32/* MSM ACPU Interrupt Numbers */
33
34/* 0-15: STI/SGI (software triggered/generated interrupts)
35 16-31: PPI (private peripheral interrupts)
36 32+: SPI (shared peripheral interrupts) */
37
38#define GIC_PPI_START 16
39#define GIC_SPI_START 32
40
41#define INT_VGIC (GIC_PPI_START + 0)
42#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
43#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
44#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
45#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
46#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
47#define AVS_SVICINT (GIC_PPI_START + 6)
48#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
49#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
50#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
51#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10)
52#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
53#define SC_AVSCPUXUP (GIC_PPI_START + 12)
54#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
55#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
56/* PPI 15 is unused */
57
58#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
59#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
60#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2)
61#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3)
62#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
63#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
64#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
65#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
66#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
67#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
68#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
69#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
70#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
71#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
72#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14)
73#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15)
74#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16)
75#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
76#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
77#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
78#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
79#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
80#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
81#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
82#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
83#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
84#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
85#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27)
86#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28)
87#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
88#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
89#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
90#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
91#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
92#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
93#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
94#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
95#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
96#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
97#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
98#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
99#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
100#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
101#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
102#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
103#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
104#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
105#define VPE_IRQ (GIC_SPI_START + 47)
106#define VFE_IRQ (GIC_SPI_START + 48)
107#define VCODEC_IRQ (GIC_SPI_START + 49)
108#define TV_ENC_IRQ (GIC_SPI_START + 50)
109#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
110#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
111#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
112#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
113#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
114#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
115#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
116#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
117#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
118#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
119#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
120#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
121#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
122#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
123#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
124#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
125#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
126#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
127#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
128#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
129#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
130#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
131#define ROT_IRQ (GIC_SPI_START + 73)
132#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
133#define MDP_IRQ (GIC_SPI_START + 75)
134#define JPEGD_IRQ (GIC_SPI_START + 76)
135#define JPEG_IRQ (GIC_SPI_START + 77)
136#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
137#define HDMI_IRQ (GIC_SPI_START + 79)
138#define GFX3D_IRQ (GIC_SPI_START + 80)
139#define GFX2D0_IRQ (GIC_SPI_START + 81)
140#define DSI1_IRQ (GIC_SPI_START + 82)
141#define CSI_1_IRQ (GIC_SPI_START + 83)
142#define CSI_0_IRQ (GIC_SPI_START + 84)
143#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
144#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
145#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
146#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
147#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
148#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
149#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
150#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
151#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
152#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
153#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
154#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
155#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
156#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
157#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
158#define USB1_HS_IRQ (GIC_SPI_START + 100)
159#define SDC4_IRQ_0 (GIC_SPI_START + 101)
160#define SDC3_IRQ_0 (GIC_SPI_START + 102)
161#define SDC2_IRQ_0 (GIC_SPI_START + 103)
162#define SDC1_IRQ_0 (GIC_SPI_START + 104)
163#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
164#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
165#define SPS_MTI_0 (GIC_SPI_START + 107)
166#define SPS_MTI_1 (GIC_SPI_START + 108)
167#define SPS_MTI_2 (GIC_SPI_START + 109)
168#define SPS_MTI_3 (GIC_SPI_START + 110)
169#define SPS_MTI_4 (GIC_SPI_START + 111)
170#define SPS_MTI_5 (GIC_SPI_START + 112)
171#define SPS_MTI_6 (GIC_SPI_START + 113)
172#define SPS_MTI_7 (GIC_SPI_START + 114)
173#define SPS_MTI_8 (GIC_SPI_START + 115)
174#define SPS_MTI_9 (GIC_SPI_START + 116)
175#define SPS_MTI_10 (GIC_SPI_START + 117)
176#define SPS_MTI_11 (GIC_SPI_START + 118)
177#define SPS_MTI_12 (GIC_SPI_START + 119)
178#define SPS_MTI_13 (GIC_SPI_START + 120)
179#define SPS_MTI_14 (GIC_SPI_START + 121)
180#define SPS_MTI_15 (GIC_SPI_START + 122)
181#define SPS_MTI_16 (GIC_SPI_START + 123)
182#define SPS_MTI_17 (GIC_SPI_START + 124)
183#define SPS_MTI_18 (GIC_SPI_START + 125)
184#define SPS_MTI_19 (GIC_SPI_START + 126)
185#define SPS_MTI_20 (GIC_SPI_START + 127)
186#define SPS_MTI_21 (GIC_SPI_START + 128)
187#define SPS_MTI_22 (GIC_SPI_START + 129)
188#define SPS_MTI_23 (GIC_SPI_START + 130)
189#define SPS_MTI_24 (GIC_SPI_START + 131)
190#define SPS_MTI_25 (GIC_SPI_START + 132)
191#define SPS_MTI_26 (GIC_SPI_START + 133)
192#define SPS_MTI_27 (GIC_SPI_START + 134)
193#define SPS_MTI_28 (GIC_SPI_START + 135)
194#define SPS_MTI_29 (GIC_SPI_START + 136)
195#define SPS_MTI_30 (GIC_SPI_START + 137)
196#define SPS_MTI_31 (GIC_SPI_START + 138)
197#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139)
198#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140)
199#define USB2_IRQ (GIC_SPI_START + 141)
200#define USB1_IRQ (GIC_SPI_START + 142)
201#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
202#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
203#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
204#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
205#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
206#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
207#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
208#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
209#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
210#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
211#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
212#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
213#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
214#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156)
215#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
216#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158)
217#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
218#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160)
219#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
220#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
221#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
222#define TSIF2_IRQ (GIC_SPI_START + 164)
223#define TSIF1_IRQ (GIC_SPI_START + 165)
224#define DSI2_IRQ (GIC_SPI_START + 166)
225#define ISPIF_IRQ (GIC_SPI_START + 167)
226#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
227#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
228#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170)
229#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171)
230#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172)
231#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173)
232#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
233#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
234#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
235#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
236#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
237#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
238#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
239#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
240#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
241#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
242#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
243#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
244#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186)
245#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
246#define SDC5_IRQ_0 (GIC_SPI_START + 188)
247#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189)
248#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
249#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191)
250#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
251#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193)
252#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
253#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195)
254#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
255#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197)
256#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198)
257#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199)
258#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200)
259#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201)
260#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202)
261#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203)
262#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204)
263#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205)
264#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206)
265#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207)
266#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208)
267#define A2_BAM_IRQ (GIC_SPI_START + 209)
268#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
269#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
270#define GFX2D1_IRQ (GIC_SPI_START + 212)
271#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213)
272#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214)
273#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215)
274#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
275#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217)
276#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
277#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
278#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
279#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
280#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
281#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
282#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
283#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
284#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
285
286/* For now, use the maximum number of interrupts until a pending GIC issue
287 * is sorted out */
288#define NR_MSM_IRQS 1020
289#define NR_BOARD_IRQS 0
290#define NR_GPIO_IRQS 0
291
292#endif
293
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8679a4564744..3cd78b165abb 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,9 @@
26#include "sirc.h" 26#include "sirc.h"
27#elif defined(CONFIG_ARCH_MSM8X60) 27#elif defined(CONFIG_ARCH_MSM8X60)
28#include "irqs-8x60.h" 28#include "irqs-8x60.h"
29#elif defined(CONFIG_ARCH_MSM8960)
30/* TODO: Make these not generic. */
31#include "irqs-8960.h"
29#elif defined(CONFIG_ARCH_MSM_ARM11) 32#elif defined(CONFIG_ARCH_MSM_ARM11)
30#include "irqs-7x00.h" 33#include "irqs-7x00.h"
31#else 34#else
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 070e17d237f1..014bbd3ac1d4 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -25,6 +25,8 @@
25#define PHYS_OFFSET UL(0x00200000) 25#define PHYS_OFFSET UL(0x00200000)
26#elif defined(CONFIG_ARCH_MSM8X60) 26#elif defined(CONFIG_ARCH_MSM8X60)
27#define PHYS_OFFSET UL(0x40200000) 27#define PHYS_OFFSET UL(0x40200000)
28#elif defined(CONFIG_ARCH_MSM8960)
29#define PHYS_OFFSET UL(0x40200000)
28#else 30#else
29#define PHYS_OFFSET UL(0x10000000) 31#define PHYS_OFFSET UL(0x10000000)
30#endif 32#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index cfff0e74f128..1e75ed74f169 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -1,6 +1,7 @@
1/* arch/arm/mach-msm/include/mach/msm_iomap.h 1/* arch/arm/mach-msm/include/mach/msm_iomap.h
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 5 * Author: Brian Swetland <swetland@google.com>
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
@@ -47,13 +48,8 @@
47#define MSM_VIC_PHYS 0xC0000000 48#define MSM_VIC_PHYS 0xC0000000
48#define MSM_VIC_SIZE SZ_4K 49#define MSM_VIC_SIZE SZ_4K
49 50
50#define MSM_CSR_BASE IOMEM(0xE0001000) 51#define MSM7X00_CSR_PHYS 0xC0100000
51#define MSM_CSR_PHYS 0xC0100000 52#define MSM7X00_CSR_SIZE SZ_4K
52#define MSM_CSR_SIZE SZ_4K
53
54#define MSM_GPT_PHYS MSM_CSR_PHYS
55#define MSM_GPT_BASE MSM_CSR_BASE
56#define MSM_GPT_SIZE SZ_4K
57 53
58#define MSM_DMOV_BASE IOMEM(0xE0002000) 54#define MSM_DMOV_BASE IOMEM(0xE0002000)
59#define MSM_DMOV_PHYS 0xA9700000 55#define MSM_DMOV_PHYS 0xA9700000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 0fd7b68ca114..4d84be15955e 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
39#define MSM_VIC_PHYS 0xC0080000 39#define MSM_VIC_PHYS 0xC0080000
40#define MSM_VIC_SIZE SZ_4K 40#define MSM_VIC_SIZE SZ_4K
41 41
42#define MSM_CSR_BASE IOMEM(0xE0001000) 42#define MSM7X30_CSR_PHYS 0xC0100000
43#define MSM_CSR_PHYS 0xC0100000 43#define MSM7X30_CSR_SIZE SZ_4K
44#define MSM_CSR_SIZE SZ_4K
45
46#define MSM_TMR_PHYS MSM_CSR_PHYS
47#define MSM_TMR_BASE MSM_CSR_BASE
48#define MSM_TMR_SIZE SZ_4K
49
50#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
51#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
52 44
53#define MSM_DMOV_BASE IOMEM(0xE0002000) 45#define MSM_DMOV_BASE IOMEM(0xE0002000)
54#define MSM_DMOV_PHYS 0xAC400000 46#define MSM_DMOV_PHYS 0xAC400000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
new file mode 100644
index 000000000000..3c9d9602a318
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
24#define __ASM_ARCH_MSM_IOMAP_8960_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * If you add or remove entries here, you'll want to edit the
30 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
31 * changes.
32 *
33 */
34
35
36#define MSM8960_QGIC_DIST_PHYS 0x02000000
37#define MSM8960_QGIC_DIST_SIZE SZ_4K
38
39#define MSM8960_QGIC_CPU_PHYS 0x02002000
40#define MSM8960_QGIC_CPU_SIZE SZ_4K
41
42#define MSM8960_TMR_PHYS 0x0200A000
43#define MSM8960_TMR_SIZE SZ_4K
44
45#define MSM8960_TMR0_PHYS 0x0208A000
46#define MSM8960_TMR0_SIZE SZ_4K
47
48#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index acc819eb76e5..cf1c2df1d953 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
39#define MSM_VIC_PHYS 0xAC000000 39#define MSM_VIC_PHYS 0xAC000000
40#define MSM_VIC_SIZE SZ_4K 40#define MSM_VIC_SIZE SZ_4K
41 41
42#define MSM_CSR_BASE IOMEM(0xE0001000) 42#define QSD8X50_CSR_PHYS 0xAC100000
43#define MSM_CSR_PHYS 0xAC100000 43#define QSD8X50_CSR_SIZE SZ_4K
44#define MSM_CSR_SIZE SZ_4K
45
46#define MSM_TMR_PHYS MSM_CSR_PHYS
47#define MSM_TMR_BASE MSM_CSR_BASE
48#define MSM_TMR_SIZE SZ_4K
49
50#define MSM_GPT_BASE MSM_TMR_BASE
51#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10)
52 44
53#define MSM_DMOV_BASE IOMEM(0xE0002000) 45#define MSM_DMOV_BASE IOMEM(0xE0002000)
54#define MSM_DMOV_PHYS 0xA9700000 46#define MSM_DMOV_PHYS 0xA9700000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index a54e33b0882e..5bd18db11aea 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -35,13 +35,11 @@
35 * 35 *
36 */ 36 */
37 37
38#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) 38#define MSM8X60_QGIC_DIST_PHYS 0x02080000
39#define MSM_QGIC_DIST_PHYS 0x02080000 39#define MSM8X60_QGIC_DIST_SIZE SZ_4K
40#define MSM_QGIC_DIST_SIZE SZ_4K
41 40
42#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) 41#define MSM8X60_QGIC_CPU_PHYS 0x02081000
43#define MSM_QGIC_CPU_PHYS 0x02081000 42#define MSM8X60_QGIC_CPU_SIZE SZ_4K
44#define MSM_QGIC_CPU_SIZE SZ_4K
45 43
46#define MSM_ACC_BASE IOMEM(0xF0002000) 44#define MSM_ACC_BASE IOMEM(0xF0002000)
47#define MSM_ACC_PHYS 0x02001000 45#define MSM_ACC_PHYS 0x02001000
@@ -58,16 +56,11 @@
58#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) 56#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000)
59#define MSM_SHARED_RAM_SIZE SZ_1M 57#define MSM_SHARED_RAM_SIZE SZ_1M
60 58
61#define MSM_TMR_BASE IOMEM(0xF0200000) 59#define MSM8X60_TMR_PHYS 0x02000000
62#define MSM_TMR_PHYS 0x02000000 60#define MSM8X60_TMR_SIZE SZ_4K
63#define MSM_TMR_SIZE SZ_4K
64 61
65#define MSM_TMR0_BASE IOMEM(0xF0201000) 62#define MSM8X60_TMR0_PHYS 0x02040000
66#define MSM_TMR0_PHYS 0x02040000 63#define MSM8X60_TMR0_SIZE SZ_4K
67#define MSM_TMR0_SIZE SZ_4K
68
69#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
70#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
71 64
72#define MSM_IOMMU_JPEGD_PHYS 0x07300000 65#define MSM_IOMMU_JPEGD_PHYS 0x07300000
73#define MSM_IOMMU_JPEGD_SIZE SZ_1M 66#define MSM_IOMMU_JPEGD_SIZE SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 8e24dd812139..c98c7591f3b8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -53,6 +53,13 @@
53#include "msm_iomap-7x00.h" 53#include "msm_iomap-7x00.h"
54#endif 54#endif
55 55
56#include "msm_iomap-8960.h"
56 57
58/* Virtual addressses shared across all MSM targets. */
59#define MSM_CSR_BASE IOMEM(0xE0001000)
60#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
61#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
62#define MSM_TMR_BASE IOMEM(0xF0200000)
63#define MSM_TMR0_BASE IOMEM(0xF0201000)
57 64
58#endif 65#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 06:34:37 -0500