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-rw-r--r--arch/arm/mach-msm/include/mach/board.h4
-rw-r--r--arch/arm/mach-msm/include/mach/clk.h31
-rw-r--r--arch/arm/mach-msm/include/mach/clkdev.h19
-rw-r--r--arch/arm/mach-msm/include/mach/cpu.h54
-rw-r--r--arch/arm/mach-msm/include/mach/io.h1
-rw-r--r--arch/arm/mach-msm/include/mach/iommu.h18
-rw-r--r--arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h32
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-7x30.h31
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8960.h277
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8x50.h31
-rw-r--r--arch/arm/mach-msm/include/mach/irqs.h3
-rw-r--r--arch/arm/mach-msm/include/mach/memory.h12
-rw-r--r--arch/arm/mach-msm/include/mach/mmc.h11
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x00.h16
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x30.h14
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8960.h48
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h22
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x60.h61
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h9
-rw-r--r--arch/arm/mach-msm/include/mach/sirc.h31
-rw-r--r--arch/arm/mach-msm/include/mach/smp.h30
21 files changed, 501 insertions, 254 deletions
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 6abf4a6eadc1..2ce8f1f2fc4d 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -31,7 +31,7 @@ struct msm_acpu_clock_platform_data
31 unsigned long wait_for_irq_khz; 31 unsigned long wait_for_irq_khz;
32}; 32};
33 33
34struct clk; 34struct clk_lookup;
35 35
36extern struct sys_timer msm_timer; 36extern struct sys_timer msm_timer;
37 37
@@ -41,7 +41,7 @@ void __init msm_add_devices(void);
41void __init msm_map_common_io(void); 41void __init msm_map_common_io(void);
42void __init msm_init_irq(void); 42void __init msm_init_irq(void);
43void __init msm_init_gpio(void); 43void __init msm_init_gpio(void);
44void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks); 44void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
45void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); 45void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
46int __init msm_add_sdcc(unsigned int controller, 46int __init msm_add_sdcc(unsigned int controller,
47 struct msm_mmc_platform_data *plat, 47 struct msm_mmc_platform_data *plat,
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
index c05ca40478c7..e8d38428d813 100644
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ b/arch/arm/mach-msm/include/mach/clk.h
@@ -1,30 +1,13 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * Redistribution and use in source and binary forms, with or without 3 * This program is free software; you can redistribute it and/or modify
4 * modification, are permitted provided that the following conditions are 4 * it under the terms of the GNU General Public License version 2 and
5 * met: 5 * only version 2 as published by the Free Software Foundation.
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * 6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
28 */ 11 */
29#ifndef __MACH_CLK_H 12#ifndef __MACH_CLK_H
30#define __MACH_CLK_H 13#define __MACH_CLK_H
diff --git a/arch/arm/mach-msm/include/mach/clkdev.h b/arch/arm/mach-msm/include/mach/clkdev.h
new file mode 100644
index 000000000000..f87a57b59534
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/clkdev.h
@@ -0,0 +1,19 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef __ASM_ARCH_MSM_CLKDEV_H
13#define __ASM_ARCH_MSM_CLKDEV_H
14
15struct clk;
16
17static inline int __clk_get(struct clk *clk) { return 1; }
18static inline void __clk_put(struct clk *clk) { }
19#endif
diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
new file mode 100644
index 000000000000..a9481b08d5c7
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/cpu.h
@@ -0,0 +1,54 @@
1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
19#define __ARCH_ARM_MACH_MSM_CPU_H__
20
21/* TODO: For now, only one CPU can be compiled at a time. */
22
23#define cpu_is_msm7x01() 0
24#define cpu_is_msm7x30() 0
25#define cpu_is_qsd8x50() 0
26#define cpu_is_msm8x60() 0
27#define cpu_is_msm8960() 0
28
29#ifdef CONFIG_ARCH_MSM7X00A
30# undef cpu_is_msm7x01
31# define cpu_is_msm7x01() 1
32#endif
33
34#ifdef CONFIG_ARCH_MSM7X30
35# undef cpu_is_msm7x30
36# define cpu_is_msm7x30() 1
37#endif
38
39#ifdef CONFIG_ARCH_QSD8X50
40# undef cpu_is_qsd8x50
41# define cpu_is_qsd8x50() 1
42#endif
43
44#ifdef CONFIG_ARCH_MSM8X60
45# undef cpu_is_msm8x60
46# define cpu_is_msm8x60() 1
47#endif
48
49#ifdef CONFIG_ARCH_MSM8960
50# undef cpu_is_msm8960
51# define cpu_is_msm8960() 1
52#endif
53
54#endif
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 7386e732baad..dc1b928745e9 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -29,6 +29,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
29void msm_map_qsd8x50_io(void); 29void msm_map_qsd8x50_io(void);
30void msm_map_msm7x30_io(void); 30void msm_map_msm7x30_io(void);
31void msm_map_msm8x60_io(void); 31void msm_map_msm8x60_io(void);
32void msm_map_msm8960_io(void);
32 33
33extern unsigned int msm_shared_ram_phys; 34extern unsigned int msm_shared_ram_phys;
34 35
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
index 296c0f10f230..5c7c955e6d25 100644
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -1,4 +1,4 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 4 * it under the terms of the GNU General Public License version 2 and
@@ -19,6 +19,7 @@
19#define MSM_IOMMU_H 19#define MSM_IOMMU_H
20 20
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/clk.h>
22 23
23/* Sharability attributes of MSM IOMMU mappings */ 24/* Sharability attributes of MSM IOMMU mappings */
24#define MSM_IOMMU_ATTR_NON_SH 0x0 25#define MSM_IOMMU_ATTR_NON_SH 0x0
@@ -44,14 +45,11 @@
44/** 45/**
45 * struct msm_iommu_dev - a single IOMMU hardware instance 46 * struct msm_iommu_dev - a single IOMMU hardware instance
46 * name Human-readable name given to this IOMMU HW instance 47 * name Human-readable name given to this IOMMU HW instance
47 * clk_rate Rate to set for this IOMMU's clock, if applicable to this 48 * ncb Number of context banks present on this IOMMU HW instance
48 * particular IOMMU. 0 means don't set a rate.
49 * -1 means it is an AXI clock with no valid rate
50 *
51 */ 49 */
52struct msm_iommu_dev { 50struct msm_iommu_dev {
53 const char *name; 51 const char *name;
54 int clk_rate; 52 int ncb;
55}; 53};
56 54
57/** 55/**
@@ -73,14 +71,20 @@ struct msm_iommu_ctx_dev {
73/** 71/**
74 * struct msm_iommu_drvdata - A single IOMMU hardware instance 72 * struct msm_iommu_drvdata - A single IOMMU hardware instance
75 * @base: IOMMU config port base address (VA) 73 * @base: IOMMU config port base address (VA)
74 * @ncb The number of contexts on this IOMMU
76 * @irq: Interrupt number 75 * @irq: Interrupt number
77 * 76 * @clk: The bus clock for this IOMMU hardware instance
77 * @pclk: The clock for the IOMMU bus interconnect
78 *
78 * A msm_iommu_drvdata holds the global driver data about a single piece 79 * A msm_iommu_drvdata holds the global driver data about a single piece
79 * of an IOMMU hardware instance. 80 * of an IOMMU hardware instance.
80 */ 81 */
81struct msm_iommu_drvdata { 82struct msm_iommu_drvdata {
82 void __iomem *base; 83 void __iomem *base;
83 int irq; 84 int irq;
85 int ncb;
86 struct clk *clk;
87 struct clk *pclk;
84}; 88};
85 89
86/** 90/**
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
index c2c3da9444f4..fc160101dead 100644
--- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -1,4 +1,4 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 4 * it under the terms of the GNU General Public License version 2 and
@@ -68,6 +68,7 @@ do { \
68#define FL_CACHEABLE (1 << 3) 68#define FL_CACHEABLE (1 << 3)
69#define FL_TEX0 (1 << 12) 69#define FL_TEX0 (1 << 12)
70#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) 70#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
71#define FL_NG (1 << 17)
71 72
72/* Second-level page table bits */ 73/* Second-level page table bits */
73#define SL_BASE_MASK_LARGE 0xFFFF0000 74#define SL_BASE_MASK_LARGE 0xFFFF0000
@@ -81,6 +82,7 @@ do { \
81#define SL_CACHEABLE (1 << 3) 82#define SL_CACHEABLE (1 << 3)
82#define SL_TEX0 (1 << 6) 83#define SL_TEX0 (1 << 6)
83#define SL_OFFSET(va) (((va) & 0xFF000) >> 12) 84#define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
85#define SL_NG (1 << 11)
84 86
85/* Memory type and cache policy attributes */ 87/* Memory type and cache policy attributes */
86#define MT_SO 0 88#define MT_SO 0
@@ -623,20 +625,6 @@ do { \
623#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v) 625#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
624 626
625 627
626/* V2Pxx UW UR PW PR */
627#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v)
628#define SET_V2PUW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v)
629
630#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v)
631#define SET_V2PUR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v)
632
633#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v)
634#define SET_V2PPW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v)
635
636#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v)
637#define SET_V2PPR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v)
638
639
640/* Context Register getters */ 628/* Context Register getters */
641/* ACTLR */ 629/* ACTLR */
642#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE) 630#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
@@ -824,20 +812,6 @@ do { \
824#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX) 812#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
825 813
826 814
827/* V2Pxx UW UR PW PR */
828#define GET_V2PUW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX)
829#define GET_V2PUW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA)
830
831#define GET_V2PUR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX)
832#define GET_V2PUR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA)
833
834#define GET_V2PPW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX)
835#define GET_V2PPW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA)
836
837#define GET_V2PPR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX)
838#define GET_V2PPR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA)
839
840
841/* Global Registers */ 815/* Global Registers */
842#define M2VCBR_N (0xFF000) 816#define M2VCBR_N (0xFF000)
843#define CBACR_N (0xFF800) 817#define CBACR_N (0xFF800)
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h
index 67c5396514fe..1f15902655fd 100644
--- a/arch/arm/mach-msm/include/mach/irqs-7x30.h
+++ b/arch/arm/mach-msm/include/mach/irqs-7x30.h
@@ -1,30 +1,13 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * Redistribution and use in source and binary forms, with or without 3 * This program is free software; you can redistribute it and/or modify
4 * modification, are permitted provided that the following conditions are 4 * it under the terms of the GNU General Public License version 2 and
5 * met: 5 * only version 2 as published by the Free Software Foundation.
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * 6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
28 */ 11 */
29 12
30#ifndef __ASM_ARCH_MSM_IRQS_7X30_H 13#ifndef __ASM_ARCH_MSM_IRQS_7X30_H
diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
new file mode 100644
index 000000000000..81ab2a6792bd
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -0,0 +1,277 @@
1/* Copyright (c) 2011 Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_IRQS_8960_H
14#define __ASM_ARCH_MSM_IRQS_8960_H
15
16/* MSM ACPU Interrupt Numbers */
17
18/* 0-15: STI/SGI (software triggered/generated interrupts)
19 16-31: PPI (private peripheral interrupts)
20 32+: SPI (shared peripheral interrupts) */
21
22#define GIC_PPI_START 16
23#define GIC_SPI_START 32
24
25#define INT_VGIC (GIC_PPI_START + 0)
26#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
27#define INT_GP_TIMER_EXP (GIC_PPI_START + 2)
28#define INT_GP_TIMER2_EXP (GIC_PPI_START + 3)
29#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
30#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 5)
31#define AVS_SVICINT (GIC_PPI_START + 6)
32#define AVS_SVICINTSWDONE (GIC_PPI_START + 7)
33#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 8)
34#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 9)
35#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 10)
36#define SC_AVSCPUXDOWN (GIC_PPI_START + 11)
37#define SC_AVSCPUXUP (GIC_PPI_START + 12)
38#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 13)
39#define SC_SICCPUXEXTFAULTIRPTREQ (GIC_PPI_START + 14)
40/* PPI 15 is unused */
41
42#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
43#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
44#define SC_SICL2PERFMONIRPTREQ (GIC_SPI_START + 2)
45#define SC_SICAGCIRPTREQ (GIC_SPI_START + 3)
46#define TLMM_APCC_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
47#define TLMM_APCC_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
48#define TLMM_APCC_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
49#define TLMM_APCC_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
50#define TLMM_APCC_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
51#define TLMM_APCC_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
52#define TLMM_APCC_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
53#define TLMM_APCC_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
54#define TLMM_APCC_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
55#define TLMM_APCC_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
56#define PM8921_SEC_IRQ_103 (GIC_SPI_START + 14)
57#define PM8018_SEC_IRQ_106 (GIC_SPI_START + 15)
58#define TLMM_APCC_SUMMARY_IRQ (GIC_SPI_START + 16)
59#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
60#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
61#define RPM_APCC_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
62#define RPM_APCC_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
63#define RPM_APCC_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
64#define RPM_APCC_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
65#define RPM_APCC_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
66#define RPM_APCC_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
67#define RPM_APCC_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
68#define RPM_APCC_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
69#define SSBI2_2_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 27)
70#define SSBI2_2_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 28)
71#define SSBI2_1_SC_CPU0_SECURE_IRQ (GIC_SPI_START + 29)
72#define SSBI2_1_SC_CPU0_NON_SECURE_IRQ (GIC_SPI_START + 30)
73#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
74#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
75#define SLIMBUS0_CORE_EE1_IRQ (GIC_SPI_START + 33)
76#define SLIMBUS0_BAM_EE1_IRQ (GIC_SPI_START + 34)
77#define Q6FW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 35)
78#define Q6SW_WDOG_EXPIRED_IRQ (GIC_SPI_START + 36)
79#define MSS_TO_APPS_IRQ_0 (GIC_SPI_START + 37)
80#define MSS_TO_APPS_IRQ_1 (GIC_SPI_START + 38)
81#define MSS_TO_APPS_IRQ_2 (GIC_SPI_START + 39)
82#define MSS_TO_APPS_IRQ_3 (GIC_SPI_START + 40)
83#define MSS_TO_APPS_IRQ_4 (GIC_SPI_START + 41)
84#define MSS_TO_APPS_IRQ_5 (GIC_SPI_START + 42)
85#define MSS_TO_APPS_IRQ_6 (GIC_SPI_START + 43)
86#define MSS_TO_APPS_IRQ_7 (GIC_SPI_START + 44)
87#define MSS_TO_APPS_IRQ_8 (GIC_SPI_START + 45)
88#define MSS_TO_APPS_IRQ_9 (GIC_SPI_START + 46)
89#define VPE_IRQ (GIC_SPI_START + 47)
90#define VFE_IRQ (GIC_SPI_START + 48)
91#define VCODEC_IRQ (GIC_SPI_START + 49)
92#define TV_ENC_IRQ (GIC_SPI_START + 50)
93#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
94#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
95#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
96#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
97#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
98#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
99#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
100#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
101#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
102#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
103#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
104#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
105#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
106#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
107#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
108#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
109#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
110#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
111#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
112#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
113#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
114#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
115#define ROT_IRQ (GIC_SPI_START + 73)
116#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
117#define MDP_IRQ (GIC_SPI_START + 75)
118#define JPEGD_IRQ (GIC_SPI_START + 76)
119#define JPEG_IRQ (GIC_SPI_START + 77)
120#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
121#define HDMI_IRQ (GIC_SPI_START + 79)
122#define GFX3D_IRQ (GIC_SPI_START + 80)
123#define GFX2D0_IRQ (GIC_SPI_START + 81)
124#define DSI1_IRQ (GIC_SPI_START + 82)
125#define CSI_1_IRQ (GIC_SPI_START + 83)
126#define CSI_0_IRQ (GIC_SPI_START + 84)
127#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
128#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
129#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
130#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
131#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
132#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
133#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
134#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
135#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
136#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
137#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
138#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
139#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
140#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
141#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
142#define USB1_HS_IRQ (GIC_SPI_START + 100)
143#define SDC4_IRQ_0 (GIC_SPI_START + 101)
144#define SDC3_IRQ_0 (GIC_SPI_START + 102)
145#define SDC2_IRQ_0 (GIC_SPI_START + 103)
146#define SDC1_IRQ_0 (GIC_SPI_START + 104)
147#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
148#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
149#define SPS_MTI_0 (GIC_SPI_START + 107)
150#define SPS_MTI_1 (GIC_SPI_START + 108)
151#define SPS_MTI_2 (GIC_SPI_START + 109)
152#define SPS_MTI_3 (GIC_SPI_START + 110)
153#define SPS_MTI_4 (GIC_SPI_START + 111)
154#define SPS_MTI_5 (GIC_SPI_START + 112)
155#define SPS_MTI_6 (GIC_SPI_START + 113)
156#define SPS_MTI_7 (GIC_SPI_START + 114)
157#define SPS_MTI_8 (GIC_SPI_START + 115)
158#define SPS_MTI_9 (GIC_SPI_START + 116)
159#define SPS_MTI_10 (GIC_SPI_START + 117)
160#define SPS_MTI_11 (GIC_SPI_START + 118)
161#define SPS_MTI_12 (GIC_SPI_START + 119)
162#define SPS_MTI_13 (GIC_SPI_START + 120)
163#define SPS_MTI_14 (GIC_SPI_START + 121)
164#define SPS_MTI_15 (GIC_SPI_START + 122)
165#define SPS_MTI_16 (GIC_SPI_START + 123)
166#define SPS_MTI_17 (GIC_SPI_START + 124)
167#define SPS_MTI_18 (GIC_SPI_START + 125)
168#define SPS_MTI_19 (GIC_SPI_START + 126)
169#define SPS_MTI_20 (GIC_SPI_START + 127)
170#define SPS_MTI_21 (GIC_SPI_START + 128)
171#define SPS_MTI_22 (GIC_SPI_START + 129)
172#define SPS_MTI_23 (GIC_SPI_START + 130)
173#define SPS_MTI_24 (GIC_SPI_START + 131)
174#define SPS_MTI_25 (GIC_SPI_START + 132)
175#define SPS_MTI_26 (GIC_SPI_START + 133)
176#define SPS_MTI_27 (GIC_SPI_START + 134)
177#define SPS_MTI_28 (GIC_SPI_START + 135)
178#define SPS_MTI_29 (GIC_SPI_START + 136)
179#define SPS_MTI_30 (GIC_SPI_START + 137)
180#define SPS_MTI_31 (GIC_SPI_START + 138)
181#define CSIPHY_4LN_IRQ (GIC_SPI_START + 139)
182#define CSIPHY_2LN_IRQ (GIC_SPI_START + 140)
183#define USB2_IRQ (GIC_SPI_START + 141)
184#define USB1_IRQ (GIC_SPI_START + 142)
185#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
186#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
187#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
188#define GSBI1_UARTDM_IRQ (GIC_SPI_START + 146)
189#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
190#define GSBI2_UARTDM_IRQ (GIC_SPI_START + 148)
191#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
192#define GSBI3_UARTDM_IRQ (GIC_SPI_START + 150)
193#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
194#define GSBI4_UARTDM_IRQ (GIC_SPI_START + 152)
195#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
196#define GSBI5_UARTDM_IRQ (GIC_SPI_START + 154)
197#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
198#define GSBI6_UARTDM_IRQ (GIC_SPI_START + 156)
199#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
200#define GSBI7_UARTDM_IRQ (GIC_SPI_START + 158)
201#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
202#define GSBI8_UARTDM_IRQ (GIC_SPI_START + 160)
203#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
204#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
205#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
206#define TSIF2_IRQ (GIC_SPI_START + 164)
207#define TSIF1_IRQ (GIC_SPI_START + 165)
208#define DSI2_IRQ (GIC_SPI_START + 166)
209#define ISPIF_IRQ (GIC_SPI_START + 167)
210#define MSMC_SC_SEC_TMR_IRQ (GIC_SPI_START + 168)
211#define MSMC_SC_SEC_WDOG_BARK_IRQ (GIC_SPI_START + 169)
212#define INT_ADM0_SCSS_0_IRQ (GIC_SPI_START + 170)
213#define INT_ADM0_SCSS_1_IRQ (GIC_SPI_START + 171)
214#define INT_ADM0_SCSS_2_IRQ (GIC_SPI_START + 172)
215#define INT_ADM0_SCSS_3_IRQ (GIC_SPI_START + 173)
216#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
217#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
218#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
219#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
220#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
221#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
222#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
223#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
224#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
225#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
226#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
227#define HSDDRX_EBI1CH0_IRQ (GIC_SPI_START + 185)
228#define HSDDRX_EBI1CH1_IRQ (GIC_SPI_START + 186)
229#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
230#define SDC5_IRQ_0 (GIC_SPI_START + 188)
231#define GSBI9_UARTDM_IRQ (GIC_SPI_START + 189)
232#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
233#define GSBI10_UARTDM_IRQ (GIC_SPI_START + 191)
234#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
235#define GSBI11_UARTDM_IRQ (GIC_SPI_START + 193)
236#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
237#define GSBI12_UARTDM_IRQ (GIC_SPI_START + 195)
238#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
239#define RIVA_APSS_LTECOEX_IRQ (GIC_SPI_START + 197)
240#define RIVA_APSS_SPARE_IRQ (GIC_SPI_START + 198)
241#define RIVA_APSS_WDOG_BITE_RESET_RDY_IRQ (GIC_SPI_START + 199)
242#define RIVA_ASS_RESET_DONE_IRQ (GIC_SPI_START + 200)
243#define RIVA_APSS_ASIC_IRQ (GIC_SPI_START + 201)
244#define RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ (GIC_SPI_START + 202)
245#define RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ (GIC_SPI_START + 203)
246#define RIVA_APPS_WLAM_SMSM_IRQ (GIC_SPI_START + 204)
247#define RIVA_APPS_LOG_CTRL_IRQ (GIC_SPI_START + 205)
248#define RIVA_APPS_FM_CTRL_IRQ (GIC_SPI_START + 206)
249#define RIVA_APPS_HCI_IRQ (GIC_SPI_START + 207)
250#define RIVA_APPS_WLAN_CTRL_IRQ (GIC_SPI_START + 208)
251#define A2_BAM_IRQ (GIC_SPI_START + 209)
252#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
253#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
254#define GFX2D1_IRQ (GIC_SPI_START + 212)
255#define PPSS_WDOG_TIMER_IRQ (GIC_SPI_START + 213)
256#define SPS_SLIMBUS_CORE_EE0_IRQ (GIC_SPI_START + 214)
257#define SPS_SLIMBUS_BAM_EE0_IRQ (GIC_SPI_START + 215)
258#define QDSS_ETB_IRQ (GIC_SPI_START + 216)
259#define QDSS_CTI2KPSS_CPU1_IRQ (GIC_SPI_START + 217)
260#define QDSS_CTI2KPSS_CPU0_IRQ (GIC_SPI_START + 218)
261#define TLMM_APCC_DIR_CONN_IRQ_16 (GIC_SPI_START + 219)
262#define TLMM_APCC_DIR_CONN_IRQ_17 (GIC_SPI_START + 220)
263#define TLMM_APCC_DIR_CONN_IRQ_18 (GIC_SPI_START + 221)
264#define TLMM_APCC_DIR_CONN_IRQ_19 (GIC_SPI_START + 222)
265#define TLMM_APCC_DIR_CONN_IRQ_20 (GIC_SPI_START + 223)
266#define TLMM_APCC_DIR_CONN_IRQ_21 (GIC_SPI_START + 224)
267#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
268#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)
269
270/* For now, use the maximum number of interrupts until a pending GIC issue
271 * is sorted out */
272#define NR_MSM_IRQS 1020
273#define NR_BOARD_IRQS 0
274#define NR_GPIO_IRQS 0
275
276#endif
277
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h
index de3d8fe24e4e..26adbe0e9406 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8x50.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8x50.h
@@ -1,30 +1,13 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * Redistribution and use in source and binary forms, with or without 3 * This program is free software; you can redistribute it and/or modify
4 * modification, are permitted provided that the following conditions are 4 * it under the terms of the GNU General Public License version 2 and
5 * met: 5 * only version 2 as published by the Free Software Foundation.
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * 6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
28 */ 11 */
29 12
30#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H 13#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 8679a4564744..3cd78b165abb 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -26,6 +26,9 @@
26#include "sirc.h" 26#include "sirc.h"
27#elif defined(CONFIG_ARCH_MSM8X60) 27#elif defined(CONFIG_ARCH_MSM8X60)
28#include "irqs-8x60.h" 28#include "irqs-8x60.h"
29#elif defined(CONFIG_ARCH_MSM8960)
30/* TODO: Make these not generic. */
31#include "irqs-8960.h"
29#elif defined(CONFIG_ARCH_MSM_ARM11) 32#elif defined(CONFIG_ARCH_MSM_ARM11)
30#include "irqs-7x00.h" 33#include "irqs-7x00.h"
31#else 34#else
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 070e17d237f1..f2f8d299ba95 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -18,15 +18,17 @@
18 18
19/* physical offset of RAM */ 19/* physical offset of RAM */
20#if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A) 20#if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A)
21#define PHYS_OFFSET UL(0x00000000) 21#define PLAT_PHYS_OFFSET UL(0x00000000)
22#elif defined(CONFIG_ARCH_QSD8X50) 22#elif defined(CONFIG_ARCH_QSD8X50)
23#define PHYS_OFFSET UL(0x20000000) 23#define PLAT_PHYS_OFFSET UL(0x20000000)
24#elif defined(CONFIG_ARCH_MSM7X30) 24#elif defined(CONFIG_ARCH_MSM7X30)
25#define PHYS_OFFSET UL(0x00200000) 25#define PLAT_PHYS_OFFSET UL(0x00200000)
26#elif defined(CONFIG_ARCH_MSM8X60) 26#elif defined(CONFIG_ARCH_MSM8X60)
27#define PHYS_OFFSET UL(0x40200000) 27#define PLAT_PHYS_OFFSET UL(0x40200000)
28#elif defined(CONFIG_ARCH_MSM8960)
29#define PLAT_PHYS_OFFSET UL(0x40200000)
28#else 30#else
29#define PHYS_OFFSET UL(0x10000000) 31#define PLAT_PHYS_OFFSET UL(0x10000000)
30#endif 32#endif
31 33
32#endif 34#endif
diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h
index d54b6b086cff..5631b51cec46 100644
--- a/arch/arm/mach-msm/include/mach/mmc.h
+++ b/arch/arm/mach-msm/include/mach/mmc.h
@@ -15,12 +15,23 @@ struct embedded_sdio_data {
15 int num_funcs; 15 int num_funcs;
16}; 16};
17 17
18struct msm_mmc_gpio {
19 unsigned no;
20 const char *name;
21};
22
23struct msm_mmc_gpio_data {
24 struct msm_mmc_gpio *gpio;
25 u8 size;
26};
27
18struct msm_mmc_platform_data { 28struct msm_mmc_platform_data {
19 unsigned int ocr_mask; /* available voltages */ 29 unsigned int ocr_mask; /* available voltages */
20 u32 (*translate_vdd)(struct device *, unsigned int); 30 u32 (*translate_vdd)(struct device *, unsigned int);
21 unsigned int (*status)(struct device *); 31 unsigned int (*status)(struct device *);
22 struct embedded_sdio_data *embedded_sdio; 32 struct embedded_sdio_data *embedded_sdio;
23 int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); 33 int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
34 struct msm_mmc_gpio_data *gpio_data;
24}; 35};
25 36
26#endif 37#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index cfff0e74f128..8f99d97615a0 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -1,6 +1,7 @@
1/* arch/arm/mach-msm/include/mach/msm_iomap.h 1/* arch/arm/mach-msm/include/mach/msm_iomap.h
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 5 * Author: Brian Swetland <swetland@google.com>
5 * 6 *
6 * This software is licensed under the terms of the GNU General Public 7 * This software is licensed under the terms of the GNU General Public
@@ -47,13 +48,8 @@
47#define MSM_VIC_PHYS 0xC0000000 48#define MSM_VIC_PHYS 0xC0000000
48#define MSM_VIC_SIZE SZ_4K 49#define MSM_VIC_SIZE SZ_4K
49 50
50#define MSM_CSR_BASE IOMEM(0xE0001000) 51#define MSM7X00_CSR_PHYS 0xC0100000
51#define MSM_CSR_PHYS 0xC0100000 52#define MSM7X00_CSR_SIZE SZ_4K
52#define MSM_CSR_SIZE SZ_4K
53
54#define MSM_GPT_PHYS MSM_CSR_PHYS
55#define MSM_GPT_BASE MSM_CSR_BASE
56#define MSM_GPT_SIZE SZ_4K
57 53
58#define MSM_DMOV_BASE IOMEM(0xE0002000) 54#define MSM_DMOV_BASE IOMEM(0xE0002000)
59#define MSM_DMOV_PHYS 0xA9700000 55#define MSM_DMOV_PHYS 0xA9700000
@@ -130,10 +126,4 @@
130#define MSM_AD5_SIZE (SZ_1M*13) 126#define MSM_AD5_SIZE (SZ_1M*13)
131 127
132 128
133#if defined(CONFIG_ARCH_MSM7X30)
134#define MSM_GCC_BASE IOMEM(0xF8009000)
135#define MSM_GCC_PHYS 0xC0182000
136#define MSM_GCC_SIZE SZ_4K
137#endif
138
139#endif 129#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 0fd7b68ca114..4d84be15955e 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
39#define MSM_VIC_PHYS 0xC0080000 39#define MSM_VIC_PHYS 0xC0080000
40#define MSM_VIC_SIZE SZ_4K 40#define MSM_VIC_SIZE SZ_4K
41 41
42#define MSM_CSR_BASE IOMEM(0xE0001000) 42#define MSM7X30_CSR_PHYS 0xC0100000
43#define MSM_CSR_PHYS 0xC0100000 43#define MSM7X30_CSR_SIZE SZ_4K
44#define MSM_CSR_SIZE SZ_4K
45
46#define MSM_TMR_PHYS MSM_CSR_PHYS
47#define MSM_TMR_BASE MSM_CSR_BASE
48#define MSM_TMR_SIZE SZ_4K
49
50#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
51#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
52 44
53#define MSM_DMOV_BASE IOMEM(0xE0002000) 45#define MSM_DMOV_BASE IOMEM(0xE0002000)
54#define MSM_DMOV_PHYS 0xAC400000 46#define MSM_DMOV_PHYS 0xAC400000
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
new file mode 100644
index 000000000000..3c9d9602a318
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
24#define __ASM_ARCH_MSM_IOMAP_8960_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * If you add or remove entries here, you'll want to edit the
30 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
31 * changes.
32 *
33 */
34
35
36#define MSM8960_QGIC_DIST_PHYS 0x02000000
37#define MSM8960_QGIC_DIST_SIZE SZ_4K
38
39#define MSM8960_QGIC_CPU_PHYS 0x02002000
40#define MSM8960_QGIC_CPU_SIZE SZ_4K
41
42#define MSM8960_TMR_PHYS 0x0200A000
43#define MSM8960_TMR_SIZE SZ_4K
44
45#define MSM8960_TMR0_PHYS 0x0208A000
46#define MSM8960_TMR0_SIZE SZ_4K
47
48#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index acc819eb76e5..d4143201999f 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -39,16 +39,8 @@
39#define MSM_VIC_PHYS 0xAC000000 39#define MSM_VIC_PHYS 0xAC000000
40#define MSM_VIC_SIZE SZ_4K 40#define MSM_VIC_SIZE SZ_4K
41 41
42#define MSM_CSR_BASE IOMEM(0xE0001000) 42#define QSD8X50_CSR_PHYS 0xAC100000
43#define MSM_CSR_PHYS 0xAC100000 43#define QSD8X50_CSR_SIZE SZ_4K
44#define MSM_CSR_SIZE SZ_4K
45
46#define MSM_TMR_PHYS MSM_CSR_PHYS
47#define MSM_TMR_BASE MSM_CSR_BASE
48#define MSM_TMR_SIZE SZ_4K
49
50#define MSM_GPT_BASE MSM_TMR_BASE
51#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10)
52 44
53#define MSM_DMOV_BASE IOMEM(0xE0002000) 45#define MSM_DMOV_BASE IOMEM(0xE0002000)
54#define MSM_DMOV_PHYS 0xA9700000 46#define MSM_DMOV_PHYS 0xA9700000
@@ -132,16 +124,16 @@
132#define MSM_UART2DM_PHYS 0xA0900000 124#define MSM_UART2DM_PHYS 0xA0900000
133 125
134 126
135#define MSM_SDC1_PHYS 0xA0400000 127#define MSM_SDC1_PHYS 0xA0300000
136#define MSM_SDC1_SIZE SZ_4K 128#define MSM_SDC1_SIZE SZ_4K
137 129
138#define MSM_SDC2_PHYS 0xA0500000 130#define MSM_SDC2_PHYS 0xA0400000
139#define MSM_SDC2_SIZE SZ_4K 131#define MSM_SDC2_SIZE SZ_4K
140 132
141#define MSM_SDC3_PHYS 0xA0600000 133#define MSM_SDC3_PHYS 0xA0500000
142#define MSM_SDC3_SIZE SZ_4K 134#define MSM_SDC3_SIZE SZ_4K
143 135
144#define MSM_SDC4_PHYS 0xA0700000 136#define MSM_SDC4_PHYS 0xA0600000
145#define MSM_SDC4_SIZE SZ_4K 137#define MSM_SDC4_SIZE SZ_4K
146 138
147#endif 139#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index a54e33b0882e..3b19b8f244b8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -35,13 +35,11 @@
35 * 35 *
36 */ 36 */
37 37
38#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000) 38#define MSM8X60_QGIC_DIST_PHYS 0x02080000
39#define MSM_QGIC_DIST_PHYS 0x02080000 39#define MSM8X60_QGIC_DIST_SIZE SZ_4K
40#define MSM_QGIC_DIST_SIZE SZ_4K
41 40
42#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) 41#define MSM8X60_QGIC_CPU_PHYS 0x02081000
43#define MSM_QGIC_CPU_PHYS 0x02081000 42#define MSM8X60_QGIC_CPU_SIZE SZ_4K
44#define MSM_QGIC_CPU_SIZE SZ_4K
45 43
46#define MSM_ACC_BASE IOMEM(0xF0002000) 44#define MSM_ACC_BASE IOMEM(0xF0002000)
47#define MSM_ACC_PHYS 0x02001000 45#define MSM_ACC_PHYS 0x02001000
@@ -58,51 +56,10 @@
58#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000) 56#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000)
59#define MSM_SHARED_RAM_SIZE SZ_1M 57#define MSM_SHARED_RAM_SIZE SZ_1M
60 58
61#define MSM_TMR_BASE IOMEM(0xF0200000) 59#define MSM8X60_TMR_PHYS 0x02000000
62#define MSM_TMR_PHYS 0x02000000 60#define MSM8X60_TMR_SIZE SZ_4K
63#define MSM_TMR_SIZE SZ_4K
64 61
65#define MSM_TMR0_BASE IOMEM(0xF0201000) 62#define MSM8X60_TMR0_PHYS 0x02040000
66#define MSM_TMR0_PHYS 0x02040000 63#define MSM8X60_TMR0_SIZE SZ_4K
67#define MSM_TMR0_SIZE SZ_4K
68
69#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
70#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
71
72#define MSM_IOMMU_JPEGD_PHYS 0x07300000
73#define MSM_IOMMU_JPEGD_SIZE SZ_1M
74
75#define MSM_IOMMU_VPE_PHYS 0x07400000
76#define MSM_IOMMU_VPE_SIZE SZ_1M
77
78#define MSM_IOMMU_MDP0_PHYS 0x07500000
79#define MSM_IOMMU_MDP0_SIZE SZ_1M
80
81#define MSM_IOMMU_MDP1_PHYS 0x07600000
82#define MSM_IOMMU_MDP1_SIZE SZ_1M
83
84#define MSM_IOMMU_ROT_PHYS 0x07700000
85#define MSM_IOMMU_ROT_SIZE SZ_1M
86
87#define MSM_IOMMU_IJPEG_PHYS 0x07800000
88#define MSM_IOMMU_IJPEG_SIZE SZ_1M
89
90#define MSM_IOMMU_VFE_PHYS 0x07900000
91#define MSM_IOMMU_VFE_SIZE SZ_1M
92
93#define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000
94#define MSM_IOMMU_VCODEC_A_SIZE SZ_1M
95
96#define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000
97#define MSM_IOMMU_VCODEC_B_SIZE SZ_1M
98
99#define MSM_IOMMU_GFX3D_PHYS 0x07C00000
100#define MSM_IOMMU_GFX3D_SIZE SZ_1M
101
102#define MSM_IOMMU_GFX2D0_PHYS 0x07D00000
103#define MSM_IOMMU_GFX2D0_SIZE SZ_1M
104
105#define MSM_IOMMU_GFX2D1_PHYS 0x07E00000
106#define MSM_IOMMU_GFX2D1_SIZE SZ_1M
107 64
108#endif 65#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 8e24dd812139..c98c7591f3b8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -53,6 +53,13 @@
53#include "msm_iomap-7x00.h" 53#include "msm_iomap-7x00.h"
54#endif 54#endif
55 55
56#include "msm_iomap-8960.h"
56 57
58/* Virtual addressses shared across all MSM targets. */
59#define MSM_CSR_BASE IOMEM(0xE0001000)
60#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
61#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
62#define MSM_TMR_BASE IOMEM(0xF0200000)
63#define MSM_TMR0_BASE IOMEM(0xF0201000)
57 64
58#endif 65#endif
diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h
index 7281337ee28d..ef55868a5b8a 100644
--- a/arch/arm/mach-msm/include/mach/sirc.h
+++ b/arch/arm/mach-msm/include/mach/sirc.h
@@ -1,30 +1,13 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * Redistribution and use in source and binary forms, with or without 3 * This program is free software; you can redistribute it and/or modify
4 * modification, are permitted provided that the following conditions are 4 * it under the terms of the GNU General Public License version 2 and
5 * met: 5 * only version 2 as published by the Free Software Foundation.
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * 6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
28 */ 11 */
29 12
30#ifndef __ASM_ARCH_MSM_SIRC_H 13#ifndef __ASM_ARCH_MSM_SIRC_H
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
index a95f7b9efe31..3c01000ecc80 100644
--- a/arch/arm/mach-msm/include/mach/smp.h
+++ b/arch/arm/mach-msm/include/mach/smp.h
@@ -1,29 +1,13 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * Redistribution and use in source and binary forms, with or without 3 * This program is free software; you can redistribute it and/or modify
4 * modification, are permitted provided that the following conditions are met: 4 * it under the terms of the GNU General Public License version 2 and
5 * * Redistributions of source code must retain the above copyright 5 * only version 2 as published by the Free Software Foundation.
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Code Aurora nor
11 * the names of its contributors may be used to endorse or promote
12 * products derived from this software without specific prior written
13 * permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
19 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * 6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
27 */ 11 */
28 12
29#ifndef __ASM_ARCH_MSM_SMP_H 13#ifndef __ASM_ARCH_MSM_SMP_H
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 01:12:38 -0500