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-rw-r--r--arch/arm/mach-mmp/Makefile1
-rw-r--r--arch/arm/mach-mmp/clock-pxa168.c91
-rw-r--r--arch/arm/mach-mmp/common.h1
-rw-r--r--arch/arm/mach-mmp/pxa168.c58
4 files changed, 98 insertions, 53 deletions
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 815c3e74c24a..bb63f86185a9 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o
11 11
12ifeq ($(CONFIG_COMMON_CLK), ) 12ifeq ($(CONFIG_COMMON_CLK), )
13obj-y += clock.o 13obj-y += clock.o
14obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o
14endif 15endif
15ifeq ($(CONFIG_PM),y) 16ifeq ($(CONFIG_PM),y)
16obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o 17obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
new file mode 100644
index 000000000000..5e6c18ccebd4
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -0,0 +1,91 @@
1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/list.h>
5#include <linux/io.h>
6#include <linux/clk.h>
7
8#include <mach/addr-map.h>
9
10#include "common.h"
11#include "clock.h"
12
13/*
14 * APB clock register offsets for PXA168
15 */
16#define APBC_UART1 APBC_REG(0x000)
17#define APBC_UART2 APBC_REG(0x004)
18#define APBC_GPIO APBC_REG(0x008)
19#define APBC_PWM1 APBC_REG(0x00c)
20#define APBC_PWM2 APBC_REG(0x010)
21#define APBC_PWM3 APBC_REG(0x014)
22#define APBC_PWM4 APBC_REG(0x018)
23#define APBC_RTC APBC_REG(0x028)
24#define APBC_TWSI0 APBC_REG(0x02c)
25#define APBC_KPC APBC_REG(0x030)
26#define APBC_TWSI1 APBC_REG(0x06c)
27#define APBC_UART3 APBC_REG(0x070)
28#define APBC_SSP1 APBC_REG(0x81c)
29#define APBC_SSP2 APBC_REG(0x820)
30#define APBC_SSP3 APBC_REG(0x84c)
31#define APBC_SSP4 APBC_REG(0x858)
32#define APBC_SSP5 APBC_REG(0x85c)
33
34#define APMU_NAND APMU_REG(0x060)
35#define APMU_LCD APMU_REG(0x04c)
36#define APMU_ETH APMU_REG(0x0fc)
37#define APMU_USB APMU_REG(0x05c)
38
39/* APB peripheral clocks */
40static APBC_CLK(uart1, UART1, 1, 14745600);
41static APBC_CLK(uart2, UART2, 1, 14745600);
42static APBC_CLK(uart3, UART3, 1, 14745600);
43static APBC_CLK(twsi0, TWSI0, 1, 33000000);
44static APBC_CLK(twsi1, TWSI1, 1, 33000000);
45static APBC_CLK(pwm1, PWM1, 1, 13000000);
46static APBC_CLK(pwm2, PWM2, 1, 13000000);
47static APBC_CLK(pwm3, PWM3, 1, 13000000);
48static APBC_CLK(pwm4, PWM4, 1, 13000000);
49static APBC_CLK(ssp1, SSP1, 4, 0);
50static APBC_CLK(ssp2, SSP2, 4, 0);
51static APBC_CLK(ssp3, SSP3, 4, 0);
52static APBC_CLK(ssp4, SSP4, 4, 0);
53static APBC_CLK(ssp5, SSP5, 4, 0);
54static APBC_CLK(gpio, GPIO, 0, 13000000);
55static APBC_CLK(keypad, KPC, 0, 32000);
56static APBC_CLK(rtc, RTC, 8, 32768);
57
58static APMU_CLK(nand, NAND, 0x19b, 156000000);
59static APMU_CLK(lcd, LCD, 0x7f, 312000000);
60static APMU_CLK(eth, ETH, 0x09, 0);
61static APMU_CLK(usb, USB, 0x12, 0);
62
63/* device and clock bindings */
64static struct clk_lookup pxa168_clkregs[] = {
65 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
66 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
67 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
68 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
69 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
70 INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
71 INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
72 INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
73 INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
74 INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
75 INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
76 INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
77 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
78 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
79 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
80 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
81 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
82 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
83 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
84 INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
85 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
86};
87
88void __init pxa168_clk_init(void)
89{
90 clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
91}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 1c9d6c1ea97a..e47f73f55c45 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -7,3 +7,4 @@ extern void timer_init(int irq);
7extern void __init icu_init_irq(void); 7extern void __init icu_init_irq(void);
8extern void __init mmp_map_io(void); 8extern void __init mmp_map_io(void);
9extern void mmp_restart(char, const char *); 9extern void mmp_restart(char, const char *);
10extern void __init pxa168_clk_init(void);
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 62d787c34475..b7f074f15498 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -18,8 +18,8 @@
18 18
19#include <asm/mach/time.h> 19#include <asm/mach/time.h>
20#include <asm/system_misc.h> 20#include <asm/system_misc.h>
21#include <mach/addr-map.h>
22#include <mach/cputype.h> 21#include <mach/cputype.h>
22#include <mach/addr-map.h>
23#include <mach/regs-apbc.h> 23#include <mach/regs-apbc.h>
24#include <mach/regs-apmu.h> 24#include <mach/regs-apmu.h>
25#include <mach/irqs.h> 25#include <mach/irqs.h>
@@ -50,62 +50,13 @@ void __init pxa168_init_irq(void)
50 icu_init_irq(); 50 icu_init_irq();
51} 51}
52 52
53/* APB peripheral clocks */
54static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
55static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
56static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
57static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
58static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
59static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
60static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
61static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
62static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
63static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
64static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
65static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
66static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
67static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
68static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
69static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
70static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
71
72static APMU_CLK(nand, NAND, 0x19b, 156000000);
73static APMU_CLK(lcd, LCD, 0x7f, 312000000);
74static APMU_CLK(eth, ETH, 0x09, 0);
75static APMU_CLK(usb, USB, 0x12, 0);
76
77/* device and clock bindings */
78static struct clk_lookup pxa168_clkregs[] = {
79 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
80 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
81 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
82 INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
83 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
84 INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
85 INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
86 INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
87 INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
88 INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
89 INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
90 INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
91 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
92 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
93 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
94 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
95 INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
96 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
97 INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
98 INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
99 INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
100};
101
102static int __init pxa168_init(void) 53static int __init pxa168_init(void)
103{ 54{
104 if (cpu_is_pxa168()) { 55 if (cpu_is_pxa168()) {
105 mfp_init_base(MFPR_VIRT_BASE); 56 mfp_init_base(MFPR_VIRT_BASE);
106 mfp_init_addr(pxa168_mfp_addr_map); 57 mfp_init_addr(pxa168_mfp_addr_map);
107 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); 58 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
108 clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); 59 pxa168_clk_init();
109 } 60 }
110 61
111 return 0; 62 return 0;
@@ -114,6 +65,7 @@ postcore_initcall(pxa168_init);
114 65
115/* system timer - clock enabled, 3.25MHz */ 66/* system timer - clock enabled, 3.25MHz */
116#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) 67#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
68#define APBC_TIMERS APBC_REG(0x34)
117 69
118static void __init pxa168_timer_init(void) 70static void __init pxa168_timer_init(void)
119{ 71{
@@ -121,10 +73,10 @@ static void __init pxa168_timer_init(void)
121 * ourselves instead of using clk_* API. Clock rate is defined 73 * ourselves instead of using clk_* API. Clock rate is defined
122 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running 74 * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
123 */ 75 */
124 __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); 76 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
125 77
126 /* 3.25MHz, bus/functional clock enabled, release reset */ 78 /* 3.25MHz, bus/functional clock enabled, release reset */
127 __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); 79 __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
128 80
129 timer_init(IRQ_PXA168_TIMER1); 81 timer_init(IRQ_PXA168_TIMER1);
130} 82}
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-10 11:22:37 -0400