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-rw-r--r--arch/arm/mach-kirkwood/addr-map.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168fc699..8d03bcef5182 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
31#define ATTR_DEV_CS0 0x3e 31#define ATTR_DEV_CS0 0x3e
32#define ATTR_PCIE_IO 0xe0 32#define ATTR_PCIE_IO 0xe0
33#define ATTR_PCIE_MEM 0xe8 33#define ATTR_PCIE_MEM 0xe8
34#define ATTR_PCIE1_IO 0xd0
35#define ATTR_PCIE1_MEM 0xd8
34#define ATTR_SRAM 0x01 36#define ATTR_SRAM 0x01
35 37
36/* 38/*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
106 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE); 108 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
107 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE, 109 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
108 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE); 110 TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
111 setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
112 TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
113 setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
114 TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
109 115
110 /* 116 /*
111 * Setup window for NAND controller. 117 * Setup window for NAND controller.
112 */ 118 */
113 setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE, 119 setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
114 TARGET_DEV_BUS, ATTR_DEV_NAND, -1); 120 TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
115 121
116 /* 122 /*
117 * Setup window for SRAM. 123 * Setup window for SRAM.
118 */ 124 */
119 setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE, 125 setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
120 TARGET_SRAM, ATTR_SRAM, -1); 126 TARGET_SRAM, ATTR_SRAM, -1);
121 127
122 /* 128 /*