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-rw-r--r--arch/arm/mach-ixp4xx/avila-pci.c8
-rw-r--r--arch/arm/mach-ixp4xx/avila-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c25
-rw-r--r--arch/arm/mach-ixp4xx/common.c95
-rw-r--r--arch/arm/mach-ixp4xx/coyote-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/coyote-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-pci.c12
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/fsg-pci.c6
-rw-r--r--arch/arm/mach-ixp4xx/fsg-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/gateway7001-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/gateway7001-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/goramo_mlr.c14
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/debug-macro.S16
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/io.h4
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h78
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/memory.h14
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/timex.h5
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-pci.c8
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c12
-rw-r--r--arch/arm/mach-ixp4xx/ixdpg425-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_qmgr.c9
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-pci.c10
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-pci.c6
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/vulcan-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/vulcan-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/wg302v2-pci.c4
-rw-r--r--arch/arm/mach-ixp4xx/wg302v2-setup.c2
33 files changed, 191 insertions, 181 deletions
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 845e1b500548..162043ff29ff 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -39,10 +39,10 @@
39 39
40void __init avila_pci_preinit(void) 40void __init avila_pci_preinit(void)
41{ 41{
42 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
43 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 43 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
44 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 44 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
45 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); 45 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
46 ixp4xx_pci_preinit(); 46 ixp4xx_pci_preinit();
47} 47}
48 48
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index d8bc86d76f1d..73745ff102d5 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -164,8 +164,6 @@ static void __init avila_init(void)
164 164
165MACHINE_START(AVILA, "Gateworks Avila Network Platform") 165MACHINE_START(AVILA, "Gateworks Avila Network Platform")
166 /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */ 166 /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
167 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
168 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
169 .map_io = ixp4xx_map_io, 167 .map_io = ixp4xx_map_io,
170 .init_irq = ixp4xx_init_irq, 168 .init_irq = ixp4xx_init_irq,
171 .timer = &ixp4xx_timer, 169 .timer = &ixp4xx_timer,
@@ -181,8 +179,6 @@ MACHINE_END
181#ifdef CONFIG_MACH_LOFT 179#ifdef CONFIG_MACH_LOFT
182MACHINE_START(LOFT, "Giant Shoulder Inc Loft board") 180MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
183 /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */ 181 /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
184 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
185 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
186 .map_io = ixp4xx_map_io, 182 .map_io = ixp4xx_map_io,
187 .init_irq = ixp4xx_init_irq, 183 .init_irq = ixp4xx_init_irq,
188 .timer = &ixp4xx_timer, 184 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 24498a932ba6..e9a589395723 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -342,29 +342,6 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
342 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); 342 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
343} 343}
344 344
345/*
346 * Only first 64MB of memory can be accessed via PCI.
347 * We use GFP_DMA to allocate safe buffers to do map/unmap.
348 * This is really ugly and we need a better way of specifying
349 * DMA-capable regions of memory.
350 */
351void __init ixp4xx_adjust_zones(unsigned long *zone_size,
352 unsigned long *zhole_size)
353{
354 unsigned int sz = SZ_64M >> PAGE_SHIFT;
355
356 /*
357 * Only adjust if > 64M on current system
358 */
359 if (zone_size[0] <= sz)
360 return;
361
362 zone_size[1] = zone_size[0] - sz;
363 zone_size[0] = sz;
364 zhole_size[1] = zhole_size[0];
365 zhole_size[0] = 0;
366}
367
368void __init ixp4xx_pci_preinit(void) 345void __init ixp4xx_pci_preinit(void)
369{ 346{
370 unsigned long cpuid = read_cpuid_id(); 347 unsigned long cpuid = read_cpuid_id();
@@ -513,4 +490,4 @@ int dma_set_coherent_mask(struct device *dev, u64 mask)
513 490
514EXPORT_SYMBOL(ixp4xx_pci_read); 491EXPORT_SYMBOL(ixp4xx_pci_read);
515EXPORT_SYMBOL(ixp4xx_pci_write); 492EXPORT_SYMBOL(ixp4xx_pci_write);
516 493EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 0bce09799d18..07772575d7ab 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -35,6 +35,7 @@
35#include <asm/pgtable.h> 35#include <asm/pgtable.h>
36#include <asm/page.h> 36#include <asm/page.h>
37#include <asm/irq.h> 37#include <asm/irq.h>
38#include <asm/sched_clock.h>
38 39
39#include <asm/mach/map.h> 40#include <asm/mach/map.h>
40#include <asm/mach/irq.h> 41#include <asm/mach/irq.h>
@@ -127,9 +128,9 @@ int irq_to_gpio(unsigned int irq)
127} 128}
128EXPORT_SYMBOL(irq_to_gpio); 129EXPORT_SYMBOL(irq_to_gpio);
129 130
130static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type) 131static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
131{ 132{
132 int line = irq2gpio[irq]; 133 int line = irq2gpio[d->irq];
133 u32 int_style; 134 u32 int_style;
134 enum ixp4xx_irq_type irq_type; 135 enum ixp4xx_irq_type irq_type;
135 volatile u32 *int_reg; 136 volatile u32 *int_reg;
@@ -166,9 +167,9 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
166 } 167 }
167 168
168 if (irq_type == IXP4XX_IRQ_EDGE) 169 if (irq_type == IXP4XX_IRQ_EDGE)
169 ixp4xx_irq_edge |= (1 << irq); 170 ixp4xx_irq_edge |= (1 << d->irq);
170 else 171 else
171 ixp4xx_irq_edge &= ~(1 << irq); 172 ixp4xx_irq_edge &= ~(1 << d->irq);
172 173
173 if (line >= 8) { /* pins 8-15 */ 174 if (line >= 8) { /* pins 8-15 */
174 line -= 8; 175 line -= 8;
@@ -187,22 +188,22 @@ static int ixp4xx_set_irq_type(unsigned int irq, unsigned int type)
187 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); 188 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
188 189
189 /* Configure the line as an input */ 190 /* Configure the line as an input */
190 gpio_line_config(irq2gpio[irq], IXP4XX_GPIO_IN); 191 gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
191 192
192 return 0; 193 return 0;
193} 194}
194 195
195static void ixp4xx_irq_mask(unsigned int irq) 196static void ixp4xx_irq_mask(struct irq_data *d)
196{ 197{
197 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32) 198 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
198 *IXP4XX_ICMR2 &= ~(1 << (irq - 32)); 199 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
199 else 200 else
200 *IXP4XX_ICMR &= ~(1 << irq); 201 *IXP4XX_ICMR &= ~(1 << d->irq);
201} 202}
202 203
203static void ixp4xx_irq_ack(unsigned int irq) 204static void ixp4xx_irq_ack(struct irq_data *d)
204{ 205{
205 int line = (irq < 32) ? irq2gpio[irq] : -1; 206 int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
206 207
207 if (line >= 0) 208 if (line >= 0)
208 *IXP4XX_GPIO_GPISR = (1 << line); 209 *IXP4XX_GPIO_GPISR = (1 << line);
@@ -212,23 +213,23 @@ static void ixp4xx_irq_ack(unsigned int irq)
212 * Level triggered interrupts on GPIO lines can only be cleared when the 213 * Level triggered interrupts on GPIO lines can only be cleared when the
213 * interrupt condition disappears. 214 * interrupt condition disappears.
214 */ 215 */
215static void ixp4xx_irq_unmask(unsigned int irq) 216static void ixp4xx_irq_unmask(struct irq_data *d)
216{ 217{
217 if (!(ixp4xx_irq_edge & (1 << irq))) 218 if (!(ixp4xx_irq_edge & (1 << d->irq)))
218 ixp4xx_irq_ack(irq); 219 ixp4xx_irq_ack(d);
219 220
220 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32) 221 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
221 *IXP4XX_ICMR2 |= (1 << (irq - 32)); 222 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
222 else 223 else
223 *IXP4XX_ICMR |= (1 << irq); 224 *IXP4XX_ICMR |= (1 << d->irq);
224} 225}
225 226
226static struct irq_chip ixp4xx_irq_chip = { 227static struct irq_chip ixp4xx_irq_chip = {
227 .name = "IXP4xx", 228 .name = "IXP4xx",
228 .ack = ixp4xx_irq_ack, 229 .irq_ack = ixp4xx_irq_ack,
229 .mask = ixp4xx_irq_mask, 230 .irq_mask = ixp4xx_irq_mask,
230 .unmask = ixp4xx_irq_unmask, 231 .irq_unmask = ixp4xx_irq_unmask,
231 .set_type = ixp4xx_set_irq_type, 232 .irq_set_type = ixp4xx_set_irq_type,
232}; 233};
233 234
234void __init ixp4xx_init_irq(void) 235void __init ixp4xx_init_irq(void)
@@ -251,8 +252,8 @@ void __init ixp4xx_init_irq(void)
251 252
252 /* Default to all level triggered */ 253 /* Default to all level triggered */
253 for(i = 0; i < NR_IRQS; i++) { 254 for(i = 0; i < NR_IRQS; i++) {
254 set_irq_chip(i, &ixp4xx_irq_chip); 255 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
255 set_irq_handler(i, handle_level_irq); 256 handle_level_irq);
256 set_irq_flags(i, IRQF_VALID); 257 set_irq_flags(i, IRQF_VALID);
257 } 258 }
258} 259}
@@ -399,41 +400,39 @@ void __init ixp4xx_sys_init(void)
399} 400}
400 401
401/* 402/*
402 * clocksource 403 * sched_clock()
403 */ 404 */
404static cycle_t ixp4xx_get_cycles(struct clocksource *cs) 405static DEFINE_CLOCK_DATA(cd);
406
407unsigned long long notrace sched_clock(void)
405{ 408{
406 return *IXP4XX_OSTS; 409 u32 cyc = *IXP4XX_OSTS;
410 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
407} 411}
408 412
409static struct clocksource clocksource_ixp4xx = { 413static void notrace ixp4xx_update_sched_clock(void)
410 .name = "OSTS",
411 .rating = 200,
412 .read = ixp4xx_get_cycles,
413 .mask = CLOCKSOURCE_MASK(32),
414 .shift = 20,
415 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
416};
417
418unsigned long ixp4xx_timer_freq = FREQ;
419EXPORT_SYMBOL(ixp4xx_timer_freq);
420static void __init ixp4xx_clocksource_init(void)
421{ 414{
422 clocksource_ixp4xx.mult = 415 u32 cyc = *IXP4XX_OSTS;
423 clocksource_hz2mult(ixp4xx_timer_freq, 416 update_sched_clock(&cd, cyc, (u32)~0);
424 clocksource_ixp4xx.shift);
425 clocksource_register(&clocksource_ixp4xx);
426} 417}
427 418
428/* 419/*
429 * sched_clock() 420 * clocksource
430 */ 421 */
431unsigned long long sched_clock(void) 422
423static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
424{
425 return *IXP4XX_OSTS;
426}
427
428unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
429EXPORT_SYMBOL(ixp4xx_timer_freq);
430static void __init ixp4xx_clocksource_init(void)
432{ 431{
433 cycle_t cyc = ixp4xx_get_cycles(NULL); 432 init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);
434 struct clocksource *cs = &clocksource_ixp4xx;
435 433
436 return clocksource_cyc2ns(cyc, cs->mult, cs->shift); 434 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
435 ixp4xx_clocksource_read);
437} 436}
438 437
439/* 438/*
@@ -491,7 +490,7 @@ static struct clock_event_device clockevent_ixp4xx = {
491 490
492static void __init ixp4xx_clockevent_init(void) 491static void __init ixp4xx_clockevent_init(void)
493{ 492{
494 clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC, 493 clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
495 clockevent_ixp4xx.shift); 494 clockevent_ixp4xx.shift);
496 clockevent_ixp4xx.max_delta_ns = 495 clockevent_ixp4xx.max_delta_ns =
497 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx); 496 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index b978ea8bd6f0..37fda7d6e83d 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -32,8 +32,8 @@
32 32
33void __init coyote_pci_preinit(void) 33void __init coyote_pci_preinit(void)
34{ 34{
35 set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); 35 irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
36 set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); 36 irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
37 ixp4xx_pci_preinit(); 37 ixp4xx_pci_preinit();
38} 38}
39 39
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 31a47f6a8939..355e3de38733 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -109,8 +109,6 @@ static void __init coyote_init(void)
109#ifdef CONFIG_ARCH_ADI_COYOTE 109#ifdef CONFIG_ARCH_ADI_COYOTE
110MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote") 110MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
111 /* Maintainer: MontaVista Software, Inc. */ 111 /* Maintainer: MontaVista Software, Inc. */
112 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
113 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
114 .map_io = ixp4xx_map_io, 112 .map_io = ixp4xx_map_io,
115 .init_irq = ixp4xx_init_irq, 113 .init_irq = ixp4xx_init_irq,
116 .timer = &ixp4xx_timer, 114 .timer = &ixp4xx_timer,
@@ -126,8 +124,6 @@ MACHINE_END
126#ifdef CONFIG_MACH_IXDPG425 124#ifdef CONFIG_MACH_IXDPG425
127MACHINE_START(IXDPG425, "Intel IXDPG425") 125MACHINE_START(IXDPG425, "Intel IXDPG425")
128 /* Maintainer: MontaVista Software, Inc. */ 126 /* Maintainer: MontaVista Software, Inc. */
129 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
130 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
131 .map_io = ixp4xx_map_io, 127 .map_io = ixp4xx_map_io,
132 .init_irq = ixp4xx_init_irq, 128 .init_irq = ixp4xx_init_irq,
133 .timer = &ixp4xx_timer, 129 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index fa70fed462ba..c7612010b3fc 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -35,12 +35,12 @@
35 35
36void __init dsmg600_pci_preinit(void) 36void __init dsmg600_pci_preinit(void)
37{ 37{
38 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 38 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
39 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
40 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
41 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); 41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
42 set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); 42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
43 set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); 43 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
44 ixp4xx_pci_preinit(); 44 ixp4xx_pci_preinit();
45} 45}
46 46
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 7c1fa54a6145..d398229cfaa5 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -279,8 +279,6 @@ static void __init dsmg600_init(void)
279 279
280MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") 280MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
281 /* Maintainer: www.nslu2-linux.org */ 281 /* Maintainer: www.nslu2-linux.org */
282 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
283 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
284 .boot_params = 0x00000100, 282 .boot_params = 0x00000100,
285 .map_io = ixp4xx_map_io, 283 .map_io = ixp4xx_map_io,
286 .init_irq = ixp4xx_init_irq, 284 .init_irq = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
index 5a810c930624..44ccde9d4879 100644
--- a/arch/arm/mach-ixp4xx/fsg-pci.c
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -32,9 +32,9 @@
32 32
33void __init fsg_pci_preinit(void) 33void __init fsg_pci_preinit(void)
34{ 34{
35 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 35 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
36 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 36 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
37 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
38 ixp4xx_pci_preinit(); 38 ixp4xx_pci_preinit();
39} 39}
40 40
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index e7f4befba422..727ee39ce11c 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -270,8 +270,6 @@ static void __init fsg_init(void)
270 270
271MACHINE_START(FSG, "Freecom FSG-3") 271MACHINE_START(FSG, "Freecom FSG-3")
272 /* Maintainer: www.nslu2-linux.org */ 272 /* Maintainer: www.nslu2-linux.org */
273 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
274 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
275 .map_io = ixp4xx_map_io, 273 .map_io = ixp4xx_map_io,
276 .init_irq = ixp4xx_init_irq, 274 .init_irq = ixp4xx_init_irq,
277 .timer = &ixp4xx_timer, 275 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c
index 7e93a0975c4d..fc1124168874 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-pci.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c
@@ -29,8 +29,8 @@
29 29
30void __init gateway7001_pci_preinit(void) 30void __init gateway7001_pci_preinit(void)
31{ 31{
32 set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); 32 irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
33 set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); 33 irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
34 34
35 ixp4xx_pci_preinit(); 35 ixp4xx_pci_preinit();
36} 36}
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 2583b2a13174..9dc0b4eaa65a 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -96,8 +96,6 @@ static void __init gateway7001_init(void)
96#ifdef CONFIG_MACH_GATEWAY7001 96#ifdef CONFIG_MACH_GATEWAY7001
97MACHINE_START(GATEWAY7001, "Gateway 7001 AP") 97MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
98 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ 98 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
99 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
100 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
101 .map_io = ixp4xx_map_io, 99 .map_io = ixp4xx_map_io,
102 .init_irq = ixp4xx_init_irq, 100 .init_irq = ixp4xx_init_irq,
103 .timer = &ixp4xx_timer, 101 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 1c28048209c1..3e8c0e33b59c 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -420,8 +420,8 @@ static void __init gmlr_init(void)
420 gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); 420 gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
421 gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); 421 gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
422 gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); 422 gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
423 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); 423 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
424 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); 424 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
425 425
426 set_control(CONTROL_HSS0_DTR_N, 1); 426 set_control(CONTROL_HSS0_DTR_N, 1);
427 set_control(CONTROL_HSS1_DTR_N, 1); 427 set_control(CONTROL_HSS1_DTR_N, 1);
@@ -441,10 +441,10 @@ static void __init gmlr_init(void)
441#ifdef CONFIG_PCI 441#ifdef CONFIG_PCI
442static void __init gmlr_pci_preinit(void) 442static void __init gmlr_pci_preinit(void)
443{ 443{
444 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); 444 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
445 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); 445 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
446 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); 446 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
447 set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); 447 irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
448 ixp4xx_pci_preinit(); 448 ixp4xx_pci_preinit();
449} 449}
450 450
@@ -496,8 +496,6 @@ subsys_initcall(gmlr_pci_init);
496 496
497MACHINE_START(GORAMO_MLR, "MultiLink") 497MACHINE_START(GORAMO_MLR, "MultiLink")
498 /* Maintainer: Krzysztof Halasa */ 498 /* Maintainer: Krzysztof Halasa */
499 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
500 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
501 .map_io = ixp4xx_map_io, 499 .map_io = ixp4xx_map_io,
502 .init_irq = ixp4xx_init_irq, 500 .init_irq = ixp4xx_init_irq,
503 .timer = &ixp4xx_timer, 501 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index 25d2c333c204..38cc0725dbd8 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -43,8 +43,8 @@
43 */ 43 */
44void __init gtwx5715_pci_preinit(void) 44void __init gtwx5715_pci_preinit(void)
45{ 45{
46 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 46 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
47 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 47 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
48 ixp4xx_pci_preinit(); 48 ixp4xx_pci_preinit();
49} 49}
50 50
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index c67586b79400..77abead36227 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -164,8 +164,6 @@ static void __init gtwx5715_init(void)
164 164
165MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)") 165MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
166 /* Maintainer: George Joseph */ 166 /* Maintainer: George Joseph */
167 .phys_io = IXP4XX_UART2_BASE_PHYS,
168 .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc,
169 .map_io = ixp4xx_map_io, 167 .map_io = ixp4xx_map_io,
170 .init_irq = ixp4xx_init_irq, 168 .init_irq = ixp4xx_init_irq,
171 .timer = &ixp4xx_timer, 169 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
index 3fc66d6d00a0..b974a49c0aff 100644
--- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -10,16 +10,16 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13 .macro addruart, rx, tmp 13 .macro addruart, rp, rv
14 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled?
16 moveq \rx, #0xc8000000
17 movne \rx, #0xff000000
18 orrne \rx, \rx, #0x00b00000
19#ifdef __ARMEB__ 14#ifdef __ARMEB__
20 add \rx,\rx,#3 @ Uart regs are at off set of 3 if 15 mov \rp, #3 @ Uart regs are at off set of 3 if
21 @ byte writes used - Big Endian. 16 @ byte writes used - Big Endian.
17#else
18 mov \rp, #0
22#endif 19#endif
20 orr \rv, \rp, #0xff000000 @ virtual
21 orr \rv, \rv, #0x00b00000
22 orr \rp, \rp, #0xc8000000 @ physical
23 .endm 23 .endm
24 24
25#define UART_SHIFT 2 25#define UART_SHIFT 2
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index de274a1f19d7..57b5410c31f4 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -74,8 +74,8 @@ static inline void __indirect_iounmap(void __iomem *addr)
74 __iounmap(addr); 74 __iounmap(addr);
75} 75}
76 76
77#define __arch_ioremap(a, s, f) __indirect_ioremap(a, s, f) 77#define __arch_ioremap __indirect_ioremap
78#define __arch_iounmap(a) __indirect_iounmap(a) 78#define __arch_iounmap __indirect_iounmap
79 79
80#define writeb(v, p) __indirect_writeb(v, p) 80#define writeb(v, p) __indirect_writeb(v, p)
81#define writew(v, p) __indirect_writew(v, p) 81#define writew(v, p) __indirect_writew(v, p)
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000000000000..292d55ed2113
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
1/*
2 * PTP 1588 clock using the IXP46X
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#ifndef _IXP46X_TS_H_
22#define _IXP46X_TS_H_
23
24#define DEFAULT_ADDEND 0xF0000029
25#define TICKS_NS_SHIFT 4
26
27struct ixp46x_channel_ctl {
28 u32 ch_control; /* 0x40 Time Synchronization Channel Control */
29 u32 ch_event; /* 0x44 Time Synchronization Channel Event */
30 u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
31 u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
32 u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
33 u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
34 u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
35 u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
36};
37
38struct ixp46x_ts_regs {
39 u32 control; /* 0x00 Time Sync Control Register */
40 u32 event; /* 0x04 Time Sync Event Register */
41 u32 addend; /* 0x08 Time Sync Addend Register */
42 u32 accum; /* 0x0C Time Sync Accumulator Register */
43 u32 test; /* 0x10 Time Sync Test Register */
44 u32 unused; /* 0x14 */
45 u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
46 u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
47 u32 systime_lo; /* 0x20 SystemTime_Low Register */
48 u32 systime_hi; /* 0x24 SystemTime_High Register */
49 u32 trgt_lo; /* 0x28 TargetTime_Low Register */
50 u32 trgt_hi; /* 0x2C TargetTime_High Register */
51 u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
52 u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
53 u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
54 u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
55
56 struct ixp46x_channel_ctl channel[3];
57};
58
59/* 0x00 Time Sync Control Register Bits */
60#define TSCR_AMM (1<<3)
61#define TSCR_ASM (1<<2)
62#define TSCR_TTM (1<<1)
63#define TSCR_RST (1<<0)
64
65/* 0x04 Time Sync Event Register Bits */
66#define TSER_SNM (1<<3)
67#define TSER_SNS (1<<2)
68#define TTIPEND (1<<1)
69
70/* 0x40 Time Synchronization Channel Control Register Bits */
71#define MASTER_MODE (1<<0)
72#define TIMESTAMP_ALL (1<<1)
73
74/* 0x44 Time Synchronization Channel Event Register Bits */
75#define TX_SNAPSHOT_LOCKED (1<<0)
76#define RX_SNAPSHOT_LOCKED (1<<1)
77
78#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
index 0136eaa29224..34e79404671a 100644
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -12,18 +12,10 @@
12/* 12/*
13 * Physical DRAM offset. 13 * Physical DRAM offset.
14 */ 14 */
15#define PHYS_OFFSET UL(0x00000000) 15#define PLAT_PHYS_OFFSET UL(0x00000000)
16
17#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
18
19void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
20
21#define arch_adjust_zones(size, holes) \
22 ixp4xx_adjust_zones(size, holes)
23
24#define ISA_DMA_THRESHOLD (SZ_64M - 1)
25#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
26 16
17#ifdef CONFIG_PCI
18#define ARM_DMA_ZONE_SIZE SZ_64M
27#endif 19#endif
28 20
29#endif 21#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index 2c3f93c3eb79..c9e930f29339 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -10,6 +10,7 @@
10 * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the 10 * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
11 * timer register ignores the bottom 2 bits of the LATCH value. 11 * timer register ignores the bottom 2 bits of the LATCH value.
12 */ 12 */
13#define FREQ 66666000 13#define IXP4XX_TIMER_FREQ 66666000
14#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) 14#define CLOCK_TICK_RATE \
15 (((IXP4XX_TIMER_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
15 16
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 2db0078a8cf2..219d7c1dcdba 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -19,7 +19,7 @@
19 19
20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) 20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
21 21
22static volatile u32* uart_base; 22volatile u32* uart_base;
23 23
24static inline void putc(int c) 24static inline void putc(int c)
25{ 25{
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 1ba165a6edac..58f400417eaf 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -36,10 +36,10 @@
36 36
37void __init ixdp425_pci_preinit(void) 37void __init ixdp425_pci_preinit(void)
38{ 38{
39 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
40 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
41 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
42 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); 42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
43 ixp4xx_pci_preinit(); 43 ixp4xx_pci_preinit();
44} 44}
45 45
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index ea9ee4ed0a3e..dca4f7f9f4f7 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -60,7 +60,6 @@ static struct platform_device ixdp425_flash = {
60#if defined(CONFIG_MTD_NAND_PLATFORM) || \ 60#if defined(CONFIG_MTD_NAND_PLATFORM) || \
61 defined(CONFIG_MTD_NAND_PLATFORM_MODULE) 61 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
62 62
63#ifdef CONFIG_MTD_PARTITIONS
64const char *part_probes[] = { "cmdlinepart", NULL }; 63const char *part_probes[] = { "cmdlinepart", NULL };
65 64
66static struct mtd_partition ixdp425_partitions[] = { 65static struct mtd_partition ixdp425_partitions[] = {
@@ -74,7 +73,6 @@ static struct mtd_partition ixdp425_partitions[] = {
74 .size = MTDPART_SIZ_FULL 73 .size = MTDPART_SIZ_FULL
75 }, 74 },
76}; 75};
77#endif
78 76
79static void 77static void
80ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) 78ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
@@ -103,11 +101,9 @@ static struct platform_nand_data ixdp425_flash_nand_data = {
103 .nr_chips = 1, 101 .nr_chips = 1,
104 .chip_delay = 30, 102 .chip_delay = 30,
105 .options = NAND_NO_AUTOINCR, 103 .options = NAND_NO_AUTOINCR,
106#ifdef CONFIG_MTD_PARTITIONS
107 .part_probe_types = part_probes, 104 .part_probe_types = part_probes,
108 .partitions = ixdp425_partitions, 105 .partitions = ixdp425_partitions,
109 .nr_partitions = ARRAY_SIZE(ixdp425_partitions), 106 .nr_partitions = ARRAY_SIZE(ixdp425_partitions),
110#endif
111 }, 107 },
112 .ctrl = { 108 .ctrl = {
113 .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl 109 .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
@@ -257,8 +253,6 @@ static void __init ixdp425_init(void)
257#ifdef CONFIG_ARCH_IXDP425 253#ifdef CONFIG_ARCH_IXDP425
258MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") 254MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
259 /* Maintainer: MontaVista Software, Inc. */ 255 /* Maintainer: MontaVista Software, Inc. */
260 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
261 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
262 .map_io = ixp4xx_map_io, 256 .map_io = ixp4xx_map_io,
263 .init_irq = ixp4xx_init_irq, 257 .init_irq = ixp4xx_init_irq,
264 .timer = &ixp4xx_timer, 258 .timer = &ixp4xx_timer,
@@ -270,8 +264,6 @@ MACHINE_END
270#ifdef CONFIG_MACH_IXDP465 264#ifdef CONFIG_MACH_IXDP465
271MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") 265MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
272 /* Maintainer: MontaVista Software, Inc. */ 266 /* Maintainer: MontaVista Software, Inc. */
273 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
274 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
275 .map_io = ixp4xx_map_io, 267 .map_io = ixp4xx_map_io,
276 .init_irq = ixp4xx_init_irq, 268 .init_irq = ixp4xx_init_irq,
277 .timer = &ixp4xx_timer, 269 .timer = &ixp4xx_timer,
@@ -283,8 +275,6 @@ MACHINE_END
283#ifdef CONFIG_ARCH_PRPMC1100 275#ifdef CONFIG_ARCH_PRPMC1100
284MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") 276MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
285 /* Maintainer: MontaVista Software, Inc. */ 277 /* Maintainer: MontaVista Software, Inc. */
286 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
287 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
288 .map_io = ixp4xx_map_io, 278 .map_io = ixp4xx_map_io,
289 .init_irq = ixp4xx_init_irq, 279 .init_irq = ixp4xx_init_irq,
290 .timer = &ixp4xx_timer, 280 .timer = &ixp4xx_timer,
@@ -296,8 +286,6 @@ MACHINE_END
296#ifdef CONFIG_MACH_KIXRP435 286#ifdef CONFIG_MACH_KIXRP435
297MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") 287MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
298 /* Maintainer: MontaVista Software, Inc. */ 288 /* Maintainer: MontaVista Software, Inc. */
299 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
300 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
301 .map_io = ixp4xx_map_io, 289 .map_io = ixp4xx_map_io,
302 .init_irq = ixp4xx_init_irq, 290 .init_irq = ixp4xx_init_irq,
303 .timer = &ixp4xx_timer, 291 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index 4ed7ac614920..e64f6d041488 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -25,8 +25,8 @@
25 25
26void __init ixdpg425_pci_preinit(void) 26void __init ixdpg425_pci_preinit(void)
27{ 27{
28 set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); 28 irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
29 set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); 29 irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
30 30
31 ixp4xx_pci_preinit(); 31 ixp4xx_pci_preinit();
32} 32}
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
index bfdbe4b5a3cc..852f7c9f87d0 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -265,6 +265,11 @@ void qmgr_release_queue(unsigned int queue)
265 qmgr_queue_descs[queue], queue); 265 qmgr_queue_descs[queue], queue);
266 qmgr_queue_descs[queue][0] = '\x0'; 266 qmgr_queue_descs[queue][0] = '\x0';
267#endif 267#endif
268
269 while ((addr = qmgr_get_entry(queue)))
270 printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
271 queue, addr);
272
268 __raw_writel(0, &qmgr_regs->sram[queue]); 273 __raw_writel(0, &qmgr_regs->sram[queue]);
269 274
270 used_sram_bitmap[0] &= ~mask[0]; 275 used_sram_bitmap[0] &= ~mask[0];
@@ -275,10 +280,6 @@ void qmgr_release_queue(unsigned int queue)
275 spin_unlock_irq(&qmgr_lock); 280 spin_unlock_irq(&qmgr_lock);
276 281
277 module_put(THIS_MODULE); 282 module_put(THIS_MODULE);
278
279 while ((addr = qmgr_get_entry(queue)))
280 printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
281 queue, addr);
282} 283}
283 284
284static int qmgr_init(void) 285static int qmgr_init(void)
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index d0cea34cf61e..428d1202b799 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -33,11 +33,11 @@
33 33
34void __init nas100d_pci_preinit(void) 34void __init nas100d_pci_preinit(void)
35{ 35{
36 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 36 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
37 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
38 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 38 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
39 set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); 39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
40 set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); 40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
41 ixp4xx_pci_preinit(); 41 ixp4xx_pci_preinit();
42} 42}
43 43
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index e3ee880aa1e6..f18fee748878 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -314,8 +314,6 @@ static void __init nas100d_init(void)
314 314
315MACHINE_START(NAS100D, "Iomega NAS 100d") 315MACHINE_START(NAS100D, "Iomega NAS 100d")
316 /* Maintainer: www.nslu2-linux.org */ 316 /* Maintainer: www.nslu2-linux.org */
317 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
318 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
319 .boot_params = 0x00000100, 317 .boot_params = 0x00000100,
320 .map_io = ixp4xx_map_io, 318 .map_io = ixp4xx_map_io,
321 .init_irq = ixp4xx_init_irq, 319 .init_irq = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c
index 1eb5a90470bc..2e85f76b950d 100644
--- a/arch/arm/mach-ixp4xx/nslu2-pci.c
+++ b/arch/arm/mach-ixp4xx/nslu2-pci.c
@@ -32,9 +32,9 @@
32 32
33void __init nslu2_pci_preinit(void) 33void __init nslu2_pci_preinit(void)
34{ 34{
35 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 35 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
36 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 36 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
37 set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); 37 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
38 ixp4xx_pci_preinit(); 38 ixp4xx_pci_preinit();
39} 39}
40 40
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index c14e0034be4b..f79b62eb7614 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -300,8 +300,6 @@ static void __init nslu2_init(void)
300 300
301MACHINE_START(NSLU2, "Linksys NSLU2") 301MACHINE_START(NSLU2, "Linksys NSLU2")
302 /* Maintainer: www.nslu2-linux.org */ 302 /* Maintainer: www.nslu2-linux.org */
303 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
304 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
305 .boot_params = 0x00000100, 303 .boot_params = 0x00000100,
306 .map_io = ixp4xx_map_io, 304 .map_io = ixp4xx_map_io,
307 .init_irq = ixp4xx_init_irq, 305 .init_irq = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c
index f3111c6840ef..03bdec5140a7 100644
--- a/arch/arm/mach-ixp4xx/vulcan-pci.c
+++ b/arch/arm/mach-ixp4xx/vulcan-pci.c
@@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void)
38 pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", 38 pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
39 (int)(pci_cardbus_mem_size >> 20)); 39 (int)(pci_cardbus_mem_size >> 20));
40#endif 40#endif
41 set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); 41 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
42 set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); 42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
43 ixp4xx_pci_preinit(); 43 ixp4xx_pci_preinit();
44} 44}
45 45
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 465cc5cce687..4e72cfdd3c46 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -236,8 +236,6 @@ static void __init vulcan_init(void)
236 236
237MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan") 237MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
238 /* Maintainer: Marc Zyngier <maz@misterjones.org> */ 238 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
239 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
240 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
241 .map_io = ixp4xx_map_io, 239 .map_io = ixp4xx_map_io,
242 .init_irq = ixp4xx_init_irq, 240 .init_irq = ixp4xx_init_irq,
243 .timer = &ixp4xx_timer, 241 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c
index 9b59ed03b151..17f3cf59a31b 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-pci.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c
@@ -29,8 +29,8 @@
29 29
30void __init wg302v2_pci_preinit(void) 30void __init wg302v2_pci_preinit(void)
31{ 31{
32 set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); 32 irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
33 set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); 33 irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
34 34
35 ixp4xx_pci_preinit(); 35 ixp4xx_pci_preinit();
36} 36}
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 4dd74863daa9..5d148c7bc4fb 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -97,8 +97,6 @@ static void __init wg302v2_init(void)
97#ifdef CONFIG_MACH_WG302V2 97#ifdef CONFIG_MACH_WG302V2
98MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2") 98MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
99 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ 99 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
100 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
101 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
102 .map_io = ixp4xx_map_io, 100 .map_io = ixp4xx_map_io,
103 .init_irq = ixp4xx_init_irq, 101 .init_irq = ixp4xx_init_irq,
104 .timer = &ixp4xx_timer, 102 .timer = &ixp4xx_timer,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-10 05:05:36 -0500