diff options
Diffstat (limited to 'arch/arm/mach-ixp4xx/goramo_mlr.c')
-rw-r--r-- | arch/arm/mach-ixp4xx/goramo_mlr.c | 45 |
1 files changed, 22 insertions, 23 deletions
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c index a733b8ff3cec..1c28048209c1 100644 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ b/arch/arm/mach-ixp4xx/goramo_mlr.c | |||
@@ -17,29 +17,28 @@ | |||
17 | #include <asm/mach/flash.h> | 17 | #include <asm/mach/flash.h> |
18 | #include <asm/mach/pci.h> | 18 | #include <asm/mach/pci.h> |
19 | 19 | ||
20 | #define xgpio_irq(n) (IRQ_IXP4XX_GPIO ## n) | ||
21 | #define gpio_irq(n) xgpio_irq(n) | ||
22 | |||
23 | #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ | 20 | #define SLOT_ETHA 0x0B /* IDSEL = AD21 */ |
24 | #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ | 21 | #define SLOT_ETHB 0x0C /* IDSEL = AD20 */ |
25 | #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ | 22 | #define SLOT_MPCI 0x0D /* IDSEL = AD19 */ |
26 | #define SLOT_NEC 0x0E /* IDSEL = AD18 */ | 23 | #define SLOT_NEC 0x0E /* IDSEL = AD18 */ |
27 | 24 | ||
28 | #define IRQ_ETHA IRQ_IXP4XX_GPIO4 | ||
29 | #define IRQ_ETHB IRQ_IXP4XX_GPIO5 | ||
30 | #define IRQ_NEC IRQ_IXP4XX_GPIO3 | ||
31 | #define IRQ_MPCI IRQ_IXP4XX_GPIO12 | ||
32 | |||
33 | /* GPIO lines */ | 25 | /* GPIO lines */ |
34 | #define GPIO_SCL 0 | 26 | #define GPIO_SCL 0 |
35 | #define GPIO_SDA 1 | 27 | #define GPIO_SDA 1 |
36 | #define GPIO_STR 2 | 28 | #define GPIO_STR 2 |
29 | #define GPIO_IRQ_NEC 3 | ||
30 | #define GPIO_IRQ_ETHA 4 | ||
31 | #define GPIO_IRQ_ETHB 5 | ||
37 | #define GPIO_HSS0_DCD_N 6 | 32 | #define GPIO_HSS0_DCD_N 6 |
38 | #define GPIO_HSS1_DCD_N 7 | 33 | #define GPIO_HSS1_DCD_N 7 |
34 | #define GPIO_UART0_DCD 8 | ||
35 | #define GPIO_UART1_DCD 9 | ||
39 | #define GPIO_HSS0_CTS_N 10 | 36 | #define GPIO_HSS0_CTS_N 10 |
40 | #define GPIO_HSS1_CTS_N 11 | 37 | #define GPIO_HSS1_CTS_N 11 |
38 | #define GPIO_IRQ_MPCI 12 | ||
41 | #define GPIO_HSS1_RTS_N 13 | 39 | #define GPIO_HSS1_RTS_N 13 |
42 | #define GPIO_HSS0_RTS_N 14 | 40 | #define GPIO_HSS0_RTS_N 14 |
41 | /* GPIO15 is not connected */ | ||
43 | 42 | ||
44 | /* Control outputs from 74HC4094 */ | 43 | /* Control outputs from 74HC4094 */ |
45 | #define CONTROL_HSS0_CLK_INT 0 | 44 | #define CONTROL_HSS0_CLK_INT 0 |
@@ -152,7 +151,7 @@ static int hss_set_clock(int port, unsigned int clock_type) | |||
152 | 151 | ||
153 | static irqreturn_t hss_dcd_irq(int irq, void *pdev) | 152 | static irqreturn_t hss_dcd_irq(int irq, void *pdev) |
154 | { | 153 | { |
155 | int i, port = (irq == gpio_irq(GPIO_HSS1_DCD_N)); | 154 | int i, port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); |
156 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); | 155 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); |
157 | set_carrier_cb_tab[port](pdev, !i); | 156 | set_carrier_cb_tab[port](pdev, !i); |
158 | return IRQ_HANDLED; | 157 | return IRQ_HANDLED; |
@@ -165,9 +164,9 @@ static int hss_open(int port, void *pdev, | |||
165 | int i, irq; | 164 | int i, irq; |
166 | 165 | ||
167 | if (!port) | 166 | if (!port) |
168 | irq = gpio_irq(GPIO_HSS0_DCD_N); | 167 | irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); |
169 | else | 168 | else |
170 | irq = gpio_irq(GPIO_HSS1_DCD_N); | 169 | irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); |
171 | 170 | ||
172 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); | 171 | gpio_line_get(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N, &i); |
173 | set_carrier_cb(pdev, !i); | 172 | set_carrier_cb(pdev, !i); |
@@ -188,8 +187,8 @@ static int hss_open(int port, void *pdev, | |||
188 | 187 | ||
189 | static void hss_close(int port, void *pdev) | 188 | static void hss_close(int port, void *pdev) |
190 | { | 189 | { |
191 | free_irq(port ? gpio_irq(GPIO_HSS1_DCD_N) : gpio_irq(GPIO_HSS0_DCD_N), | 190 | free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : |
192 | pdev); | 191 | IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); |
193 | set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ | 192 | set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ |
194 | 193 | ||
195 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); | 194 | set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); |
@@ -421,8 +420,8 @@ static void __init gmlr_init(void) | |||
421 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); | 420 | gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); |
422 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); | 421 | gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); |
423 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); | 422 | gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); |
424 | set_irq_type(gpio_irq(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); | 423 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); |
425 | set_irq_type(gpio_irq(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); | 424 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); |
426 | 425 | ||
427 | set_control(CONTROL_HSS0_DTR_N, 1); | 426 | set_control(CONTROL_HSS0_DTR_N, 1); |
428 | set_control(CONTROL_HSS1_DTR_N, 1); | 427 | set_control(CONTROL_HSS1_DTR_N, 1); |
@@ -442,10 +441,10 @@ static void __init gmlr_init(void) | |||
442 | #ifdef CONFIG_PCI | 441 | #ifdef CONFIG_PCI |
443 | static void __init gmlr_pci_preinit(void) | 442 | static void __init gmlr_pci_preinit(void) |
444 | { | 443 | { |
445 | set_irq_type(IRQ_ETHA, IRQ_TYPE_LEVEL_LOW); | 444 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); |
446 | set_irq_type(IRQ_ETHB, IRQ_TYPE_LEVEL_LOW); | 445 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); |
447 | set_irq_type(IRQ_NEC, IRQ_TYPE_LEVEL_LOW); | 446 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); |
448 | set_irq_type(IRQ_MPCI, IRQ_TYPE_LEVEL_LOW); | 447 | set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); |
449 | ixp4xx_pci_preinit(); | 448 | ixp4xx_pci_preinit(); |
450 | } | 449 | } |
451 | 450 | ||
@@ -466,10 +465,10 @@ static void __init gmlr_pci_postinit(void) | |||
466 | static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 465 | static int __init gmlr_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
467 | { | 466 | { |
468 | switch(slot) { | 467 | switch(slot) { |
469 | case SLOT_ETHA: return IRQ_ETHA; | 468 | case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); |
470 | case SLOT_ETHB: return IRQ_ETHB; | 469 | case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); |
471 | case SLOT_NEC: return IRQ_NEC; | 470 | case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); |
472 | default: return IRQ_MPCI; | 471 | default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); |
473 | } | 472 | } |
474 | } | 473 | } |
475 | 474 | ||