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-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h54
1 files changed, 9 insertions, 45 deletions
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index e00a2624f269..5e6ea5cfea6e 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -23,9 +23,6 @@
23 * 23 *
24 * Integrator address map 24 * Integrator address map
25 * 25 *
26 * NOTE: This is a multi-hosted header file for use with uHAL and
27 * supported debuggers.
28 *
29 * ***********************************************************************/ 26 * ***********************************************************************/
30 27
31#ifndef __address_h 28#ifndef __address_h
@@ -290,12 +287,14 @@
290#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET) 287#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
291#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET) 288#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
292 289
290#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
293 291
294#if defined(CONFIG_ARCH_INTEGRATOR_AP) 292#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
295#define INTEGRATOR_GPIO_BASE 0x1B000000 /* GPIO */ 293#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
296#elif defined(CONFIG_ARCH_INTEGRATOR_CP) 294#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
297#define INTEGRATOR_GPIO_BASE 0xC9000000 /* GPIO */ 295#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
298#endif 296#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
297#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
299 298
300/* ------------------------------------------------------------------------ 299/* ------------------------------------------------------------------------
301 * KMI keyboard/mouse definitions 300 * KMI keyboard/mouse definitions
@@ -328,20 +327,6 @@
328 */ 327 */
329#define PHYS_PCI_V3_BASE 0x62000000 328#define PHYS_PCI_V3_BASE 0x62000000
330 329
331#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
332
333/* 'export' these to UHAL */
334#define UHAL_PCI_IO PCI_IO_BASE
335#define UHAL_PCI_MEM PCI_MEM_BASE
336#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
337#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
338#define UHAL_PCI_MAX_SLOT 20
339
340/* ========================================================================
341 * Start of uHAL definitions
342 * ========================================================================
343 */
344
345/* ------------------------------------------------------------------------ 330/* ------------------------------------------------------------------------
346 * Integrator Interrupt Controllers 331 * Integrator Interrupt Controllers
347 * ------------------------------------------------------------------------ 332 * ------------------------------------------------------------------------
@@ -389,7 +374,7 @@
389 */ 374 */
390 375
391/* ------------------------------------------------------------------------ 376/* ------------------------------------------------------------------------
392 * LED's - The header LED is not accessible via the uHAL API 377 * LED's
393 * ------------------------------------------------------------------------ 378 * ------------------------------------------------------------------------
394 * 379 *
395 */ 380 */
@@ -402,34 +387,18 @@
402#define LED_BANK INTEGRATOR_DBG_LEDS 387#define LED_BANK INTEGRATOR_DBG_LEDS
403 388
404/* 389/*
405 * Memory definitions - run uHAL out of SSRAM.
406 *
407 */
408#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
409
410/*
411 * Clean base - dummy
412 *
413 */
414#define CLEAN_BASE INTEGRATOR_BOOT_ROM_HI
415
416/*
417 * Timer definitions 390 * Timer definitions
418 * 391 *
419 * Only use timer 1 & 2 392 * Only use timer 1 & 2
420 * (both run at 24MHz and will need the clock divider set to 16). 393 * (both run at 24MHz and will need the clock divider set to 16).
421 * 394 *
422 * Timer 0 runs at bus frequency and therefore could vary and currently 395 * Timer 0 runs at bus frequency
423 * uHAL can't handle that.
424 *
425 */ 396 */
426 397
427#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE 398#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
428#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100) 399#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
429#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200) 400#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
430 401
431#define MAX_TIMER 2
432#define MAX_PERIOD 699050
433#define TICKS_PER_uSEC 24 402#define TICKS_PER_uSEC 24
434 403
435/* 404/*
@@ -437,14 +406,9 @@
437 * 406 *
438 */ 407 */
439#define mSEC_1 1000 408#define mSEC_1 1000
440#define mSEC_5 (mSEC_1 * 5)
441#define mSEC_10 (mSEC_1 * 10) 409#define mSEC_10 (mSEC_1 * 10)
442#define mSEC_25 (mSEC_1 * 25)
443#define SEC_1 (mSEC_1 * 1000)
444 410
445#define INTEGRATOR_CSR_BASE 0x10000000 411#define INTEGRATOR_CSR_BASE 0x10000000
446#define INTEGRATOR_CSR_SIZE 0x10000000 412#define INTEGRATOR_CSR_SIZE 0x10000000
447 413
448#endif 414#endif
449
450/* END */