5 files changed, 22 insertions, 5 deletions

diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c
index deb4b8093b30..0d40b35c557c 100644
--- a/arch/arm/mach-imx/clk-fixup-mux.c
+++ b/arch/arm/mach-imx/clk-fixup-mux.c
@@ -90,6 +90,7 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
         init.ops = &clk_fixup_mux_ops;
         init.parent_names = parents;
         init.num_parents = num_parents;
+        init.flags = 0;
 
         fixup_mux->mux.reg = reg;
         fixup_mux->mux.shift = shift;
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index c3cfa4116dc0..c6b40f386786 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -285,7 +285,7 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
         clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
         clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
-        clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0");
+        clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
         clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
 
         mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 1a56a3319997..7c0dc4540aa4 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -328,7 +328,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-        clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
+        clk_register_clkdev(clk[cpu_podf], NULL, "cpu0");
         clk_register_clkdev(clk[iim_gate], "iim", NULL);
         clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
         clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
@@ -397,7 +397,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                                 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
         clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
                                 spdif_sel, ARRAY_SIZE(spdif_sel));
-        clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
+        clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
         clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
         clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
                                 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 85a1b51346c8..90372a21087f 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -233,10 +233,15 @@ put_node:
         of_node_put(np);
 }
 
-static void __init imx6q_opp_init(struct device *cpu_dev)
+static void __init imx6q_opp_init(void)
 {
         struct device_node *np;
+        struct device *cpu_dev = get_cpu_device(0);
 
+        if (!cpu_dev) {
+                pr_warn("failed to get cpu0 device\n");
+                return;
+        }
         np = of_node_get(cpu_dev->of_node);
         if (!np) {
                 pr_warn("failed to find cpu0 node\n");
@@ -268,7 +273,7 @@ static void __init imx6q_init_late(void)
                 imx6q_cpuidle_init();
 
         if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
-                imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
+                imx6q_opp_init();
                 platform_device_register(&imx6q_cpufreq_pdev);
         }
 }
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 64ff37ea72b1..80c177c36c5f 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -117,6 +117,17 @@ void __init imx_init_l2cache(void)
         /* Configure the L2 PREFETCH and POWER registers */
         val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
         val |= 0x70800000;
+        /*
+         * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+         * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+         * But according to ARM PL310 errata: 752271
+         * ID: 752271: Double linefill feature can cause data corruption
+         * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+         * Workaround: The only workaround to this erratum is to disable the
+         * double linefill feature. This is the default behavior.
+         */
+        if (cpu_is_imx6q())
+                val &= ~(1 << 30 | 1 << 23);
         writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
         val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
         writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);