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Diffstat (limited to 'arch/arm/mach-imx/clock-imx35.c')
-rw-r--r--arch/arm/mach-imx/clock-imx35.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index 8116f119517d..ac8238caecb9 100644
--- a/arch/arm/mach-imx/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -507,7 +507,7 @@ static struct clk_lookup lookups[] = {
507 507
508int __init mx35_clocks_init() 508int __init mx35_clocks_init()
509{ 509{
510 unsigned int cgr2 = 3 << 26, cgr3 = 0; 510 unsigned int cgr2 = 3 << 26;
511 511
512#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) 512#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
513 cgr2 |= 3 << 16; 513 cgr2 |= 3 << 16;
@@ -521,6 +521,12 @@ int __init mx35_clocks_init()
521 __raw_writel((3 << 18), CCM_BASE + CCM_CGR0); 521 __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
522 __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16), 522 __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
523 CCM_BASE + CCM_CGR1); 523 CCM_BASE + CCM_CGR1);
524 __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
525 __raw_writel(0, CCM_BASE + CCM_CGR3);
526
527 clk_enable(&iim_clk);
528 imx_print_silicon_rev("i.MX35", mx35_revision());
529 clk_disable(&iim_clk);
524 530
525 /* 531 /*
526 * Check if we came up in internal boot mode. If yes, we need some 532 * Check if we came up in internal boot mode. If yes, we need some
@@ -529,17 +535,11 @@ int __init mx35_clocks_init()
529 */ 535 */
530 if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) { 536 if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
531 /* Additionally turn on UART1, SCC, and IIM clocks */ 537 /* Additionally turn on UART1, SCC, and IIM clocks */
532 cgr2 |= 3 << 16 | 3 << 4; 538 clk_enable(&iim_clk);
533 cgr3 |= 3 << 2; 539 clk_enable(&uart1_clk);
540 clk_enable(&scc_clk);
534 } 541 }
535 542
536 __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
537 __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
538
539 clk_enable(&iim_clk);
540 imx_print_silicon_rev("i.MX35", mx35_revision());
541 clk_disable(&iim_clk);
542
543#ifdef CONFIG_MXC_USE_EPIT 543#ifdef CONFIG_MXC_USE_EPIT
544 epit_timer_init(&epit1_clk, 544 epit_timer_init(&epit1_clk,
545 MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); 545 MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);