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Diffstat (limited to 'arch/arm/mach-imx/clk-pllv3.c')
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c43
1 files changed, 25 insertions, 18 deletions
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index c9ca19184420..df1736232961 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -46,21 +46,15 @@ struct clk_pllv3 {
46 46
47#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw) 47#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
48 48
49static int clk_pllv3_prepare(struct clk_hw *hw) 49static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
50{ 50{
51 struct clk_pllv3 *pll = to_clk_pllv3(hw); 51 unsigned long timeout = jiffies + msecs_to_jiffies(10);
52 unsigned long timeout; 52 u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
53 u32 val;
54 53
55 val = readl_relaxed(pll->base); 54 /* No need to wait for lock when pll is not powered up */
56 val &= ~BM_PLL_BYPASS; 55 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
57 if (pll->powerup_set) 56 return 0;
58 val |= BM_PLL_POWER;
59 else
60 val &= ~BM_PLL_POWER;
61 writel_relaxed(val, pll->base);
62 57
63 timeout = jiffies + msecs_to_jiffies(10);
64 /* Wait for PLL to lock */ 58 /* Wait for PLL to lock */
65 do { 59 do {
66 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 60 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
@@ -70,10 +64,23 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
70 usleep_range(50, 500); 64 usleep_range(50, 500);
71 } while (1); 65 } while (1);
72 66
73 if (readl_relaxed(pll->base) & BM_PLL_LOCK) 67 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
74 return 0; 68}
69
70static int clk_pllv3_prepare(struct clk_hw *hw)
71{
72 struct clk_pllv3 *pll = to_clk_pllv3(hw);
73 u32 val;
74
75 val = readl_relaxed(pll->base);
76 val &= ~BM_PLL_BYPASS;
77 if (pll->powerup_set)
78 val |= BM_PLL_POWER;
75 else 79 else
76 return -ETIMEDOUT; 80 val &= ~BM_PLL_POWER;
81 writel_relaxed(val, pll->base);
82
83 return clk_pllv3_wait_lock(pll);
77} 84}
78 85
79static void clk_pllv3_unprepare(struct clk_hw *hw) 86static void clk_pllv3_unprepare(struct clk_hw *hw)
@@ -148,7 +155,7 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
148 val |= div; 155 val |= div;
149 writel_relaxed(val, pll->base); 156 writel_relaxed(val, pll->base);
150 157
151 return 0; 158 return clk_pllv3_wait_lock(pll);
152} 159}
153 160
154static const struct clk_ops clk_pllv3_ops = { 161static const struct clk_ops clk_pllv3_ops = {
@@ -204,7 +211,7 @@ static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
204 val |= div; 211 val |= div;
205 writel_relaxed(val, pll->base); 212 writel_relaxed(val, pll->base);
206 213
207 return 0; 214 return clk_pllv3_wait_lock(pll);
208} 215}
209 216
210static const struct clk_ops clk_pllv3_sys_ops = { 217static const struct clk_ops clk_pllv3_sys_ops = {
@@ -278,7 +285,7 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
278 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); 285 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
279 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); 286 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
280 287
281 return 0; 288 return clk_pllv3_wait_lock(pll);
282} 289}
283 290
284static const struct clk_ops clk_pllv3_av_ops = { 291static const struct clk_ops clk_pllv3_av_ops = {