diff options
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index b0e7f9d2c245..2b4d6acfa34a 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
| @@ -208,8 +208,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 208 | * the "output_enable" bit as a gate, even though it's really just | 208 | * the "output_enable" bit as a gate, even though it's really just |
| 209 | * enabling clock output. | 209 | * enabling clock output. |
| 210 | */ | 210 | */ |
| 211 | clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); | 211 | clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10); |
| 212 | clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); | 212 | clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11); |
| 213 | 213 | ||
| 214 | /* name parent_name reg idx */ | 214 | /* name parent_name reg idx */ |
| 215 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | 215 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); |
| @@ -258,14 +258,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 258 | clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); | 258 | clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); |
| 259 | clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | 259 | clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
| 260 | clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); | 260 | clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); |
| 261 | clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); | 261 | clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
| 262 | clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); | 262 | clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
| 263 | clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); | 263 | clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
| 264 | clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels)); | 264 | clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); |
| 265 | clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels)); | 265 | clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); |
| 266 | clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels)); | 266 | clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); |
| 267 | clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels)); | 267 | clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); |
| 268 | clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); | 268 | clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); |
| 269 | clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); | 269 | clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); |
| 270 | clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); | 270 | clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); |
| 271 | clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); | 271 | clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); |
| @@ -445,6 +445,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) | |||
| 445 | clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); | 445 | clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); |
| 446 | } | 446 | } |
| 447 | 447 | ||
| 448 | clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); | ||
| 449 | clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); | ||
| 450 | clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); | ||
| 451 | clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]); | ||
| 452 | clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]); | ||
| 453 | clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]); | ||
| 454 | clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]); | ||
| 455 | clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]); | ||
| 456 | |||
| 448 | /* | 457 | /* |
| 449 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, | 458 | * The gpmi needs 100MHz frequency in the EDO/Sync mode, |
| 450 | * We can not get the 100MHz from the pll2_pfd0_352m. | 459 | * We can not get the 100MHz from the pll2_pfd0_352m. |