aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-exynos4/include
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-exynos4/include')
-rw-r--r--arch/arm/mach-exynos4/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-exynos4/include/mach/dwmci.h20
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S11
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h196
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h19
-rw-r--r--arch/arm/mach-exynos4/include/mach/pm-core.h10
-rw-r--r--arch/arm/mach-exynos4/include/mach/pmu.h25
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-audss.h18
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h12
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h1
10 files changed, 214 insertions, 105 deletions
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_CLKDEV_H__
2#define __MACH_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do {} while (0)
6
7#endif
diff --git a/arch/arm/mach-exynos4/include/mach/dwmci.h b/arch/arm/mach-exynos4/include/mach/dwmci.h
new file mode 100644
index 000000000000..7ce657459cc0
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/dwmci.h
@@ -0,0 +1,20 @@
1/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Synopsys DesignWare Mobile Storage for EXYNOS4210
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARM_ARCH_DWMCI_H
14#define __ASM_ARM_ARCH_DWMCI_H __FILE__
15
16#include <linux/mmc/dw_mmc.h>
17
18extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
19
20#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d8f38c2e5654..d7a1e281ce7a 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -10,6 +10,7 @@
10*/ 10*/
11 11
12#include <mach/hardware.h> 12#include <mach/hardware.h>
13#include <mach/map.h>
13#include <asm/hardware/gic.h> 14#include <asm/hardware/gic.h>
14 15
15 .macro disable_fiq 16 .macro disable_fiq
@@ -18,6 +19,10 @@
18 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
19 ldr \base, =gic_cpu_base_addr 20 ldr \base, =gic_cpu_base_addr
20 ldr \base, [\base] 21 ldr \base, [\base]
22 mrc p15, 0, \tmp, c0, c0, 5
23 and \tmp, \tmp, #3
24 cmp \tmp, #1
25 addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
21 .endm 26 .endm
22 27
23 .macro arch_ret_to_user, tmp1, tmp2 28 .macro arch_ret_to_user, tmp1, tmp2
@@ -75,10 +80,4 @@
75 /* As above, this assumes that irqstat and base are preserved.. */ 80 /* As above, this assumes that irqstat and base are preserved.. */
76 81
77 .macro test_for_ltirq, irqnr, irqstat, base, tmp 82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
78 bic \irqnr, \irqstat, #0x1c00
79 mov \tmp, #0
80 cmp \irqnr, #29
81 moveq \tmp, #1
82 streq \irqstat, [\base, #GIC_CPU_EOI]
83 cmp \tmp, #0
84 .endm 83 .endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 5d037301d21a..934d2a493982 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,40 +19,105 @@
19 19
20#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) S5P_IRQ(x+16)
21 21
22#define IRQ_LOCALTIMER IRQ_PPI(13)
23
24/* SPI: Shared Peripheral Interrupt */ 22/* SPI: Shared Peripheral Interrupt */
25 23
26#define IRQ_SPI(x) S5P_IRQ(x+32) 24#define IRQ_SPI(x) S5P_IRQ(x+32)
27 25
28#define IRQ_MCT1 IRQ_SPI(35) 26#define IRQ_EINT0 IRQ_SPI(16)
29 27#define IRQ_EINT1 IRQ_SPI(17)
30#define IRQ_EINT0 IRQ_SPI(40) 28#define IRQ_EINT2 IRQ_SPI(18)
31#define IRQ_EINT1 IRQ_SPI(41) 29#define IRQ_EINT3 IRQ_SPI(19)
32#define IRQ_EINT2 IRQ_SPI(42) 30#define IRQ_EINT4 IRQ_SPI(20)
33#define IRQ_EINT3 IRQ_SPI(43) 31#define IRQ_EINT5 IRQ_SPI(21)
34#define IRQ_USB_HSOTG IRQ_SPI(44) 32#define IRQ_EINT6 IRQ_SPI(22)
35#define IRQ_USB_HOST IRQ_SPI(45) 33#define IRQ_EINT7 IRQ_SPI(23)
36#define IRQ_MODEM_IF IRQ_SPI(46) 34#define IRQ_EINT8 IRQ_SPI(24)
37#define IRQ_ROTATOR IRQ_SPI(47) 35#define IRQ_EINT9 IRQ_SPI(25)
38#define IRQ_JPEG IRQ_SPI(48) 36#define IRQ_EINT10 IRQ_SPI(26)
39#define IRQ_2D IRQ_SPI(49) 37#define IRQ_EINT11 IRQ_SPI(27)
40#define IRQ_PCIE IRQ_SPI(50) 38#define IRQ_EINT12 IRQ_SPI(28)
41#define IRQ_MCT0 IRQ_SPI(51) 39#define IRQ_EINT13 IRQ_SPI(29)
42#define IRQ_MFC IRQ_SPI(52) 40#define IRQ_EINT14 IRQ_SPI(30)
43#define IRQ_AUDIO_SS IRQ_SPI(54) 41#define IRQ_EINT15 IRQ_SPI(31)
44#define IRQ_AC97 IRQ_SPI(55) 42#define IRQ_EINT16_31 IRQ_SPI(32)
45#define IRQ_SPDIF IRQ_SPI(56) 43
46#define IRQ_KEYPAD IRQ_SPI(57) 44#define IRQ_PDMA0 IRQ_SPI(35)
47#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58) 45#define IRQ_PDMA1 IRQ_SPI(36)
48#define IRQ_SLIMBUS IRQ_SPI(59) 46#define IRQ_TIMER0_VIC IRQ_SPI(37)
49#define IRQ_PMU IRQ_SPI(60) 47#define IRQ_TIMER1_VIC IRQ_SPI(38)
50#define IRQ_TSI IRQ_SPI(61) 48#define IRQ_TIMER2_VIC IRQ_SPI(39)
51#define IRQ_SATA IRQ_SPI(62) 49#define IRQ_TIMER3_VIC IRQ_SPI(40)
52#define IRQ_GPS IRQ_SPI(63) 50#define IRQ_TIMER4_VIC IRQ_SPI(41)
51#define IRQ_MCT_L0 IRQ_SPI(42)
52#define IRQ_WDT IRQ_SPI(43)
53#define IRQ_RTC_ALARM IRQ_SPI(44)
54#define IRQ_RTC_TIC IRQ_SPI(45)
55#define IRQ_GPIO_XB IRQ_SPI(46)
56#define IRQ_GPIO_XA IRQ_SPI(47)
57#define IRQ_MCT_L1 IRQ_SPI(48)
58
59#define IRQ_UART0 IRQ_SPI(52)
60#define IRQ_UART1 IRQ_SPI(53)
61#define IRQ_UART2 IRQ_SPI(54)
62#define IRQ_UART3 IRQ_SPI(55)
63#define IRQ_UART4 IRQ_SPI(56)
64#define IRQ_MCT_G0 IRQ_SPI(57)
65#define IRQ_IIC IRQ_SPI(58)
66#define IRQ_IIC1 IRQ_SPI(59)
67#define IRQ_IIC2 IRQ_SPI(60)
68#define IRQ_IIC3 IRQ_SPI(61)
69#define IRQ_IIC4 IRQ_SPI(62)
70#define IRQ_IIC5 IRQ_SPI(63)
71#define IRQ_IIC6 IRQ_SPI(64)
72#define IRQ_IIC7 IRQ_SPI(65)
73
74#define IRQ_USB_HOST IRQ_SPI(70)
75#define IRQ_USB_HSOTG IRQ_SPI(71)
76#define IRQ_MODEM_IF IRQ_SPI(72)
77#define IRQ_HSMMC0 IRQ_SPI(73)
78#define IRQ_HSMMC1 IRQ_SPI(74)
79#define IRQ_HSMMC2 IRQ_SPI(75)
80#define IRQ_HSMMC3 IRQ_SPI(76)
81#define IRQ_DWMCI IRQ_SPI(77)
82
83#define IRQ_MIPICSI0 IRQ_SPI(78)
84
85#define IRQ_MIPICSI1 IRQ_SPI(80)
86
87#define IRQ_ONENAND_AUDI IRQ_SPI(82)
88#define IRQ_ROTATOR IRQ_SPI(83)
89#define IRQ_FIMC0 IRQ_SPI(84)
90#define IRQ_FIMC1 IRQ_SPI(85)
91#define IRQ_FIMC2 IRQ_SPI(86)
92#define IRQ_FIMC3 IRQ_SPI(87)
93#define IRQ_JPEG IRQ_SPI(88)
94#define IRQ_2D IRQ_SPI(89)
95#define IRQ_PCIE IRQ_SPI(90)
96
97#define IRQ_MFC IRQ_SPI(94)
98
99#define IRQ_AUDIO_SS IRQ_SPI(96)
100#define IRQ_I2S0 IRQ_SPI(97)
101#define IRQ_I2S1 IRQ_SPI(98)
102#define IRQ_I2S2 IRQ_SPI(99)
103#define IRQ_AC97 IRQ_SPI(100)
104
105#define IRQ_SPDIF IRQ_SPI(104)
106#define IRQ_ADC0 IRQ_SPI(105)
107#define IRQ_PEN0 IRQ_SPI(106)
108#define IRQ_ADC1 IRQ_SPI(107)
109#define IRQ_PEN1 IRQ_SPI(108)
110#define IRQ_KEYPAD IRQ_SPI(109)
111#define IRQ_PMU IRQ_SPI(110)
112#define IRQ_GPS IRQ_SPI(111)
113#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
114#define IRQ_SLIMBUS IRQ_SPI(113)
115
116#define IRQ_TSI IRQ_SPI(115)
117#define IRQ_SATA IRQ_SPI(116)
53 118
54#define MAX_IRQ_IN_COMBINER 8 119#define MAX_IRQ_IN_COMBINER 8
55#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64)) 120#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
56#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y) 121#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
57 122
58#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0) 123#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
@@ -73,75 +138,14 @@
73#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6) 138#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
74#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7) 139#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
75 140
76#define IRQ_PDMA0 COMBINER_IRQ(21, 0) 141#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
77#define IRQ_PDMA1 COMBINER_IRQ(21, 1) 142#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
78 143#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
79#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
80#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
81#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
82#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
83#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
84
85#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
86#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
87
88#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
89#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
90
91#define IRQ_UART0 COMBINER_IRQ(26, 0)
92#define IRQ_UART1 COMBINER_IRQ(26, 1)
93#define IRQ_UART2 COMBINER_IRQ(26, 2)
94#define IRQ_UART3 COMBINER_IRQ(26, 3)
95#define IRQ_UART4 COMBINER_IRQ(26, 4)
96
97#define IRQ_IIC COMBINER_IRQ(27, 0)
98#define IRQ_IIC1 COMBINER_IRQ(27, 1)
99#define IRQ_IIC2 COMBINER_IRQ(27, 2)
100#define IRQ_IIC3 COMBINER_IRQ(27, 3)
101#define IRQ_IIC4 COMBINER_IRQ(27, 4)
102#define IRQ_IIC5 COMBINER_IRQ(27, 5)
103#define IRQ_IIC6 COMBINER_IRQ(27, 6)
104#define IRQ_IIC7 COMBINER_IRQ(27, 7)
105
106#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
107#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
108#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
109#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
110
111#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
112#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
113
114#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
115#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
116#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
117#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
118
119#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
120
121#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
122
123#define IRQ_EINT4 COMBINER_IRQ(37, 0)
124#define IRQ_EINT5 COMBINER_IRQ(37, 1)
125#define IRQ_EINT6 COMBINER_IRQ(37, 2)
126#define IRQ_EINT7 COMBINER_IRQ(37, 3)
127#define IRQ_EINT8 COMBINER_IRQ(38, 0)
128
129#define IRQ_EINT9 COMBINER_IRQ(38, 1)
130#define IRQ_EINT10 COMBINER_IRQ(38, 2)
131#define IRQ_EINT11 COMBINER_IRQ(38, 3)
132#define IRQ_EINT12 COMBINER_IRQ(38, 4)
133#define IRQ_EINT13 COMBINER_IRQ(38, 5)
134#define IRQ_EINT14 COMBINER_IRQ(38, 6)
135#define IRQ_EINT15 COMBINER_IRQ(38, 7)
136
137#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
138
139#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
140 144
141#define IRQ_WDT COMBINER_IRQ(53, 0) 145#define MAX_COMBINER_NR 16
142#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
143 146
144#define MAX_COMBINER_NR 54 147#define IRQ_ADC IRQ_ADC0
148#define IRQ_TC IRQ_PEN0
145 149
146#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0) 150#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
147 151
@@ -155,6 +159,6 @@
155#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT) 159#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
156 160
157/* Set the default NR_IRQS */ 161/* Set the default NR_IRQS */
158#define NR_IRQS (IRQ_GPIO_END) 162#define NR_IRQS (IRQ_GPIO_END + 64)
159 163
160#endif /* __ASM_ARCH_IRQS_H */ 164#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 0009e77a05fc..d32296dc65e2 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -57,12 +57,14 @@
57 57
58#define EXYNOS4_PA_DMC0 0x10400000 58#define EXYNOS4_PA_DMC0 0x10400000
59 59
60#define EXYNOS4_PA_COMBINER 0x10448000 60#define EXYNOS4_PA_COMBINER 0x10440000
61
62#define EXYNOS4_PA_GIC_CPU 0x10480000
63#define EXYNOS4_PA_GIC_DIST 0x10490000
64#define EXYNOS4_GIC_BANK_OFFSET 0x8000
61 65
62#define EXYNOS4_PA_COREPERI 0x10500000 66#define EXYNOS4_PA_COREPERI 0x10500000
63#define EXYNOS4_PA_GIC_CPU 0x10500100
64#define EXYNOS4_PA_TWD 0x10500600 67#define EXYNOS4_PA_TWD 0x10500600
65#define EXYNOS4_PA_GIC_DIST 0x10501000
66#define EXYNOS4_PA_L2CC 0x10502000 68#define EXYNOS4_PA_L2CC 0x10502000
67 69
68#define EXYNOS4_PA_MDMA 0x10810000 70#define EXYNOS4_PA_MDMA 0x10810000
@@ -93,7 +95,10 @@
93#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 95#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
94#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 96#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
95 97
98#define EXYNOS4_PA_FIMD0 0x11C00000
99
96#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 100#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
101#define EXYNOS4_PA_DWMCI 0x12550000
97 102
98#define EXYNOS4_PA_SATA 0x12560000 103#define EXYNOS4_PA_SATA 0x12560000
99#define EXYNOS4_PA_SATAPHY 0x125D0000 104#define EXYNOS4_PA_SATAPHY 0x125D0000
@@ -103,11 +108,15 @@
103 108
104#define EXYNOS4_PA_EHCI 0x12580000 109#define EXYNOS4_PA_EHCI 0x12580000
105#define EXYNOS4_PA_HSPHY 0x125B0000 110#define EXYNOS4_PA_HSPHY 0x125B0000
111#define EXYNOS4_PA_MFC 0x13400000
106 112
107#define EXYNOS4_PA_UART 0x13800000 113#define EXYNOS4_PA_UART 0x13800000
108 114
109#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) 115#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
110 116
117#define EXYNOS4_PA_ADC 0x13910000
118#define EXYNOS4_PA_ADC1 0x13911000
119
111#define EXYNOS4_PA_AC97 0x139A0000 120#define EXYNOS4_PA_AC97 0x139A0000
112 121
113#define EXYNOS4_PA_SPDIF 0x139B0000 122#define EXYNOS4_PA_SPDIF 0x139B0000
@@ -130,6 +139,8 @@
130#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5) 139#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
131#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6) 140#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
132#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) 141#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
142#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
143#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
133#define S3C_PA_RTC EXYNOS4_PA_RTC 144#define S3C_PA_RTC EXYNOS4_PA_RTC
134#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG 145#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
135 146
@@ -140,10 +151,12 @@
140#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3 151#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
141#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0 152#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
142#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1 153#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
154#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
143#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND 155#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
144#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA 156#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
145#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM 157#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
146#define S5P_PA_SROMC EXYNOS4_PA_SROMC 158#define S5P_PA_SROMC EXYNOS4_PA_SROMC
159#define S5P_PA_MFC EXYNOS4_PA_MFC
147#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON 160#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
148#define S5P_PA_TIMER EXYNOS4_PA_TIMER 161#define S5P_PA_TIMER EXYNOS4_PA_TIMER
149#define S5P_PA_EHCI EXYNOS4_PA_EHCI 162#define S5P_PA_EHCI EXYNOS4_PA_EHCI
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index f26e46bc06ca..1df3b81f96e8 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
47{ 47{
48 /* nothing here yet */ 48 /* nothing here yet */
49} 49}
50
51static inline void s3c_pm_restored_gpios(void)
52{
53 /* nothing here yet */
54}
55
56static inline void s3c_pm_saved_gpios(void)
57{
58 /* nothing here yet */
59}
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 000000000000..a952904b010e
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4210 - PMU(Power Management Unit) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_PMU_H
14#define __ASM_ARCH_PMU_H __FILE__
15
16enum sys_powerdown {
17 SYS_AFTR,
18 SYS_LPA,
19 SYS_SLEEP,
20 NUM_SYS_POWERDOWN,
21};
22
23extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
24
25#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos4/include/mach/regs-audss.h
new file mode 100644
index 000000000000..ca5a8b64218a
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
1/* arch/arm/mach-exynos4/include/mach/regs-audss.h
2 *
3 * Copyright (c) 2011 Samsung Electronics
4 * http://www.samsung.com
5 *
6 * Exynos4 Audio SubSystem clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_REGS_AUDSS_H
14#define __PLAT_REGS_AUDSS_H __FILE__
15
16#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
17
18#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1157f5..d493fdb422ff 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
25#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600) 25#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
26#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800) 26#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
27 27
28#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
29#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
30
28#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110) 31#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
29#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114) 32#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
30#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120) 33#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -33,7 +36,9 @@
33#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210) 36#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
34#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214) 37#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
35#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220) 38#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
39#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
36#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228) 40#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
41#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
37#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) 42#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
38#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) 43#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
39#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) 44#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
@@ -61,6 +66,7 @@
61#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C) 66#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
62#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560) 67#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
63#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) 68#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
69#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
64 70
65#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) 71#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
66#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) 72#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
@@ -120,6 +126,12 @@
120#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) 126#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
121#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) 127#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
122 128
129#define S5P_EPLLCON0_ENABLE_SHIFT (31)
130#define S5P_EPLLCON0_LOCKED_SHIFT (29)
131
132#define S5P_VPLLCON0_ENABLE_SHIFT (31)
133#define S5P_VPLLCON0_LOCKED_SHIFT (29)
134
123#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16) 135#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
124#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT) 136#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
125 137
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index a9643371f8e7..fa49bbb8e7b0 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -158,6 +158,7 @@
158#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) 158#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
159 159
160#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 160#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
161#define S5P_CORE_LOCAL_PWR_EN 0x3
161#define S5P_INT_LOCAL_PWR_EN 0x7 162#define S5P_INT_LOCAL_PWR_EN 0x7
162 163
163#define S5P_CHECK_SLEEP 0x00000BAD 164#define S5P_CHECK_SLEEP 0x00000BAD
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 02:14:51 -0500