4 files changed, 29 insertions, 8 deletions

diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d7a1e281ce7a..4c9adbd87eac 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -17,12 +17,25 @@
                 .endm
 
                 .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =gic_cpu_base_addr
+                mov     \tmp, #0
+
+                mrc     p15, 0, \base, c0, c0, 5
+                and     \base, \base, #3
+                cmp     \base, #0
+                beq     1f
+
+                ldr     \tmp, =gic_bank_offset
+                ldr     \tmp, [\tmp]
+                cmp     \base, #1
+                beq     1f
+
+                cmp     \base, #2
+                addeq   \tmp, \tmp, \tmp
+                addne   \tmp, \tmp, \tmp, LSL #1
+
+1:              ldr     \base, =gic_cpu_base_addr
                 ldr     \base, [\base]
-                mrc     p15, 0, \tmp, c0, c0, 5
-                and     \tmp, \tmp, #3
-                cmp     \tmp, #1
-                addeq   \base, \base, #EXYNOS4_GIC_BANK_OFFSET
+                add     \base, \base, \tmp
                 .endm
 
                 .macro  arch_ret_to_user, tmp1, tmp2
@@ -80,4 +93,10 @@
                 /* As above, this assumes that irqstat and base are preserved.. */
 
                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
+                bic     \irqnr, \irqstat, #0x1c00
+                mov     \tmp, #0
+                cmp     \irqnr, #28
+                moveq   \tmp, #1
+                streq   \irqstat, [\base, #GIC_CPU_EOI]
+                cmp     \tmp, #0
                 .endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index f8952f8f3757..2d3f6bcd9bc0 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,6 +19,8 @@
 
 #define IRQ_PPI(x)              S5P_IRQ(x+16)
 
+#define IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
+
 /* SPI: Shared Peripheral Interrupt */
 
 #define IRQ_SPI(x)              S5P_IRQ(x+32)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 7073ac730855..9f97eb8499ee 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -62,7 +62,6 @@
 
 #define EXYNOS4_PA_GIC_CPU              0x10480000
 #define EXYNOS4_PA_GIC_DIST             0x10490000
-#define EXYNOS4_GIC_BANK_OFFSET         0x8000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
 #define EXYNOS4_PA_TWD                  0x10500600
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
index ca9c8434b023..80dd02ad6d61 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-mct.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h
@@ -31,8 +31,9 @@
 #define EXYNOS4_MCT_G_INT_ENB           EXYNOS4_MCTREG(0x248)
 #define EXYNOS4_MCT_G_WSTAT             EXYNOS4_MCTREG(0x24C)
 
-#define EXYNOS4_MCT_L0_BASE             EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L1_BASE             EXYNOS4_MCTREG(0x400)
+#define _EXYNOS4_MCT_L_BASE             EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x)           (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK              (0xffffff00)
 
 #define MCT_L_TCNTB_OFFSET              (0x00)
 #define MCT_L_ICNTB_OFFSET              (0x08)