diff options
Diffstat (limited to 'arch/arm/mach-exynos4/clock.c')
-rw-r--r-- | arch/arm/mach-exynos4/clock.c | 238 |
1 files changed, 118 insertions, 120 deletions
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c index 871f9d508fde..851dea018578 100644 --- a/arch/arm/mach-exynos4/clock.c +++ b/arch/arm/mach-exynos4/clock.c | |||
@@ -27,24 +27,20 @@ | |||
27 | 27 | ||
28 | static struct clk clk_sclk_hdmi27m = { | 28 | static struct clk clk_sclk_hdmi27m = { |
29 | .name = "sclk_hdmi27m", | 29 | .name = "sclk_hdmi27m", |
30 | .id = -1, | ||
31 | .rate = 27000000, | 30 | .rate = 27000000, |
32 | }; | 31 | }; |
33 | 32 | ||
34 | static struct clk clk_sclk_hdmiphy = { | 33 | static struct clk clk_sclk_hdmiphy = { |
35 | .name = "sclk_hdmiphy", | 34 | .name = "sclk_hdmiphy", |
36 | .id = -1, | ||
37 | }; | 35 | }; |
38 | 36 | ||
39 | static struct clk clk_sclk_usbphy0 = { | 37 | static struct clk clk_sclk_usbphy0 = { |
40 | .name = "sclk_usbphy0", | 38 | .name = "sclk_usbphy0", |
41 | .id = -1, | ||
42 | .rate = 27000000, | 39 | .rate = 27000000, |
43 | }; | 40 | }; |
44 | 41 | ||
45 | static struct clk clk_sclk_usbphy1 = { | 42 | static struct clk clk_sclk_usbphy1 = { |
46 | .name = "sclk_usbphy1", | 43 | .name = "sclk_usbphy1", |
47 | .id = -1, | ||
48 | }; | 44 | }; |
49 | 45 | ||
50 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) | 46 | static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable) |
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable) | |||
132 | static struct clksrc_clk clk_mout_apll = { | 128 | static struct clksrc_clk clk_mout_apll = { |
133 | .clk = { | 129 | .clk = { |
134 | .name = "mout_apll", | 130 | .name = "mout_apll", |
135 | .id = -1, | ||
136 | }, | 131 | }, |
137 | .sources = &clk_src_apll, | 132 | .sources = &clk_src_apll, |
138 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, | 133 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, |
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = { | |||
141 | static struct clksrc_clk clk_sclk_apll = { | 136 | static struct clksrc_clk clk_sclk_apll = { |
142 | .clk = { | 137 | .clk = { |
143 | .name = "sclk_apll", | 138 | .name = "sclk_apll", |
144 | .id = -1, | ||
145 | .parent = &clk_mout_apll.clk, | 139 | .parent = &clk_mout_apll.clk, |
146 | }, | 140 | }, |
147 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, | 141 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, |
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = { | |||
150 | static struct clksrc_clk clk_mout_epll = { | 144 | static struct clksrc_clk clk_mout_epll = { |
151 | .clk = { | 145 | .clk = { |
152 | .name = "mout_epll", | 146 | .name = "mout_epll", |
153 | .id = -1, | ||
154 | }, | 147 | }, |
155 | .sources = &clk_src_epll, | 148 | .sources = &clk_src_epll, |
156 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, | 149 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, |
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = { | |||
159 | static struct clksrc_clk clk_mout_mpll = { | 152 | static struct clksrc_clk clk_mout_mpll = { |
160 | .clk = { | 153 | .clk = { |
161 | .name = "mout_mpll", | 154 | .name = "mout_mpll", |
162 | .id = -1, | ||
163 | }, | 155 | }, |
164 | .sources = &clk_src_mpll, | 156 | .sources = &clk_src_mpll, |
165 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, | 157 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, |
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = { | |||
178 | static struct clksrc_clk clk_moutcore = { | 170 | static struct clksrc_clk clk_moutcore = { |
179 | .clk = { | 171 | .clk = { |
180 | .name = "moutcore", | 172 | .name = "moutcore", |
181 | .id = -1, | ||
182 | }, | 173 | }, |
183 | .sources = &clkset_moutcore, | 174 | .sources = &clkset_moutcore, |
184 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, | 175 | .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 }, |
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = { | |||
187 | static struct clksrc_clk clk_coreclk = { | 178 | static struct clksrc_clk clk_coreclk = { |
188 | .clk = { | 179 | .clk = { |
189 | .name = "core_clk", | 180 | .name = "core_clk", |
190 | .id = -1, | ||
191 | .parent = &clk_moutcore.clk, | 181 | .parent = &clk_moutcore.clk, |
192 | }, | 182 | }, |
193 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, | 183 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 }, |
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = { | |||
196 | static struct clksrc_clk clk_armclk = { | 186 | static struct clksrc_clk clk_armclk = { |
197 | .clk = { | 187 | .clk = { |
198 | .name = "armclk", | 188 | .name = "armclk", |
199 | .id = -1, | ||
200 | .parent = &clk_coreclk.clk, | 189 | .parent = &clk_coreclk.clk, |
201 | }, | 190 | }, |
202 | }; | 191 | }; |
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = { | |||
204 | static struct clksrc_clk clk_aclk_corem0 = { | 193 | static struct clksrc_clk clk_aclk_corem0 = { |
205 | .clk = { | 194 | .clk = { |
206 | .name = "aclk_corem0", | 195 | .name = "aclk_corem0", |
207 | .id = -1, | ||
208 | .parent = &clk_coreclk.clk, | 196 | .parent = &clk_coreclk.clk, |
209 | }, | 197 | }, |
210 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, | 198 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, |
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = { | |||
213 | static struct clksrc_clk clk_aclk_cores = { | 201 | static struct clksrc_clk clk_aclk_cores = { |
214 | .clk = { | 202 | .clk = { |
215 | .name = "aclk_cores", | 203 | .name = "aclk_cores", |
216 | .id = -1, | ||
217 | .parent = &clk_coreclk.clk, | 204 | .parent = &clk_coreclk.clk, |
218 | }, | 205 | }, |
219 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, | 206 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 }, |
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = { | |||
222 | static struct clksrc_clk clk_aclk_corem1 = { | 209 | static struct clksrc_clk clk_aclk_corem1 = { |
223 | .clk = { | 210 | .clk = { |
224 | .name = "aclk_corem1", | 211 | .name = "aclk_corem1", |
225 | .id = -1, | ||
226 | .parent = &clk_coreclk.clk, | 212 | .parent = &clk_coreclk.clk, |
227 | }, | 213 | }, |
228 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, | 214 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 }, |
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = { | |||
231 | static struct clksrc_clk clk_periphclk = { | 217 | static struct clksrc_clk clk_periphclk = { |
232 | .clk = { | 218 | .clk = { |
233 | .name = "periphclk", | 219 | .name = "periphclk", |
234 | .id = -1, | ||
235 | .parent = &clk_coreclk.clk, | 220 | .parent = &clk_coreclk.clk, |
236 | }, | 221 | }, |
237 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, | 222 | .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 }, |
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = { | |||
252 | static struct clksrc_clk clk_mout_corebus = { | 237 | static struct clksrc_clk clk_mout_corebus = { |
253 | .clk = { | 238 | .clk = { |
254 | .name = "mout_corebus", | 239 | .name = "mout_corebus", |
255 | .id = -1, | ||
256 | }, | 240 | }, |
257 | .sources = &clkset_mout_corebus, | 241 | .sources = &clkset_mout_corebus, |
258 | .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, | 242 | .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 }, |
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = { | |||
261 | static struct clksrc_clk clk_sclk_dmc = { | 245 | static struct clksrc_clk clk_sclk_dmc = { |
262 | .clk = { | 246 | .clk = { |
263 | .name = "sclk_dmc", | 247 | .name = "sclk_dmc", |
264 | .id = -1, | ||
265 | .parent = &clk_mout_corebus.clk, | 248 | .parent = &clk_mout_corebus.clk, |
266 | }, | 249 | }, |
267 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, | 250 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 }, |
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = { | |||
270 | static struct clksrc_clk clk_aclk_cored = { | 253 | static struct clksrc_clk clk_aclk_cored = { |
271 | .clk = { | 254 | .clk = { |
272 | .name = "aclk_cored", | 255 | .name = "aclk_cored", |
273 | .id = -1, | ||
274 | .parent = &clk_sclk_dmc.clk, | 256 | .parent = &clk_sclk_dmc.clk, |
275 | }, | 257 | }, |
276 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, | 258 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 }, |
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = { | |||
279 | static struct clksrc_clk clk_aclk_corep = { | 261 | static struct clksrc_clk clk_aclk_corep = { |
280 | .clk = { | 262 | .clk = { |
281 | .name = "aclk_corep", | 263 | .name = "aclk_corep", |
282 | .id = -1, | ||
283 | .parent = &clk_aclk_cored.clk, | 264 | .parent = &clk_aclk_cored.clk, |
284 | }, | 265 | }, |
285 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, | 266 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 }, |
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = { | |||
288 | static struct clksrc_clk clk_aclk_acp = { | 269 | static struct clksrc_clk clk_aclk_acp = { |
289 | .clk = { | 270 | .clk = { |
290 | .name = "aclk_acp", | 271 | .name = "aclk_acp", |
291 | .id = -1, | ||
292 | .parent = &clk_mout_corebus.clk, | 272 | .parent = &clk_mout_corebus.clk, |
293 | }, | 273 | }, |
294 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, | 274 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 }, |
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = { | |||
297 | static struct clksrc_clk clk_pclk_acp = { | 277 | static struct clksrc_clk clk_pclk_acp = { |
298 | .clk = { | 278 | .clk = { |
299 | .name = "pclk_acp", | 279 | .name = "pclk_acp", |
300 | .id = -1, | ||
301 | .parent = &clk_aclk_acp.clk, | 280 | .parent = &clk_aclk_acp.clk, |
302 | }, | 281 | }, |
303 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, | 282 | .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 }, |
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = { | |||
318 | static struct clksrc_clk clk_aclk_200 = { | 297 | static struct clksrc_clk clk_aclk_200 = { |
319 | .clk = { | 298 | .clk = { |
320 | .name = "aclk_200", | 299 | .name = "aclk_200", |
321 | .id = -1, | ||
322 | }, | 300 | }, |
323 | .sources = &clkset_aclk, | 301 | .sources = &clkset_aclk, |
324 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, | 302 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 }, |
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = { | |||
328 | static struct clksrc_clk clk_aclk_100 = { | 306 | static struct clksrc_clk clk_aclk_100 = { |
329 | .clk = { | 307 | .clk = { |
330 | .name = "aclk_100", | 308 | .name = "aclk_100", |
331 | .id = -1, | ||
332 | }, | 309 | }, |
333 | .sources = &clkset_aclk, | 310 | .sources = &clkset_aclk, |
334 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, | 311 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 }, |
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = { | |||
338 | static struct clksrc_clk clk_aclk_160 = { | 315 | static struct clksrc_clk clk_aclk_160 = { |
339 | .clk = { | 316 | .clk = { |
340 | .name = "aclk_160", | 317 | .name = "aclk_160", |
341 | .id = -1, | ||
342 | }, | 318 | }, |
343 | .sources = &clkset_aclk, | 319 | .sources = &clkset_aclk, |
344 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, | 320 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 }, |
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = { | |||
348 | static struct clksrc_clk clk_aclk_133 = { | 324 | static struct clksrc_clk clk_aclk_133 = { |
349 | .clk = { | 325 | .clk = { |
350 | .name = "aclk_133", | 326 | .name = "aclk_133", |
351 | .id = -1, | ||
352 | }, | 327 | }, |
353 | .sources = &clkset_aclk, | 328 | .sources = &clkset_aclk, |
354 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, | 329 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 }, |
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = { | |||
368 | static struct clksrc_clk clk_vpllsrc = { | 343 | static struct clksrc_clk clk_vpllsrc = { |
369 | .clk = { | 344 | .clk = { |
370 | .name = "vpll_src", | 345 | .name = "vpll_src", |
371 | .id = -1, | ||
372 | .enable = exynos4_clksrc_mask_top_ctrl, | 346 | .enable = exynos4_clksrc_mask_top_ctrl, |
373 | .ctrlbit = (1 << 0), | 347 | .ctrlbit = (1 << 0), |
374 | }, | 348 | }, |
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = { | |||
389 | static struct clksrc_clk clk_sclk_vpll = { | 363 | static struct clksrc_clk clk_sclk_vpll = { |
390 | .clk = { | 364 | .clk = { |
391 | .name = "sclk_vpll", | 365 | .name = "sclk_vpll", |
392 | .id = -1, | ||
393 | }, | 366 | }, |
394 | .sources = &clkset_sclk_vpll, | 367 | .sources = &clkset_sclk_vpll, |
395 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, | 368 | .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 }, |
@@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = { | |||
398 | static struct clk init_clocks_off[] = { | 371 | static struct clk init_clocks_off[] = { |
399 | { | 372 | { |
400 | .name = "timers", | 373 | .name = "timers", |
401 | .id = -1, | ||
402 | .parent = &clk_aclk_100.clk, | 374 | .parent = &clk_aclk_100.clk, |
403 | .enable = exynos4_clk_ip_peril_ctrl, | 375 | .enable = exynos4_clk_ip_peril_ctrl, |
404 | .ctrlbit = (1<<24), | 376 | .ctrlbit = (1<<24), |
405 | }, { | 377 | }, { |
406 | .name = "csis", | 378 | .name = "csis", |
407 | .id = 0, | 379 | .devname = "s5p-mipi-csis.0", |
408 | .enable = exynos4_clk_ip_cam_ctrl, | 380 | .enable = exynos4_clk_ip_cam_ctrl, |
409 | .ctrlbit = (1 << 4), | 381 | .ctrlbit = (1 << 4), |
410 | }, { | 382 | }, { |
411 | .name = "csis", | 383 | .name = "csis", |
412 | .id = 1, | 384 | .devname = "s5p-mipi-csis.1", |
413 | .enable = exynos4_clk_ip_cam_ctrl, | 385 | .enable = exynos4_clk_ip_cam_ctrl, |
414 | .ctrlbit = (1 << 5), | 386 | .ctrlbit = (1 << 5), |
415 | }, { | 387 | }, { |
416 | .name = "fimc", | 388 | .name = "fimc", |
417 | .id = 0, | 389 | .devname = "exynos4-fimc.0", |
418 | .enable = exynos4_clk_ip_cam_ctrl, | 390 | .enable = exynos4_clk_ip_cam_ctrl, |
419 | .ctrlbit = (1 << 0), | 391 | .ctrlbit = (1 << 0), |
420 | }, { | 392 | }, { |
421 | .name = "fimc", | 393 | .name = "fimc", |
422 | .id = 1, | 394 | .devname = "exynos4-fimc.1", |
423 | .enable = exynos4_clk_ip_cam_ctrl, | 395 | .enable = exynos4_clk_ip_cam_ctrl, |
424 | .ctrlbit = (1 << 1), | 396 | .ctrlbit = (1 << 1), |
425 | }, { | 397 | }, { |
426 | .name = "fimc", | 398 | .name = "fimc", |
427 | .id = 2, | 399 | .devname = "exynos4-fimc.2", |
428 | .enable = exynos4_clk_ip_cam_ctrl, | 400 | .enable = exynos4_clk_ip_cam_ctrl, |
429 | .ctrlbit = (1 << 2), | 401 | .ctrlbit = (1 << 2), |
430 | }, { | 402 | }, { |
431 | .name = "fimc", | 403 | .name = "fimc", |
432 | .id = 3, | 404 | .devname = "exynos4-fimc.3", |
433 | .enable = exynos4_clk_ip_cam_ctrl, | 405 | .enable = exynos4_clk_ip_cam_ctrl, |
434 | .ctrlbit = (1 << 3), | 406 | .ctrlbit = (1 << 3), |
435 | }, { | 407 | }, { |
436 | .name = "fimd", | 408 | .name = "fimd", |
437 | .id = 0, | 409 | .devname = "exynos4-fb.0", |
438 | .enable = exynos4_clk_ip_lcd0_ctrl, | 410 | .enable = exynos4_clk_ip_lcd0_ctrl, |
439 | .ctrlbit = (1 << 0), | 411 | .ctrlbit = (1 << 0), |
440 | }, { | 412 | }, { |
441 | .name = "fimd", | 413 | .name = "fimd", |
442 | .id = 1, | 414 | .devname = "exynos4-fb.1", |
443 | .enable = exynos4_clk_ip_lcd1_ctrl, | 415 | .enable = exynos4_clk_ip_lcd1_ctrl, |
444 | .ctrlbit = (1 << 0), | 416 | .ctrlbit = (1 << 0), |
445 | }, { | 417 | }, { |
446 | .name = "sataphy", | 418 | .name = "sataphy", |
447 | .id = -1, | ||
448 | .parent = &clk_aclk_133.clk, | 419 | .parent = &clk_aclk_133.clk, |
449 | .enable = exynos4_clk_ip_fsys_ctrl, | 420 | .enable = exynos4_clk_ip_fsys_ctrl, |
450 | .ctrlbit = (1 << 3), | 421 | .ctrlbit = (1 << 3), |
451 | }, { | 422 | }, { |
452 | .name = "hsmmc", | 423 | .name = "hsmmc", |
453 | .id = 0, | 424 | .devname = "s3c-sdhci.0", |
454 | .parent = &clk_aclk_133.clk, | 425 | .parent = &clk_aclk_133.clk, |
455 | .enable = exynos4_clk_ip_fsys_ctrl, | 426 | .enable = exynos4_clk_ip_fsys_ctrl, |
456 | .ctrlbit = (1 << 5), | 427 | .ctrlbit = (1 << 5), |
457 | }, { | 428 | }, { |
458 | .name = "hsmmc", | 429 | .name = "hsmmc", |
459 | .id = 1, | 430 | .devname = "s3c-sdhci.1", |
460 | .parent = &clk_aclk_133.clk, | 431 | .parent = &clk_aclk_133.clk, |
461 | .enable = exynos4_clk_ip_fsys_ctrl, | 432 | .enable = exynos4_clk_ip_fsys_ctrl, |
462 | .ctrlbit = (1 << 6), | 433 | .ctrlbit = (1 << 6), |
463 | }, { | 434 | }, { |
464 | .name = "hsmmc", | 435 | .name = "hsmmc", |
465 | .id = 2, | 436 | .devname = "s3c-sdhci.2", |
466 | .parent = &clk_aclk_133.clk, | 437 | .parent = &clk_aclk_133.clk, |
467 | .enable = exynos4_clk_ip_fsys_ctrl, | 438 | .enable = exynos4_clk_ip_fsys_ctrl, |
468 | .ctrlbit = (1 << 7), | 439 | .ctrlbit = (1 << 7), |
469 | }, { | 440 | }, { |
470 | .name = "hsmmc", | 441 | .name = "hsmmc", |
471 | .id = 3, | 442 | .devname = "s3c-sdhci.3", |
472 | .parent = &clk_aclk_133.clk, | 443 | .parent = &clk_aclk_133.clk, |
473 | .enable = exynos4_clk_ip_fsys_ctrl, | 444 | .enable = exynos4_clk_ip_fsys_ctrl, |
474 | .ctrlbit = (1 << 8), | 445 | .ctrlbit = (1 << 8), |
475 | }, { | 446 | }, { |
476 | .name = "hsmmc", | 447 | .name = "dwmmc", |
477 | .id = 4, | ||
478 | .parent = &clk_aclk_133.clk, | 448 | .parent = &clk_aclk_133.clk, |
479 | .enable = exynos4_clk_ip_fsys_ctrl, | 449 | .enable = exynos4_clk_ip_fsys_ctrl, |
480 | .ctrlbit = (1 << 9), | 450 | .ctrlbit = (1 << 9), |
481 | }, { | 451 | }, { |
482 | .name = "sata", | 452 | .name = "sata", |
483 | .id = -1, | ||
484 | .parent = &clk_aclk_133.clk, | 453 | .parent = &clk_aclk_133.clk, |
485 | .enable = exynos4_clk_ip_fsys_ctrl, | 454 | .enable = exynos4_clk_ip_fsys_ctrl, |
486 | .ctrlbit = (1 << 10), | 455 | .ctrlbit = (1 << 10), |
487 | }, { | 456 | }, { |
488 | .name = "pdma", | 457 | .name = "pdma", |
489 | .id = 0, | 458 | .devname = "s3c-pl330.0", |
490 | .enable = exynos4_clk_ip_fsys_ctrl, | 459 | .enable = exynos4_clk_ip_fsys_ctrl, |
491 | .ctrlbit = (1 << 0), | 460 | .ctrlbit = (1 << 0), |
492 | }, { | 461 | }, { |
493 | .name = "pdma", | 462 | .name = "pdma", |
494 | .id = 1, | 463 | .devname = "s3c-pl330.1", |
495 | .enable = exynos4_clk_ip_fsys_ctrl, | 464 | .enable = exynos4_clk_ip_fsys_ctrl, |
496 | .ctrlbit = (1 << 1), | 465 | .ctrlbit = (1 << 1), |
497 | }, { | 466 | }, { |
498 | .name = "adc", | 467 | .name = "adc", |
499 | .id = -1, | ||
500 | .enable = exynos4_clk_ip_peril_ctrl, | 468 | .enable = exynos4_clk_ip_peril_ctrl, |
501 | .ctrlbit = (1 << 15), | 469 | .ctrlbit = (1 << 15), |
502 | }, { | 470 | }, { |
503 | .name = "keypad", | 471 | .name = "keypad", |
504 | .id = -1, | ||
505 | .enable = exynos4_clk_ip_perir_ctrl, | 472 | .enable = exynos4_clk_ip_perir_ctrl, |
506 | .ctrlbit = (1 << 16), | 473 | .ctrlbit = (1 << 16), |
507 | }, { | 474 | }, { |
508 | .name = "rtc", | 475 | .name = "rtc", |
509 | .id = -1, | ||
510 | .enable = exynos4_clk_ip_perir_ctrl, | 476 | .enable = exynos4_clk_ip_perir_ctrl, |
511 | .ctrlbit = (1 << 15), | 477 | .ctrlbit = (1 << 15), |
512 | }, { | 478 | }, { |
513 | .name = "watchdog", | 479 | .name = "watchdog", |
514 | .id = -1, | ||
515 | .parent = &clk_aclk_100.clk, | 480 | .parent = &clk_aclk_100.clk, |
516 | .enable = exynos4_clk_ip_perir_ctrl, | 481 | .enable = exynos4_clk_ip_perir_ctrl, |
517 | .ctrlbit = (1 << 14), | 482 | .ctrlbit = (1 << 14), |
518 | }, { | 483 | }, { |
519 | .name = "usbhost", | 484 | .name = "usbhost", |
520 | .id = -1, | ||
521 | .enable = exynos4_clk_ip_fsys_ctrl , | 485 | .enable = exynos4_clk_ip_fsys_ctrl , |
522 | .ctrlbit = (1 << 12), | 486 | .ctrlbit = (1 << 12), |
523 | }, { | 487 | }, { |
524 | .name = "otg", | 488 | .name = "otg", |
525 | .id = -1, | ||
526 | .enable = exynos4_clk_ip_fsys_ctrl, | 489 | .enable = exynos4_clk_ip_fsys_ctrl, |
527 | .ctrlbit = (1 << 13), | 490 | .ctrlbit = (1 << 13), |
528 | }, { | 491 | }, { |
529 | .name = "spi", | 492 | .name = "spi", |
530 | .id = 0, | 493 | .devname = "s3c64xx-spi.0", |
531 | .enable = exynos4_clk_ip_peril_ctrl, | 494 | .enable = exynos4_clk_ip_peril_ctrl, |
532 | .ctrlbit = (1 << 16), | 495 | .ctrlbit = (1 << 16), |
533 | }, { | 496 | }, { |
534 | .name = "spi", | 497 | .name = "spi", |
535 | .id = 1, | 498 | .devname = "s3c64xx-spi.1", |
536 | .enable = exynos4_clk_ip_peril_ctrl, | 499 | .enable = exynos4_clk_ip_peril_ctrl, |
537 | .ctrlbit = (1 << 17), | 500 | .ctrlbit = (1 << 17), |
538 | }, { | 501 | }, { |
539 | .name = "spi", | 502 | .name = "spi", |
540 | .id = 2, | 503 | .devname = "s3c64xx-spi.2", |
541 | .enable = exynos4_clk_ip_peril_ctrl, | 504 | .enable = exynos4_clk_ip_peril_ctrl, |
542 | .ctrlbit = (1 << 18), | 505 | .ctrlbit = (1 << 18), |
543 | }, { | 506 | }, { |
544 | .name = "iis", | 507 | .name = "iis", |
545 | .id = 0, | 508 | .devname = "samsung-i2s.0", |
546 | .enable = exynos4_clk_ip_peril_ctrl, | 509 | .enable = exynos4_clk_ip_peril_ctrl, |
547 | .ctrlbit = (1 << 19), | 510 | .ctrlbit = (1 << 19), |
548 | }, { | 511 | }, { |
549 | .name = "iis", | 512 | .name = "iis", |
550 | .id = 1, | 513 | .devname = "samsung-i2s.1", |
551 | .enable = exynos4_clk_ip_peril_ctrl, | 514 | .enable = exynos4_clk_ip_peril_ctrl, |
552 | .ctrlbit = (1 << 20), | 515 | .ctrlbit = (1 << 20), |
553 | }, { | 516 | }, { |
554 | .name = "iis", | 517 | .name = "iis", |
555 | .id = 2, | 518 | .devname = "samsung-i2s.2", |
556 | .enable = exynos4_clk_ip_peril_ctrl, | 519 | .enable = exynos4_clk_ip_peril_ctrl, |
557 | .ctrlbit = (1 << 21), | 520 | .ctrlbit = (1 << 21), |
558 | }, { | 521 | }, { |
@@ -562,125 +525,115 @@ static struct clk init_clocks_off[] = { | |||
562 | .ctrlbit = (1 << 27), | 525 | .ctrlbit = (1 << 27), |
563 | }, { | 526 | }, { |
564 | .name = "fimg2d", | 527 | .name = "fimg2d", |
565 | .id = -1, | ||
566 | .enable = exynos4_clk_ip_image_ctrl, | 528 | .enable = exynos4_clk_ip_image_ctrl, |
567 | .ctrlbit = (1 << 0), | 529 | .ctrlbit = (1 << 0), |
568 | }, { | 530 | }, { |
531 | .name = "mfc", | ||
532 | .devname = "s5p-mfc", | ||
533 | .enable = exynos4_clk_ip_mfc_ctrl, | ||
534 | .ctrlbit = (1 << 0), | ||
535 | }, { | ||
569 | .name = "i2c", | 536 | .name = "i2c", |
570 | .id = 0, | 537 | .devname = "s3c2440-i2c.0", |
571 | .parent = &clk_aclk_100.clk, | 538 | .parent = &clk_aclk_100.clk, |
572 | .enable = exynos4_clk_ip_peril_ctrl, | 539 | .enable = exynos4_clk_ip_peril_ctrl, |
573 | .ctrlbit = (1 << 6), | 540 | .ctrlbit = (1 << 6), |
574 | }, { | 541 | }, { |
575 | .name = "i2c", | 542 | .name = "i2c", |
576 | .id = 1, | 543 | .devname = "s3c2440-i2c.1", |
577 | .parent = &clk_aclk_100.clk, | 544 | .parent = &clk_aclk_100.clk, |
578 | .enable = exynos4_clk_ip_peril_ctrl, | 545 | .enable = exynos4_clk_ip_peril_ctrl, |
579 | .ctrlbit = (1 << 7), | 546 | .ctrlbit = (1 << 7), |
580 | }, { | 547 | }, { |
581 | .name = "i2c", | 548 | .name = "i2c", |
582 | .id = 2, | 549 | .devname = "s3c2440-i2c.2", |
583 | .parent = &clk_aclk_100.clk, | 550 | .parent = &clk_aclk_100.clk, |
584 | .enable = exynos4_clk_ip_peril_ctrl, | 551 | .enable = exynos4_clk_ip_peril_ctrl, |
585 | .ctrlbit = (1 << 8), | 552 | .ctrlbit = (1 << 8), |
586 | }, { | 553 | }, { |
587 | .name = "i2c", | 554 | .name = "i2c", |
588 | .id = 3, | 555 | .devname = "s3c2440-i2c.3", |
589 | .parent = &clk_aclk_100.clk, | 556 | .parent = &clk_aclk_100.clk, |
590 | .enable = exynos4_clk_ip_peril_ctrl, | 557 | .enable = exynos4_clk_ip_peril_ctrl, |
591 | .ctrlbit = (1 << 9), | 558 | .ctrlbit = (1 << 9), |
592 | }, { | 559 | }, { |
593 | .name = "i2c", | 560 | .name = "i2c", |
594 | .id = 4, | 561 | .devname = "s3c2440-i2c.4", |
595 | .parent = &clk_aclk_100.clk, | 562 | .parent = &clk_aclk_100.clk, |
596 | .enable = exynos4_clk_ip_peril_ctrl, | 563 | .enable = exynos4_clk_ip_peril_ctrl, |
597 | .ctrlbit = (1 << 10), | 564 | .ctrlbit = (1 << 10), |
598 | }, { | 565 | }, { |
599 | .name = "i2c", | 566 | .name = "i2c", |
600 | .id = 5, | 567 | .devname = "s3c2440-i2c.5", |
601 | .parent = &clk_aclk_100.clk, | 568 | .parent = &clk_aclk_100.clk, |
602 | .enable = exynos4_clk_ip_peril_ctrl, | 569 | .enable = exynos4_clk_ip_peril_ctrl, |
603 | .ctrlbit = (1 << 11), | 570 | .ctrlbit = (1 << 11), |
604 | }, { | 571 | }, { |
605 | .name = "i2c", | 572 | .name = "i2c", |
606 | .id = 6, | 573 | .devname = "s3c2440-i2c.6", |
607 | .parent = &clk_aclk_100.clk, | 574 | .parent = &clk_aclk_100.clk, |
608 | .enable = exynos4_clk_ip_peril_ctrl, | 575 | .enable = exynos4_clk_ip_peril_ctrl, |
609 | .ctrlbit = (1 << 12), | 576 | .ctrlbit = (1 << 12), |
610 | }, { | 577 | }, { |
611 | .name = "i2c", | 578 | .name = "i2c", |
612 | .id = 7, | 579 | .devname = "s3c2440-i2c.7", |
613 | .parent = &clk_aclk_100.clk, | 580 | .parent = &clk_aclk_100.clk, |
614 | .enable = exynos4_clk_ip_peril_ctrl, | 581 | .enable = exynos4_clk_ip_peril_ctrl, |
615 | .ctrlbit = (1 << 13), | 582 | .ctrlbit = (1 << 13), |
616 | }, { | 583 | }, { |
617 | .name = "SYSMMU_MDMA", | 584 | .name = "SYSMMU_MDMA", |
618 | .id = -1, | ||
619 | .enable = exynos4_clk_ip_image_ctrl, | 585 | .enable = exynos4_clk_ip_image_ctrl, |
620 | .ctrlbit = (1 << 5), | 586 | .ctrlbit = (1 << 5), |
621 | }, { | 587 | }, { |
622 | .name = "SYSMMU_FIMC0", | 588 | .name = "SYSMMU_FIMC0", |
623 | .id = -1, | ||
624 | .enable = exynos4_clk_ip_cam_ctrl, | 589 | .enable = exynos4_clk_ip_cam_ctrl, |
625 | .ctrlbit = (1 << 7), | 590 | .ctrlbit = (1 << 7), |
626 | }, { | 591 | }, { |
627 | .name = "SYSMMU_FIMC1", | 592 | .name = "SYSMMU_FIMC1", |
628 | .id = -1, | ||
629 | .enable = exynos4_clk_ip_cam_ctrl, | 593 | .enable = exynos4_clk_ip_cam_ctrl, |
630 | .ctrlbit = (1 << 8), | 594 | .ctrlbit = (1 << 8), |
631 | }, { | 595 | }, { |
632 | .name = "SYSMMU_FIMC2", | 596 | .name = "SYSMMU_FIMC2", |
633 | .id = -1, | ||
634 | .enable = exynos4_clk_ip_cam_ctrl, | 597 | .enable = exynos4_clk_ip_cam_ctrl, |
635 | .ctrlbit = (1 << 9), | 598 | .ctrlbit = (1 << 9), |
636 | }, { | 599 | }, { |
637 | .name = "SYSMMU_FIMC3", | 600 | .name = "SYSMMU_FIMC3", |
638 | .id = -1, | ||
639 | .enable = exynos4_clk_ip_cam_ctrl, | 601 | .enable = exynos4_clk_ip_cam_ctrl, |
640 | .ctrlbit = (1 << 10), | 602 | .ctrlbit = (1 << 10), |
641 | }, { | 603 | }, { |
642 | .name = "SYSMMU_JPEG", | 604 | .name = "SYSMMU_JPEG", |
643 | .id = -1, | ||
644 | .enable = exynos4_clk_ip_cam_ctrl, | 605 | .enable = exynos4_clk_ip_cam_ctrl, |
645 | .ctrlbit = (1 << 11), | 606 | .ctrlbit = (1 << 11), |
646 | }, { | 607 | }, { |
647 | .name = "SYSMMU_FIMD0", | 608 | .name = "SYSMMU_FIMD0", |
648 | .id = -1, | ||
649 | .enable = exynos4_clk_ip_lcd0_ctrl, | 609 | .enable = exynos4_clk_ip_lcd0_ctrl, |
650 | .ctrlbit = (1 << 4), | 610 | .ctrlbit = (1 << 4), |
651 | }, { | 611 | }, { |
652 | .name = "SYSMMU_FIMD1", | 612 | .name = "SYSMMU_FIMD1", |
653 | .id = -1, | ||
654 | .enable = exynos4_clk_ip_lcd1_ctrl, | 613 | .enable = exynos4_clk_ip_lcd1_ctrl, |
655 | .ctrlbit = (1 << 4), | 614 | .ctrlbit = (1 << 4), |
656 | }, { | 615 | }, { |
657 | .name = "SYSMMU_PCIe", | 616 | .name = "SYSMMU_PCIe", |
658 | .id = -1, | ||
659 | .enable = exynos4_clk_ip_fsys_ctrl, | 617 | .enable = exynos4_clk_ip_fsys_ctrl, |
660 | .ctrlbit = (1 << 18), | 618 | .ctrlbit = (1 << 18), |
661 | }, { | 619 | }, { |
662 | .name = "SYSMMU_G2D", | 620 | .name = "SYSMMU_G2D", |
663 | .id = -1, | ||
664 | .enable = exynos4_clk_ip_image_ctrl, | 621 | .enable = exynos4_clk_ip_image_ctrl, |
665 | .ctrlbit = (1 << 3), | 622 | .ctrlbit = (1 << 3), |
666 | }, { | 623 | }, { |
667 | .name = "SYSMMU_ROTATOR", | 624 | .name = "SYSMMU_ROTATOR", |
668 | .id = -1, | ||
669 | .enable = exynos4_clk_ip_image_ctrl, | 625 | .enable = exynos4_clk_ip_image_ctrl, |
670 | .ctrlbit = (1 << 4), | 626 | .ctrlbit = (1 << 4), |
671 | }, { | 627 | }, { |
672 | .name = "SYSMMU_TV", | 628 | .name = "SYSMMU_TV", |
673 | .id = -1, | ||
674 | .enable = exynos4_clk_ip_tv_ctrl, | 629 | .enable = exynos4_clk_ip_tv_ctrl, |
675 | .ctrlbit = (1 << 4), | 630 | .ctrlbit = (1 << 4), |
676 | }, { | 631 | }, { |
677 | .name = "SYSMMU_MFC_L", | 632 | .name = "SYSMMU_MFC_L", |
678 | .id = -1, | ||
679 | .enable = exynos4_clk_ip_mfc_ctrl, | 633 | .enable = exynos4_clk_ip_mfc_ctrl, |
680 | .ctrlbit = (1 << 1), | 634 | .ctrlbit = (1 << 1), |
681 | }, { | 635 | }, { |
682 | .name = "SYSMMU_MFC_R", | 636 | .name = "SYSMMU_MFC_R", |
683 | .id = -1, | ||
684 | .enable = exynos4_clk_ip_mfc_ctrl, | 637 | .enable = exynos4_clk_ip_mfc_ctrl, |
685 | .ctrlbit = (1 << 2), | 638 | .ctrlbit = (1 << 2), |
686 | } | 639 | } |
@@ -689,32 +642,32 @@ static struct clk init_clocks_off[] = { | |||
689 | static struct clk init_clocks[] = { | 642 | static struct clk init_clocks[] = { |
690 | { | 643 | { |
691 | .name = "uart", | 644 | .name = "uart", |
692 | .id = 0, | 645 | .devname = "s5pv210-uart.0", |
693 | .enable = exynos4_clk_ip_peril_ctrl, | 646 | .enable = exynos4_clk_ip_peril_ctrl, |
694 | .ctrlbit = (1 << 0), | 647 | .ctrlbit = (1 << 0), |
695 | }, { | 648 | }, { |
696 | .name = "uart", | 649 | .name = "uart", |
697 | .id = 1, | 650 | .devname = "s5pv210-uart.1", |
698 | .enable = exynos4_clk_ip_peril_ctrl, | 651 | .enable = exynos4_clk_ip_peril_ctrl, |
699 | .ctrlbit = (1 << 1), | 652 | .ctrlbit = (1 << 1), |
700 | }, { | 653 | }, { |
701 | .name = "uart", | 654 | .name = "uart", |
702 | .id = 2, | 655 | .devname = "s5pv210-uart.2", |
703 | .enable = exynos4_clk_ip_peril_ctrl, | 656 | .enable = exynos4_clk_ip_peril_ctrl, |
704 | .ctrlbit = (1 << 2), | 657 | .ctrlbit = (1 << 2), |
705 | }, { | 658 | }, { |
706 | .name = "uart", | 659 | .name = "uart", |
707 | .id = 3, | 660 | .devname = "s5pv210-uart.3", |
708 | .enable = exynos4_clk_ip_peril_ctrl, | 661 | .enable = exynos4_clk_ip_peril_ctrl, |
709 | .ctrlbit = (1 << 3), | 662 | .ctrlbit = (1 << 3), |
710 | }, { | 663 | }, { |
711 | .name = "uart", | 664 | .name = "uart", |
712 | .id = 4, | 665 | .devname = "s5pv210-uart.4", |
713 | .enable = exynos4_clk_ip_peril_ctrl, | 666 | .enable = exynos4_clk_ip_peril_ctrl, |
714 | .ctrlbit = (1 << 4), | 667 | .ctrlbit = (1 << 4), |
715 | }, { | 668 | }, { |
716 | .name = "uart", | 669 | .name = "uart", |
717 | .id = 5, | 670 | .devname = "s5pv210-uart.5", |
718 | .enable = exynos4_clk_ip_peril_ctrl, | 671 | .enable = exynos4_clk_ip_peril_ctrl, |
719 | .ctrlbit = (1 << 5), | 672 | .ctrlbit = (1 << 5), |
720 | } | 673 | } |
@@ -750,7 +703,6 @@ static struct clksrc_sources clkset_mout_g2d0 = { | |||
750 | static struct clksrc_clk clk_mout_g2d0 = { | 703 | static struct clksrc_clk clk_mout_g2d0 = { |
751 | .clk = { | 704 | .clk = { |
752 | .name = "mout_g2d0", | 705 | .name = "mout_g2d0", |
753 | .id = -1, | ||
754 | }, | 706 | }, |
755 | .sources = &clkset_mout_g2d0, | 707 | .sources = &clkset_mout_g2d0, |
756 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, | 708 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 }, |
@@ -769,7 +721,6 @@ static struct clksrc_sources clkset_mout_g2d1 = { | |||
769 | static struct clksrc_clk clk_mout_g2d1 = { | 721 | static struct clksrc_clk clk_mout_g2d1 = { |
770 | .clk = { | 722 | .clk = { |
771 | .name = "mout_g2d1", | 723 | .name = "mout_g2d1", |
772 | .id = -1, | ||
773 | }, | 724 | }, |
774 | .sources = &clkset_mout_g2d1, | 725 | .sources = &clkset_mout_g2d1, |
775 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, | 726 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 }, |
@@ -785,10 +736,55 @@ static struct clksrc_sources clkset_mout_g2d = { | |||
785 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), | 736 | .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list), |
786 | }; | 737 | }; |
787 | 738 | ||
739 | static struct clk *clkset_mout_mfc0_list[] = { | ||
740 | [0] = &clk_mout_mpll.clk, | ||
741 | [1] = &clk_sclk_apll.clk, | ||
742 | }; | ||
743 | |||
744 | static struct clksrc_sources clkset_mout_mfc0 = { | ||
745 | .sources = clkset_mout_mfc0_list, | ||
746 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list), | ||
747 | }; | ||
748 | |||
749 | static struct clksrc_clk clk_mout_mfc0 = { | ||
750 | .clk = { | ||
751 | .name = "mout_mfc0", | ||
752 | }, | ||
753 | .sources = &clkset_mout_mfc0, | ||
754 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 }, | ||
755 | }; | ||
756 | |||
757 | static struct clk *clkset_mout_mfc1_list[] = { | ||
758 | [0] = &clk_mout_epll.clk, | ||
759 | [1] = &clk_sclk_vpll.clk, | ||
760 | }; | ||
761 | |||
762 | static struct clksrc_sources clkset_mout_mfc1 = { | ||
763 | .sources = clkset_mout_mfc1_list, | ||
764 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list), | ||
765 | }; | ||
766 | |||
767 | static struct clksrc_clk clk_mout_mfc1 = { | ||
768 | .clk = { | ||
769 | .name = "mout_mfc1", | ||
770 | }, | ||
771 | .sources = &clkset_mout_mfc1, | ||
772 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 }, | ||
773 | }; | ||
774 | |||
775 | static struct clk *clkset_mout_mfc_list[] = { | ||
776 | [0] = &clk_mout_mfc0.clk, | ||
777 | [1] = &clk_mout_mfc1.clk, | ||
778 | }; | ||
779 | |||
780 | static struct clksrc_sources clkset_mout_mfc = { | ||
781 | .sources = clkset_mout_mfc_list, | ||
782 | .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list), | ||
783 | }; | ||
784 | |||
788 | static struct clksrc_clk clk_dout_mmc0 = { | 785 | static struct clksrc_clk clk_dout_mmc0 = { |
789 | .clk = { | 786 | .clk = { |
790 | .name = "dout_mmc0", | 787 | .name = "dout_mmc0", |
791 | .id = -1, | ||
792 | }, | 788 | }, |
793 | .sources = &clkset_group, | 789 | .sources = &clkset_group, |
794 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, | 790 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 }, |
@@ -798,7 +794,6 @@ static struct clksrc_clk clk_dout_mmc0 = { | |||
798 | static struct clksrc_clk clk_dout_mmc1 = { | 794 | static struct clksrc_clk clk_dout_mmc1 = { |
799 | .clk = { | 795 | .clk = { |
800 | .name = "dout_mmc1", | 796 | .name = "dout_mmc1", |
801 | .id = -1, | ||
802 | }, | 797 | }, |
803 | .sources = &clkset_group, | 798 | .sources = &clkset_group, |
804 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, | 799 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 }, |
@@ -808,7 +803,6 @@ static struct clksrc_clk clk_dout_mmc1 = { | |||
808 | static struct clksrc_clk clk_dout_mmc2 = { | 803 | static struct clksrc_clk clk_dout_mmc2 = { |
809 | .clk = { | 804 | .clk = { |
810 | .name = "dout_mmc2", | 805 | .name = "dout_mmc2", |
811 | .id = -1, | ||
812 | }, | 806 | }, |
813 | .sources = &clkset_group, | 807 | .sources = &clkset_group, |
814 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, | 808 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 }, |
@@ -818,7 +812,6 @@ static struct clksrc_clk clk_dout_mmc2 = { | |||
818 | static struct clksrc_clk clk_dout_mmc3 = { | 812 | static struct clksrc_clk clk_dout_mmc3 = { |
819 | .clk = { | 813 | .clk = { |
820 | .name = "dout_mmc3", | 814 | .name = "dout_mmc3", |
821 | .id = -1, | ||
822 | }, | 815 | }, |
823 | .sources = &clkset_group, | 816 | .sources = &clkset_group, |
824 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, | 817 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 }, |
@@ -828,7 +821,6 @@ static struct clksrc_clk clk_dout_mmc3 = { | |||
828 | static struct clksrc_clk clk_dout_mmc4 = { | 821 | static struct clksrc_clk clk_dout_mmc4 = { |
829 | .clk = { | 822 | .clk = { |
830 | .name = "dout_mmc4", | 823 | .name = "dout_mmc4", |
831 | .id = -1, | ||
832 | }, | 824 | }, |
833 | .sources = &clkset_group, | 825 | .sources = &clkset_group, |
834 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, | 826 | .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 }, |
@@ -839,7 +831,7 @@ static struct clksrc_clk clksrcs[] = { | |||
839 | { | 831 | { |
840 | .clk = { | 832 | .clk = { |
841 | .name = "uclk1", | 833 | .name = "uclk1", |
842 | .id = 0, | 834 | .devname = "s5pv210-uart.0", |
843 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 835 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
844 | .ctrlbit = (1 << 0), | 836 | .ctrlbit = (1 << 0), |
845 | }, | 837 | }, |
@@ -849,7 +841,7 @@ static struct clksrc_clk clksrcs[] = { | |||
849 | }, { | 841 | }, { |
850 | .clk = { | 842 | .clk = { |
851 | .name = "uclk1", | 843 | .name = "uclk1", |
852 | .id = 1, | 844 | .devname = "s5pv210-uart.1", |
853 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 845 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
854 | .ctrlbit = (1 << 4), | 846 | .ctrlbit = (1 << 4), |
855 | }, | 847 | }, |
@@ -859,7 +851,7 @@ static struct clksrc_clk clksrcs[] = { | |||
859 | }, { | 851 | }, { |
860 | .clk = { | 852 | .clk = { |
861 | .name = "uclk1", | 853 | .name = "uclk1", |
862 | .id = 2, | 854 | .devname = "s5pv210-uart.2", |
863 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 855 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
864 | .ctrlbit = (1 << 8), | 856 | .ctrlbit = (1 << 8), |
865 | }, | 857 | }, |
@@ -869,7 +861,7 @@ static struct clksrc_clk clksrcs[] = { | |||
869 | }, { | 861 | }, { |
870 | .clk = { | 862 | .clk = { |
871 | .name = "uclk1", | 863 | .name = "uclk1", |
872 | .id = 3, | 864 | .devname = "s5pv210-uart.3", |
873 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 865 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
874 | .ctrlbit = (1 << 12), | 866 | .ctrlbit = (1 << 12), |
875 | }, | 867 | }, |
@@ -879,7 +871,6 @@ static struct clksrc_clk clksrcs[] = { | |||
879 | }, { | 871 | }, { |
880 | .clk = { | 872 | .clk = { |
881 | .name = "sclk_pwm", | 873 | .name = "sclk_pwm", |
882 | .id = -1, | ||
883 | .enable = exynos4_clksrc_mask_peril0_ctrl, | 874 | .enable = exynos4_clksrc_mask_peril0_ctrl, |
884 | .ctrlbit = (1 << 24), | 875 | .ctrlbit = (1 << 24), |
885 | }, | 876 | }, |
@@ -889,7 +880,7 @@ static struct clksrc_clk clksrcs[] = { | |||
889 | }, { | 880 | }, { |
890 | .clk = { | 881 | .clk = { |
891 | .name = "sclk_csis", | 882 | .name = "sclk_csis", |
892 | .id = 0, | 883 | .devname = "s5p-mipi-csis.0", |
893 | .enable = exynos4_clksrc_mask_cam_ctrl, | 884 | .enable = exynos4_clksrc_mask_cam_ctrl, |
894 | .ctrlbit = (1 << 24), | 885 | .ctrlbit = (1 << 24), |
895 | }, | 886 | }, |
@@ -899,7 +890,7 @@ static struct clksrc_clk clksrcs[] = { | |||
899 | }, { | 890 | }, { |
900 | .clk = { | 891 | .clk = { |
901 | .name = "sclk_csis", | 892 | .name = "sclk_csis", |
902 | .id = 1, | 893 | .devname = "s5p-mipi-csis.1", |
903 | .enable = exynos4_clksrc_mask_cam_ctrl, | 894 | .enable = exynos4_clksrc_mask_cam_ctrl, |
904 | .ctrlbit = (1 << 28), | 895 | .ctrlbit = (1 << 28), |
905 | }, | 896 | }, |
@@ -909,7 +900,7 @@ static struct clksrc_clk clksrcs[] = { | |||
909 | }, { | 900 | }, { |
910 | .clk = { | 901 | .clk = { |
911 | .name = "sclk_cam", | 902 | .name = "sclk_cam", |
912 | .id = 0, | 903 | .devname = "exynos4-fimc.0", |
913 | .enable = exynos4_clksrc_mask_cam_ctrl, | 904 | .enable = exynos4_clksrc_mask_cam_ctrl, |
914 | .ctrlbit = (1 << 16), | 905 | .ctrlbit = (1 << 16), |
915 | }, | 906 | }, |
@@ -919,7 +910,7 @@ static struct clksrc_clk clksrcs[] = { | |||
919 | }, { | 910 | }, { |
920 | .clk = { | 911 | .clk = { |
921 | .name = "sclk_cam", | 912 | .name = "sclk_cam", |
922 | .id = 1, | 913 | .devname = "exynos4-fimc.1", |
923 | .enable = exynos4_clksrc_mask_cam_ctrl, | 914 | .enable = exynos4_clksrc_mask_cam_ctrl, |
924 | .ctrlbit = (1 << 20), | 915 | .ctrlbit = (1 << 20), |
925 | }, | 916 | }, |
@@ -929,7 +920,7 @@ static struct clksrc_clk clksrcs[] = { | |||
929 | }, { | 920 | }, { |
930 | .clk = { | 921 | .clk = { |
931 | .name = "sclk_fimc", | 922 | .name = "sclk_fimc", |
932 | .id = 0, | 923 | .devname = "exynos4-fimc.0", |
933 | .enable = exynos4_clksrc_mask_cam_ctrl, | 924 | .enable = exynos4_clksrc_mask_cam_ctrl, |
934 | .ctrlbit = (1 << 0), | 925 | .ctrlbit = (1 << 0), |
935 | }, | 926 | }, |
@@ -939,7 +930,7 @@ static struct clksrc_clk clksrcs[] = { | |||
939 | }, { | 930 | }, { |
940 | .clk = { | 931 | .clk = { |
941 | .name = "sclk_fimc", | 932 | .name = "sclk_fimc", |
942 | .id = 1, | 933 | .devname = "exynos4-fimc.1", |
943 | .enable = exynos4_clksrc_mask_cam_ctrl, | 934 | .enable = exynos4_clksrc_mask_cam_ctrl, |
944 | .ctrlbit = (1 << 4), | 935 | .ctrlbit = (1 << 4), |
945 | }, | 936 | }, |
@@ -949,7 +940,7 @@ static struct clksrc_clk clksrcs[] = { | |||
949 | }, { | 940 | }, { |
950 | .clk = { | 941 | .clk = { |
951 | .name = "sclk_fimc", | 942 | .name = "sclk_fimc", |
952 | .id = 2, | 943 | .devname = "exynos4-fimc.2", |
953 | .enable = exynos4_clksrc_mask_cam_ctrl, | 944 | .enable = exynos4_clksrc_mask_cam_ctrl, |
954 | .ctrlbit = (1 << 8), | 945 | .ctrlbit = (1 << 8), |
955 | }, | 946 | }, |
@@ -959,7 +950,7 @@ static struct clksrc_clk clksrcs[] = { | |||
959 | }, { | 950 | }, { |
960 | .clk = { | 951 | .clk = { |
961 | .name = "sclk_fimc", | 952 | .name = "sclk_fimc", |
962 | .id = 3, | 953 | .devname = "exynos4-fimc.3", |
963 | .enable = exynos4_clksrc_mask_cam_ctrl, | 954 | .enable = exynos4_clksrc_mask_cam_ctrl, |
964 | .ctrlbit = (1 << 12), | 955 | .ctrlbit = (1 << 12), |
965 | }, | 956 | }, |
@@ -969,7 +960,7 @@ static struct clksrc_clk clksrcs[] = { | |||
969 | }, { | 960 | }, { |
970 | .clk = { | 961 | .clk = { |
971 | .name = "sclk_fimd", | 962 | .name = "sclk_fimd", |
972 | .id = 0, | 963 | .devname = "exynos4-fb.0", |
973 | .enable = exynos4_clksrc_mask_lcd0_ctrl, | 964 | .enable = exynos4_clksrc_mask_lcd0_ctrl, |
974 | .ctrlbit = (1 << 0), | 965 | .ctrlbit = (1 << 0), |
975 | }, | 966 | }, |
@@ -979,7 +970,7 @@ static struct clksrc_clk clksrcs[] = { | |||
979 | }, { | 970 | }, { |
980 | .clk = { | 971 | .clk = { |
981 | .name = "sclk_fimd", | 972 | .name = "sclk_fimd", |
982 | .id = 1, | 973 | .devname = "exynos4-fb.1", |
983 | .enable = exynos4_clksrc_mask_lcd1_ctrl, | 974 | .enable = exynos4_clksrc_mask_lcd1_ctrl, |
984 | .ctrlbit = (1 << 0), | 975 | .ctrlbit = (1 << 0), |
985 | }, | 976 | }, |
@@ -989,7 +980,6 @@ static struct clksrc_clk clksrcs[] = { | |||
989 | }, { | 980 | }, { |
990 | .clk = { | 981 | .clk = { |
991 | .name = "sclk_sata", | 982 | .name = "sclk_sata", |
992 | .id = -1, | ||
993 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 983 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
994 | .ctrlbit = (1 << 24), | 984 | .ctrlbit = (1 << 24), |
995 | }, | 985 | }, |
@@ -999,7 +989,7 @@ static struct clksrc_clk clksrcs[] = { | |||
999 | }, { | 989 | }, { |
1000 | .clk = { | 990 | .clk = { |
1001 | .name = "sclk_spi", | 991 | .name = "sclk_spi", |
1002 | .id = 0, | 992 | .devname = "s3c64xx-spi.0", |
1003 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 993 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1004 | .ctrlbit = (1 << 16), | 994 | .ctrlbit = (1 << 16), |
1005 | }, | 995 | }, |
@@ -1009,7 +999,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1009 | }, { | 999 | }, { |
1010 | .clk = { | 1000 | .clk = { |
1011 | .name = "sclk_spi", | 1001 | .name = "sclk_spi", |
1012 | .id = 1, | 1002 | .devname = "s3c64xx-spi.1", |
1013 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 1003 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1014 | .ctrlbit = (1 << 20), | 1004 | .ctrlbit = (1 << 20), |
1015 | }, | 1005 | }, |
@@ -1019,7 +1009,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1019 | }, { | 1009 | }, { |
1020 | .clk = { | 1010 | .clk = { |
1021 | .name = "sclk_spi", | 1011 | .name = "sclk_spi", |
1022 | .id = 2, | 1012 | .devname = "s3c64xx-spi.2", |
1023 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 1013 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1024 | .ctrlbit = (1 << 24), | 1014 | .ctrlbit = (1 << 24), |
1025 | }, | 1015 | }, |
@@ -1029,15 +1019,22 @@ static struct clksrc_clk clksrcs[] = { | |||
1029 | }, { | 1019 | }, { |
1030 | .clk = { | 1020 | .clk = { |
1031 | .name = "sclk_fimg2d", | 1021 | .name = "sclk_fimg2d", |
1032 | .id = -1, | ||
1033 | }, | 1022 | }, |
1034 | .sources = &clkset_mout_g2d, | 1023 | .sources = &clkset_mout_g2d, |
1035 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, | 1024 | .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 }, |
1036 | .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, | 1025 | .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 }, |
1037 | }, { | 1026 | }, { |
1038 | .clk = { | 1027 | .clk = { |
1028 | .name = "sclk_mfc", | ||
1029 | .devname = "s5p-mfc", | ||
1030 | }, | ||
1031 | .sources = &clkset_mout_mfc, | ||
1032 | .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 }, | ||
1033 | .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, | ||
1034 | }, { | ||
1035 | .clk = { | ||
1039 | .name = "sclk_mmc", | 1036 | .name = "sclk_mmc", |
1040 | .id = 0, | 1037 | .devname = "s3c-sdhci.0", |
1041 | .parent = &clk_dout_mmc0.clk, | 1038 | .parent = &clk_dout_mmc0.clk, |
1042 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1039 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1043 | .ctrlbit = (1 << 0), | 1040 | .ctrlbit = (1 << 0), |
@@ -1046,7 +1043,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1046 | }, { | 1043 | }, { |
1047 | .clk = { | 1044 | .clk = { |
1048 | .name = "sclk_mmc", | 1045 | .name = "sclk_mmc", |
1049 | .id = 1, | 1046 | .devname = "s3c-sdhci.1", |
1050 | .parent = &clk_dout_mmc1.clk, | 1047 | .parent = &clk_dout_mmc1.clk, |
1051 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1048 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1052 | .ctrlbit = (1 << 4), | 1049 | .ctrlbit = (1 << 4), |
@@ -1055,7 +1052,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1055 | }, { | 1052 | }, { |
1056 | .clk = { | 1053 | .clk = { |
1057 | .name = "sclk_mmc", | 1054 | .name = "sclk_mmc", |
1058 | .id = 2, | 1055 | .devname = "s3c-sdhci.2", |
1059 | .parent = &clk_dout_mmc2.clk, | 1056 | .parent = &clk_dout_mmc2.clk, |
1060 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1057 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1061 | .ctrlbit = (1 << 8), | 1058 | .ctrlbit = (1 << 8), |
@@ -1064,7 +1061,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1064 | }, { | 1061 | }, { |
1065 | .clk = { | 1062 | .clk = { |
1066 | .name = "sclk_mmc", | 1063 | .name = "sclk_mmc", |
1067 | .id = 3, | 1064 | .devname = "s3c-sdhci.3", |
1068 | .parent = &clk_dout_mmc3.clk, | 1065 | .parent = &clk_dout_mmc3.clk, |
1069 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1066 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1070 | .ctrlbit = (1 << 12), | 1067 | .ctrlbit = (1 << 12), |
@@ -1072,8 +1069,7 @@ static struct clksrc_clk clksrcs[] = { | |||
1072 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, | 1069 | .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, |
1073 | }, { | 1070 | }, { |
1074 | .clk = { | 1071 | .clk = { |
1075 | .name = "sclk_mmc", | 1072 | .name = "sclk_dwmmc", |
1076 | .id = 4, | ||
1077 | .parent = &clk_dout_mmc4.clk, | 1073 | .parent = &clk_dout_mmc4.clk, |
1078 | .enable = exynos4_clksrc_mask_fsys_ctrl, | 1074 | .enable = exynos4_clksrc_mask_fsys_ctrl, |
1079 | .ctrlbit = (1 << 16), | 1075 | .ctrlbit = (1 << 16), |
@@ -1112,6 +1108,8 @@ static struct clksrc_clk *sysclks[] = { | |||
1112 | &clk_dout_mmc2, | 1108 | &clk_dout_mmc2, |
1113 | &clk_dout_mmc3, | 1109 | &clk_dout_mmc3, |
1114 | &clk_dout_mmc4, | 1110 | &clk_dout_mmc4, |
1111 | &clk_mout_mfc0, | ||
1112 | &clk_mout_mfc1, | ||
1115 | }; | 1113 | }; |
1116 | 1114 | ||
1117 | static int xtal_rate; | 1115 | static int xtal_rate; |