diff options
Diffstat (limited to 'arch/arm/mach-exynos/dma.c')
-rw-r--r-- | arch/arm/mach-exynos/dma.c | 125 |
1 files changed, 113 insertions, 12 deletions
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c index 91370def4a70..3983abee4264 100644 --- a/arch/arm/mach-exynos/dma.c +++ b/arch/arm/mach-exynos/dma.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
30 | #include <plat/devs.h> | 30 | #include <plat/devs.h> |
31 | #include <plat/irqs.h> | 31 | #include <plat/irqs.h> |
32 | #include <plat/cpu.h> | ||
32 | 33 | ||
33 | #include <mach/map.h> | 34 | #include <mach/map.h> |
34 | #include <mach/irqs.h> | 35 | #include <mach/irqs.h> |
@@ -36,7 +37,7 @@ | |||
36 | 37 | ||
37 | static u64 dma_dmamask = DMA_BIT_MASK(32); | 38 | static u64 dma_dmamask = DMA_BIT_MASK(32); |
38 | 39 | ||
39 | u8 pdma0_peri[] = { | 40 | static u8 exynos4210_pdma0_peri[] = { |
40 | DMACH_PCM0_RX, | 41 | DMACH_PCM0_RX, |
41 | DMACH_PCM0_TX, | 42 | DMACH_PCM0_TX, |
42 | DMACH_PCM2_RX, | 43 | DMACH_PCM2_RX, |
@@ -69,15 +70,47 @@ u8 pdma0_peri[] = { | |||
69 | DMACH_AC97_PCMOUT, | 70 | DMACH_AC97_PCMOUT, |
70 | }; | 71 | }; |
71 | 72 | ||
72 | struct dma_pl330_platdata exynos4_pdma0_pdata = { | 73 | static u8 exynos4212_pdma0_peri[] = { |
73 | .nr_valid_peri = ARRAY_SIZE(pdma0_peri), | 74 | DMACH_PCM0_RX, |
74 | .peri_id = pdma0_peri, | 75 | DMACH_PCM0_TX, |
76 | DMACH_PCM2_RX, | ||
77 | DMACH_PCM2_TX, | ||
78 | DMACH_MIPI_HSI0, | ||
79 | DMACH_MIPI_HSI1, | ||
80 | DMACH_SPI0_RX, | ||
81 | DMACH_SPI0_TX, | ||
82 | DMACH_SPI2_RX, | ||
83 | DMACH_SPI2_TX, | ||
84 | DMACH_I2S0S_TX, | ||
85 | DMACH_I2S0_RX, | ||
86 | DMACH_I2S0_TX, | ||
87 | DMACH_I2S2_RX, | ||
88 | DMACH_I2S2_TX, | ||
89 | DMACH_UART0_RX, | ||
90 | DMACH_UART0_TX, | ||
91 | DMACH_UART2_RX, | ||
92 | DMACH_UART2_TX, | ||
93 | DMACH_UART4_RX, | ||
94 | DMACH_UART4_TX, | ||
95 | DMACH_SLIMBUS0_RX, | ||
96 | DMACH_SLIMBUS0_TX, | ||
97 | DMACH_SLIMBUS2_RX, | ||
98 | DMACH_SLIMBUS2_TX, | ||
99 | DMACH_SLIMBUS4_RX, | ||
100 | DMACH_SLIMBUS4_TX, | ||
101 | DMACH_AC97_MICIN, | ||
102 | DMACH_AC97_PCMIN, | ||
103 | DMACH_AC97_PCMOUT, | ||
104 | DMACH_MIPI_HSI4, | ||
105 | DMACH_MIPI_HSI5, | ||
75 | }; | 106 | }; |
76 | 107 | ||
77 | AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, EXYNOS4_PA_PDMA0, | 108 | struct dma_pl330_platdata exynos4_pdma0_pdata; |
78 | {IRQ_PDMA0}, &exynos4_pdma0_pdata); | 109 | |
110 | static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, | ||
111 | EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata); | ||
79 | 112 | ||
80 | u8 pdma1_peri[] = { | 113 | static u8 exynos4210_pdma1_peri[] = { |
81 | DMACH_PCM0_RX, | 114 | DMACH_PCM0_RX, |
82 | DMACH_PCM0_TX, | 115 | DMACH_PCM0_TX, |
83 | DMACH_PCM1_RX, | 116 | DMACH_PCM1_RX, |
@@ -105,19 +138,84 @@ u8 pdma1_peri[] = { | |||
105 | DMACH_SLIMBUS5_TX, | 138 | DMACH_SLIMBUS5_TX, |
106 | }; | 139 | }; |
107 | 140 | ||
108 | struct dma_pl330_platdata exynos4_pdma1_pdata = { | 141 | static u8 exynos4212_pdma1_peri[] = { |
109 | .nr_valid_peri = ARRAY_SIZE(pdma1_peri), | 142 | DMACH_PCM0_RX, |
110 | .peri_id = pdma1_peri, | 143 | DMACH_PCM0_TX, |
144 | DMACH_PCM1_RX, | ||
145 | DMACH_PCM1_TX, | ||
146 | DMACH_MIPI_HSI2, | ||
147 | DMACH_MIPI_HSI3, | ||
148 | DMACH_SPI1_RX, | ||
149 | DMACH_SPI1_TX, | ||
150 | DMACH_I2S0S_TX, | ||
151 | DMACH_I2S0_RX, | ||
152 | DMACH_I2S0_TX, | ||
153 | DMACH_I2S1_RX, | ||
154 | DMACH_I2S1_TX, | ||
155 | DMACH_UART0_RX, | ||
156 | DMACH_UART0_TX, | ||
157 | DMACH_UART1_RX, | ||
158 | DMACH_UART1_TX, | ||
159 | DMACH_UART3_RX, | ||
160 | DMACH_UART3_TX, | ||
161 | DMACH_SLIMBUS1_RX, | ||
162 | DMACH_SLIMBUS1_TX, | ||
163 | DMACH_SLIMBUS3_RX, | ||
164 | DMACH_SLIMBUS3_TX, | ||
165 | DMACH_SLIMBUS5_RX, | ||
166 | DMACH_SLIMBUS5_TX, | ||
167 | DMACH_SLIMBUS0AUX_RX, | ||
168 | DMACH_SLIMBUS0AUX_TX, | ||
169 | DMACH_SPDIF, | ||
170 | DMACH_MIPI_HSI6, | ||
171 | DMACH_MIPI_HSI7, | ||
172 | }; | ||
173 | |||
174 | static struct dma_pl330_platdata exynos4_pdma1_pdata; | ||
175 | |||
176 | static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, | ||
177 | EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata); | ||
178 | |||
179 | static u8 mdma_peri[] = { | ||
180 | DMACH_MTOM_0, | ||
181 | DMACH_MTOM_1, | ||
182 | DMACH_MTOM_2, | ||
183 | DMACH_MTOM_3, | ||
184 | DMACH_MTOM_4, | ||
185 | DMACH_MTOM_5, | ||
186 | DMACH_MTOM_6, | ||
187 | DMACH_MTOM_7, | ||
111 | }; | 188 | }; |
112 | 189 | ||
113 | AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, EXYNOS4_PA_PDMA1, | 190 | static struct dma_pl330_platdata exynos4_mdma1_pdata = { |
114 | {IRQ_PDMA1}, &exynos4_pdma1_pdata); | 191 | .nr_valid_peri = ARRAY_SIZE(mdma_peri), |
192 | .peri_id = mdma_peri, | ||
193 | }; | ||
194 | |||
195 | static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330, | ||
196 | EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata); | ||
115 | 197 | ||
116 | static int __init exynos4_dma_init(void) | 198 | static int __init exynos4_dma_init(void) |
117 | { | 199 | { |
118 | if (of_have_populated_dt()) | 200 | if (of_have_populated_dt()) |
119 | return 0; | 201 | return 0; |
120 | 202 | ||
203 | if (soc_is_exynos4210()) { | ||
204 | exynos4_pdma0_pdata.nr_valid_peri = | ||
205 | ARRAY_SIZE(exynos4210_pdma0_peri); | ||
206 | exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri; | ||
207 | exynos4_pdma1_pdata.nr_valid_peri = | ||
208 | ARRAY_SIZE(exynos4210_pdma1_peri); | ||
209 | exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri; | ||
210 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { | ||
211 | exynos4_pdma0_pdata.nr_valid_peri = | ||
212 | ARRAY_SIZE(exynos4212_pdma0_peri); | ||
213 | exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri; | ||
214 | exynos4_pdma1_pdata.nr_valid_peri = | ||
215 | ARRAY_SIZE(exynos4212_pdma1_peri); | ||
216 | exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri; | ||
217 | } | ||
218 | |||
121 | dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); | 219 | dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask); |
122 | dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); | 220 | dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask); |
123 | amba_device_register(&exynos4_pdma0_device, &iomem_resource); | 221 | amba_device_register(&exynos4_pdma0_device, &iomem_resource); |
@@ -126,6 +224,9 @@ static int __init exynos4_dma_init(void) | |||
126 | dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); | 224 | dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); |
127 | amba_device_register(&exynos4_pdma1_device, &iomem_resource); | 225 | amba_device_register(&exynos4_pdma1_device, &iomem_resource); |
128 | 226 | ||
227 | dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask); | ||
228 | amba_device_register(&exynos4_mdma1_device, &iomem_resource); | ||
229 | |||
129 | return 0; | 230 | return 0; |
130 | } | 231 | } |
131 | arch_initcall(exynos4_dma_init); | 232 | arch_initcall(exynos4_dma_init); |