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-rw-r--r--arch/arm/mach-epxa10db/irq.c82
1 files changed, 0 insertions, 82 deletions
diff --git a/arch/arm/mach-epxa10db/irq.c b/arch/arm/mach-epxa10db/irq.c
deleted file mode 100644
index 9bf927e13309..000000000000
--- a/arch/arm/mach-epxa10db/irq.c
+++ /dev/null
@@ -1,82 +0,0 @@
1/*
2 * linux/arch/arm/mach-epxa10db/irq.c
3 *
4 * Copyright (C) 2001 Altera Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/stddef.h>
23#include <linux/timer.h>
24#include <linux/list.h>
25#include <asm/io.h>
26#include <asm/hardware.h>
27#include <asm/irq.h>
28#include <asm/mach/irq.h>
29#include <asm/arch/platform.h>
30#include <asm/arch/int_ctrl00.h>
31
32
33static void epxa_mask_irq(unsigned int irq)
34{
35 writel(1 << irq, INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
36}
37
38static void epxa_unmask_irq(unsigned int irq)
39{
40 writel(1 << irq, INT_MS(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
41}
42
43
44static struct irqchip epxa_irq_chip = {
45 .ack = epxa_mask_irq,
46 .mask = epxa_mask_irq,
47 .unmask = epxa_unmask_irq,
48};
49
50static struct resource irq_resource = {
51 .name = "irq_handler",
52 .start = IO_ADDRESS(EXC_INT_CTRL00_BASE),
53 .end = IO_ADDRESS(INT_PRIORITY_FC(EXC_INT_CTRL00_BASE))+4,
54};
55
56void __init epxa10db_init_irq(void)
57{
58 unsigned int i;
59
60 request_resource(&iomem_resource, &irq_resource);
61
62 /*
63 * This bit sets up the interrupt controller using
64 * the 6 PLD interrupts mode (the default) each
65 * irqs is assigned a priority which is the same
66 * as its interrupt number. This scheme is used because
67 * its easy, but you may want to change it depending
68 * on the contents of your PLD
69 */
70
71 writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
72 for (i = 0; i < NR_IRQS; i++){
73 writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i));
74 set_irq_chip(i,&epxa_irq_chip);
75 set_irq_handler(i,do_level_IRQ);
76 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
77 }
78
79 /* Disable all interrupts */
80 writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE)));
81
82}