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-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h61
-rw-r--r--arch/arm/mach-ep93xx/include/mach/io.h17
2 files changed, 47 insertions, 31 deletions
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 967c079180db..49b256b3ddfc 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -52,40 +52,43 @@
52#define EP93XX_AHB_VIRT_BASE 0xfef00000 52#define EP93XX_AHB_VIRT_BASE 0xfef00000
53#define EP93XX_AHB_SIZE 0x00100000 53#define EP93XX_AHB_SIZE 0x00100000
54 54
55#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
56
55#define EP93XX_APB_PHYS_BASE 0x80800000 57#define EP93XX_APB_PHYS_BASE 0x80800000
56#define EP93XX_APB_VIRT_BASE 0xfed00000 58#define EP93XX_APB_VIRT_BASE 0xfed00000
57#define EP93XX_APB_SIZE 0x00200000 59#define EP93XX_APB_SIZE 0x00200000
58 60
61#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
62
59 63
60/* AHB peripherals */ 64/* AHB peripherals */
61#define EP93XX_DMA_BASE ((void __iomem *) \ 65#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
62 (EP93XX_AHB_VIRT_BASE + 0x00000000))
63 66
64#define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000)
65#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) 67#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000)
68#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
66 69
67#define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000)
68#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) 70#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000)
71#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
69 72
70#define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) 73#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
71 74
72#define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) 75#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
73 76
74#define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) 77#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
75 78
76#define EP93XX_PCMCIA_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00080000) 79#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
77 80
78#define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) 81#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
79 82
80#define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) 83#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
81 84
82#define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) 85#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
83 86
84#define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) 87#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
85 88
86 89
87/* APB peripherals */ 90/* APB peripherals */
88#define EP93XX_TIMER_BASE (EP93XX_APB_VIRT_BASE + 0x00010000) 91#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
89#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) 92#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
90#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) 93#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
91#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) 94#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
@@ -102,11 +105,11 @@
102#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) 105#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
103#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) 106#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
104 107
105#define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000) 108#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
106 109
107#define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) 110#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
108 111
109#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) 112#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
110#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) 113#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
111#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c) 114#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c)
112#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50) 115#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50)
@@ -124,32 +127,32 @@
124#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) 127#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8)
125#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) 128#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
126 129
127#define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) 130#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
128 131
129#define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000) 132#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
130 133
131#define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000) 134#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
132 135
133#define EP93XX_UART1_BASE (EP93XX_APB_VIRT_BASE + 0x000c0000)
134#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000) 136#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000)
137#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
135 138
136#define EP93XX_UART2_BASE (EP93XX_APB_VIRT_BASE + 0x000d0000)
137#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000) 139#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000)
140#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
138 141
139#define EP93XX_UART3_BASE (EP93XX_APB_VIRT_BASE + 0x000e0000)
140#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000) 142#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000)
143#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
141 144
142#define EP93XX_KEY_MATRIX_BASE (EP93XX_APB_VIRT_BASE + 0x000f0000) 145#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
143 146
144#define EP93XX_ADC_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) 147#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
145#define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) 148#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
146 149
147#define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) 150#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
148 151
149#define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000)
150#define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000) 152#define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000)
153#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
151 154
152#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) 155#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
153#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) 156#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
154#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) 157#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
155#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) 158#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
@@ -179,7 +182,7 @@
179#define EP93XX_SYSCON_DEVICE_CONFIG_U1EN (1<<18) 182#define EP93XX_SYSCON_DEVICE_CONFIG_U1EN (1<<18)
180#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) 183#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
181 184
182#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) 185#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
183 186
184 187
185#endif 188#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index fd5f081cc8b7..cebcc1c53d63 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -1,8 +1,21 @@
1/* 1/*
2 * arch/arm/mach-ep93xx/include/mach/io.h 2 * arch/arm/mach-ep93xx/include/mach/io.h
3 */ 3 */
4#ifndef __ASM_MACH_IO_H
5#define __ASM_MACH_IO_H
4 6
5#define IO_SPACE_LIMIT 0xffffffff 7#define IO_SPACE_LIMIT 0xffffffff
6 8
7#define __io(p) __typesafe_io(p) 9#define __io(p) __typesafe_io(p)
8#define __mem_pci(p) (p) 10#define __mem_pci(p) (p)
11
12/*
13 * A typesafe __io() variation for variable initialisers
14 */
15#ifdef __ASSEMBLER__
16#define IOMEM(p) p
17#else
18#define IOMEM(p) ((void __iomem __force *)(p))
19#endif
20
21#endif /* __ASM_MACH_IO_H */