aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-ep93xx
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-ep93xx')
-rw-r--r--arch/arm/mach-ep93xx/adssphere.c11
-rw-r--r--arch/arm/mach-ep93xx/clock.c131
-rw-r--r--arch/arm/mach-ep93xx/core.c202
-rw-r--r--arch/arm/mach-ep93xx/edb93xx.c10
-rw-r--r--arch/arm/mach-ep93xx/gesbc9312.c11
-rw-r--r--arch/arm/mach-ep93xx/gpio.c65
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h103
-rw-r--r--arch/arm/mach-ep93xx/include/mach/hardware.h17
-rw-r--r--arch/arm/mach-ep93xx/include/mach/io.h17
-rw-r--r--arch/arm/mach-ep93xx/include/mach/platform.h20
-rw-r--r--arch/arm/mach-ep93xx/include/mach/system.h12
-rw-r--r--arch/arm/mach-ep93xx/include/mach/ts72xx.h1
-rw-r--r--arch/arm/mach-ep93xx/micro9.c11
-rw-r--r--arch/arm/mach-ep93xx/ts72xx.c15
14 files changed, 454 insertions, 172 deletions
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 3fbd9b0fbe24..caf6d5154aec 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -12,18 +12,15 @@
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/mtd/physmap.h>
20#include <linux/platform_device.h> 15#include <linux/platform_device.h>
21#include <linux/io.h> 16#include <linux/mtd/physmap.h>
22#include <linux/i2c.h> 17
23#include <mach/hardware.h> 18#include <mach/hardware.h>
19
24#include <asm/mach-types.h> 20#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
26 22
23
27static struct physmap_flash_data adssphere_flash_data = { 24static struct physmap_flash_data adssphere_flash_data = {
28 .width = 4, 25 .width = 4,
29}; 26};
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 6c4c1633ed12..3dd0e2a23095 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -22,48 +22,39 @@
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23 23
24 24
25/*
26 * The EP93xx has two external crystal oscillators. To generate the
27 * required high-frequency clocks, the processor uses two phase-locked-
28 * loops (PLLs) to multiply the incoming external clock signal to much
29 * higher frequencies that are then divided down by programmable dividers
30 * to produce the needed clocks. The PLLs operate independently of one
31 * another.
32 */
33#define EP93XX_EXT_CLK_RATE 14745600
34#define EP93XX_EXT_RTC_RATE 32768
35
36
37struct clk { 25struct clk {
38 unsigned long rate; 26 unsigned long rate;
39 int users; 27 int users;
40 int sw_locked; 28 int sw_locked;
41 u32 enable_reg; 29 void __iomem *enable_reg;
42 u32 enable_mask; 30 u32 enable_mask;
43 31
44 unsigned long (*get_rate)(struct clk *clk); 32 unsigned long (*get_rate)(struct clk *clk);
33 int (*set_rate)(struct clk *clk, unsigned long rate);
45}; 34};
46 35
47 36
48static unsigned long get_uart_rate(struct clk *clk); 37static unsigned long get_uart_rate(struct clk *clk);
49 38
39static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
40
50 41
51static struct clk clk_uart1 = { 42static struct clk clk_uart1 = {
52 .sw_locked = 1, 43 .sw_locked = 1,
53 .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, 44 .enable_reg = EP93XX_SYSCON_DEVCFG,
54 .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U1EN, 45 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
55 .get_rate = get_uart_rate, 46 .get_rate = get_uart_rate,
56}; 47};
57static struct clk clk_uart2 = { 48static struct clk clk_uart2 = {
58 .sw_locked = 1, 49 .sw_locked = 1,
59 .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, 50 .enable_reg = EP93XX_SYSCON_DEVCFG,
60 .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U2EN, 51 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
61 .get_rate = get_uart_rate, 52 .get_rate = get_uart_rate,
62}; 53};
63static struct clk clk_uart3 = { 54static struct clk clk_uart3 = {
64 .sw_locked = 1, 55 .sw_locked = 1,
65 .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, 56 .enable_reg = EP93XX_SYSCON_DEVCFG,
66 .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U3EN, 57 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
67 .get_rate = get_uart_rate, 58 .get_rate = get_uart_rate,
68}; 59};
69static struct clk clk_pll1; 60static struct clk clk_pll1;
@@ -75,6 +66,15 @@ static struct clk clk_usb_host = {
75 .enable_reg = EP93XX_SYSCON_PWRCNT, 66 .enable_reg = EP93XX_SYSCON_PWRCNT,
76 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, 67 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
77}; 68};
69static struct clk clk_keypad = {
70 .sw_locked = 1,
71 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
72 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
73 .set_rate = set_keytchclk_rate,
74};
75static struct clk clk_pwm = {
76 .rate = EP93XX_EXT_CLK_RATE,
77};
78 78
79/* DMA Clocks */ 79/* DMA Clocks */
80static struct clk clk_m2p0 = { 80static struct clk clk_m2p0 = {
@@ -130,27 +130,29 @@ static struct clk clk_m2m1 = {
130 { .dev_id = dev, .con_id = con, .clk = ck } 130 { .dev_id = dev, .con_id = con, .clk = ck }
131 131
132static struct clk_lookup clocks[] = { 132static struct clk_lookup clocks[] = {
133 INIT_CK("apb:uart1", NULL, &clk_uart1), 133 INIT_CK("apb:uart1", NULL, &clk_uart1),
134 INIT_CK("apb:uart2", NULL, &clk_uart2), 134 INIT_CK("apb:uart2", NULL, &clk_uart2),
135 INIT_CK("apb:uart3", NULL, &clk_uart3), 135 INIT_CK("apb:uart3", NULL, &clk_uart3),
136 INIT_CK(NULL, "pll1", &clk_pll1), 136 INIT_CK(NULL, "pll1", &clk_pll1),
137 INIT_CK(NULL, "fclk", &clk_f), 137 INIT_CK(NULL, "fclk", &clk_f),
138 INIT_CK(NULL, "hclk", &clk_h), 138 INIT_CK(NULL, "hclk", &clk_h),
139 INIT_CK(NULL, "pclk", &clk_p), 139 INIT_CK(NULL, "pclk", &clk_p),
140 INIT_CK(NULL, "pll2", &clk_pll2), 140 INIT_CK(NULL, "pll2", &clk_pll2),
141 INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), 141 INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
142 INIT_CK(NULL, "m2p0", &clk_m2p0), 142 INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
143 INIT_CK(NULL, "m2p1", &clk_m2p1), 143 INIT_CK(NULL, "pwm_clk", &clk_pwm),
144 INIT_CK(NULL, "m2p2", &clk_m2p2), 144 INIT_CK(NULL, "m2p0", &clk_m2p0),
145 INIT_CK(NULL, "m2p3", &clk_m2p3), 145 INIT_CK(NULL, "m2p1", &clk_m2p1),
146 INIT_CK(NULL, "m2p4", &clk_m2p4), 146 INIT_CK(NULL, "m2p2", &clk_m2p2),
147 INIT_CK(NULL, "m2p5", &clk_m2p5), 147 INIT_CK(NULL, "m2p3", &clk_m2p3),
148 INIT_CK(NULL, "m2p6", &clk_m2p6), 148 INIT_CK(NULL, "m2p4", &clk_m2p4),
149 INIT_CK(NULL, "m2p7", &clk_m2p7), 149 INIT_CK(NULL, "m2p5", &clk_m2p5),
150 INIT_CK(NULL, "m2p8", &clk_m2p8), 150 INIT_CK(NULL, "m2p6", &clk_m2p6),
151 INIT_CK(NULL, "m2p9", &clk_m2p9), 151 INIT_CK(NULL, "m2p7", &clk_m2p7),
152 INIT_CK(NULL, "m2m0", &clk_m2m0), 152 INIT_CK(NULL, "m2p8", &clk_m2p8),
153 INIT_CK(NULL, "m2m1", &clk_m2m1), 153 INIT_CK(NULL, "m2p9", &clk_m2p9),
154 INIT_CK(NULL, "m2m0", &clk_m2m0),
155 INIT_CK(NULL, "m2m1", &clk_m2m1),
154}; 156};
155 157
156 158
@@ -160,9 +162,11 @@ int clk_enable(struct clk *clk)
160 u32 value; 162 u32 value;
161 163
162 value = __raw_readl(clk->enable_reg); 164 value = __raw_readl(clk->enable_reg);
165 value |= clk->enable_mask;
163 if (clk->sw_locked) 166 if (clk->sw_locked)
164 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 167 ep93xx_syscon_swlocked_write(value, clk->enable_reg);
165 __raw_writel(value | clk->enable_mask, clk->enable_reg); 168 else
169 __raw_writel(value, clk->enable_reg);
166 } 170 }
167 171
168 return 0; 172 return 0;
@@ -175,9 +179,11 @@ void clk_disable(struct clk *clk)
175 u32 value; 179 u32 value;
176 180
177 value = __raw_readl(clk->enable_reg); 181 value = __raw_readl(clk->enable_reg);
182 value &= ~clk->enable_mask;
178 if (clk->sw_locked) 183 if (clk->sw_locked)
179 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 184 ep93xx_syscon_swlocked_write(value, clk->enable_reg);
180 __raw_writel(value & ~clk->enable_mask, clk->enable_reg); 185 else
186 __raw_writel(value, clk->enable_reg);
181 } 187 }
182} 188}
183EXPORT_SYMBOL(clk_disable); 189EXPORT_SYMBOL(clk_disable);
@@ -202,6 +208,43 @@ unsigned long clk_get_rate(struct clk *clk)
202} 208}
203EXPORT_SYMBOL(clk_get_rate); 209EXPORT_SYMBOL(clk_get_rate);
204 210
211static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
212{
213 u32 val;
214 u32 div_bit;
215
216 val = __raw_readl(clk->enable_reg);
217
218 /*
219 * The Key Matrix and ADC clocks are configured using the same
220 * System Controller register. The clock used will be either
221 * 1/4 or 1/16 the external clock rate depending on the
222 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
223 * bit being set or cleared.
224 */
225 div_bit = clk->enable_mask >> 15;
226
227 if (rate == EP93XX_KEYTCHCLK_DIV4)
228 val |= div_bit;
229 else if (rate == EP93XX_KEYTCHCLK_DIV16)
230 val &= ~div_bit;
231 else
232 return -EINVAL;
233
234 ep93xx_syscon_swlocked_write(val, clk->enable_reg);
235 clk->rate = rate;
236 return 0;
237}
238
239int clk_set_rate(struct clk *clk, unsigned long rate)
240{
241 if (clk->set_rate)
242 return clk->set_rate(clk, rate);
243
244 return -EINVAL;
245}
246EXPORT_SYMBOL(clk_set_rate);
247
205 248
206static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; 249static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
207static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; 250static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 204dc5cbd0b8..16b92c37ec99 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -16,40 +16,24 @@
16 16
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/spinlock.h> 19#include <linux/platform_device.h>
20#include <linux/sched.h>
21#include <linux/interrupt.h> 20#include <linux/interrupt.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/bitops.h>
25#include <linux/serial_8250.h>
26#include <linux/serial_core.h>
27#include <linux/device.h>
28#include <linux/mm.h>
29#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
30#include <linux/time.h>
31#include <linux/timex.h> 22#include <linux/timex.h>
32#include <linux/delay.h> 23#include <linux/io.h>
24#include <linux/gpio.h>
25#include <linux/leds.h>
33#include <linux/termios.h> 26#include <linux/termios.h>
34#include <linux/amba/bus.h> 27#include <linux/amba/bus.h>
35#include <linux/amba/serial.h> 28#include <linux/amba/serial.h>
36#include <linux/io.h>
37#include <linux/i2c.h> 29#include <linux/i2c.h>
38#include <linux/i2c-gpio.h> 30#include <linux/i2c-gpio.h>
39 31
40#include <asm/types.h>
41#include <asm/setup.h>
42#include <asm/memory.h>
43#include <mach/hardware.h> 32#include <mach/hardware.h>
44#include <asm/irq.h>
45#include <asm/system.h>
46#include <asm/tlbflush.h>
47#include <asm/pgtable.h>
48 33
49#include <asm/mach/map.h> 34#include <asm/mach/map.h>
50#include <asm/mach/time.h> 35#include <asm/mach/time.h>
51#include <asm/mach/irq.h> 36#include <asm/mach/irq.h>
52#include <mach/gpio.h>
53 37
54#include <asm/hardware/vic.h> 38#include <asm/hardware/vic.h>
55 39
@@ -98,7 +82,7 @@ void __init ep93xx_map_io(void)
98 */ 82 */
99static unsigned int last_jiffy_time; 83static unsigned int last_jiffy_time;
100 84
101#define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) 85#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
102 86
103static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) 87static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
104{ 88{
@@ -362,8 +346,8 @@ void __init ep93xx_init_irq(void)
362{ 346{
363 int gpio_irq; 347 int gpio_irq;
364 348
365 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); 349 vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
366 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); 350 vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
367 351
368 for (gpio_irq = gpio_to_irq(0); 352 for (gpio_irq = gpio_to_irq(0);
369 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { 353 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
@@ -385,6 +369,47 @@ void __init ep93xx_init_irq(void)
385 369
386 370
387/************************************************************************* 371/*************************************************************************
372 * EP93xx System Controller Software Locked register handling
373 *************************************************************************/
374
375/*
376 * syscon_swlock prevents anything else from writing to the syscon
377 * block while a software locked register is being written.
378 */
379static DEFINE_SPINLOCK(syscon_swlock);
380
381void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
382{
383 unsigned long flags;
384
385 spin_lock_irqsave(&syscon_swlock, flags);
386
387 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
388 __raw_writel(val, reg);
389
390 spin_unlock_irqrestore(&syscon_swlock, flags);
391}
392EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
393
394void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
395{
396 unsigned long flags;
397 unsigned int val;
398
399 spin_lock_irqsave(&syscon_swlock, flags);
400
401 val = __raw_readl(EP93XX_SYSCON_DEVCFG);
402 val |= set_bits;
403 val &= ~clear_bits;
404 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
405 __raw_writel(val, EP93XX_SYSCON_DEVCFG);
406
407 spin_unlock_irqrestore(&syscon_swlock, flags);
408}
409EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
410
411
412/*************************************************************************
388 * EP93xx peripheral handling 413 * EP93xx peripheral handling
389 *************************************************************************/ 414 *************************************************************************/
390#define EP93XX_UART_MCR_OFFSET (0x0100) 415#define EP93XX_UART_MCR_OFFSET (0x0100)
@@ -517,10 +542,8 @@ static struct platform_device ep93xx_eth_device = {
517 542
518void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) 543void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
519{ 544{
520 if (copy_addr) { 545 if (copy_addr)
521 memcpy(data->dev_addr, 546 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
522 (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
523 }
524 547
525 ep93xx_eth_data = *data; 548 ep93xx_eth_data = *data;
526 platform_device_register(&ep93xx_eth_device); 549 platform_device_register(&ep93xx_eth_device);
@@ -546,19 +569,125 @@ void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
546 platform_device_register(&ep93xx_i2c_device); 569 platform_device_register(&ep93xx_i2c_device);
547} 570}
548 571
572
573/*************************************************************************
574 * EP93xx LEDs
575 *************************************************************************/
576static struct gpio_led ep93xx_led_pins[] = {
577 {
578 .name = "platform:grled",
579 .gpio = EP93XX_GPIO_LINE_GRLED,
580 }, {
581 .name = "platform:rdled",
582 .gpio = EP93XX_GPIO_LINE_RDLED,
583 },
584};
585
586static struct gpio_led_platform_data ep93xx_led_data = {
587 .num_leds = ARRAY_SIZE(ep93xx_led_pins),
588 .leds = ep93xx_led_pins,
589};
590
591static struct platform_device ep93xx_leds = {
592 .name = "leds-gpio",
593 .id = -1,
594 .dev = {
595 .platform_data = &ep93xx_led_data,
596 },
597};
598
599
600/*************************************************************************
601 * EP93xx pwm peripheral handling
602 *************************************************************************/
603static struct resource ep93xx_pwm0_resource[] = {
604 {
605 .start = EP93XX_PWM_PHYS_BASE,
606 .end = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
607 .flags = IORESOURCE_MEM,
608 },
609};
610
611static struct platform_device ep93xx_pwm0_device = {
612 .name = "ep93xx-pwm",
613 .id = 0,
614 .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource),
615 .resource = ep93xx_pwm0_resource,
616};
617
618static struct resource ep93xx_pwm1_resource[] = {
619 {
620 .start = EP93XX_PWM_PHYS_BASE + 0x20,
621 .end = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
622 .flags = IORESOURCE_MEM,
623 },
624};
625
626static struct platform_device ep93xx_pwm1_device = {
627 .name = "ep93xx-pwm",
628 .id = 1,
629 .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource),
630 .resource = ep93xx_pwm1_resource,
631};
632
633void __init ep93xx_register_pwm(int pwm0, int pwm1)
634{
635 if (pwm0)
636 platform_device_register(&ep93xx_pwm0_device);
637
638 /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
639 if (pwm1)
640 platform_device_register(&ep93xx_pwm1_device);
641}
642
643int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
644{
645 int err;
646
647 if (pdev->id == 0) {
648 err = 0;
649 } else if (pdev->id == 1) {
650 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
651 dev_name(&pdev->dev));
652 if (err)
653 return err;
654 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
655 if (err)
656 goto fail;
657
658 /* PWM 1 output on EGPIO[14] */
659 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
660 } else {
661 err = -ENODEV;
662 }
663
664 return err;
665
666fail:
667 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
668 return err;
669}
670EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
671
672void ep93xx_pwm_release_gpio(struct platform_device *pdev)
673{
674 if (pdev->id == 1) {
675 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
676 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
677
678 /* EGPIO[14] used for GPIO */
679 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
680 }
681}
682EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
683
684
549extern void ep93xx_gpio_init(void); 685extern void ep93xx_gpio_init(void);
550 686
551void __init ep93xx_init_devices(void) 687void __init ep93xx_init_devices(void)
552{ 688{
553 unsigned int v; 689 /* Disallow access to MaverickCrunch initially */
554 690 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
555 /*
556 * Disallow access to MaverickCrunch initially.
557 */
558 v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
559 v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
560 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
561 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
562 691
563 ep93xx_gpio_init(); 692 ep93xx_gpio_init();
564 693
@@ -568,4 +697,5 @@ void __init ep93xx_init_devices(void)
568 697
569 platform_device_register(&ep93xx_rtc_device); 698 platform_device_register(&ep93xx_rtc_device);
570 platform_device_register(&ep93xx_ohci_device); 699 platform_device_register(&ep93xx_ohci_device);
700 platform_device_register(&ep93xx_leds);
571} 701}
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index e9e45b92457e..73145ae5d3fa 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -26,18 +26,16 @@
26 26
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/mm.h>
30#include <linux/sched.h>
31#include <linux/interrupt.h>
32#include <linux/ioport.h>
33#include <linux/mtd/physmap.h>
34#include <linux/platform_device.h> 29#include <linux/platform_device.h>
35#include <linux/io.h>
36#include <linux/i2c.h> 30#include <linux/i2c.h>
31#include <linux/mtd/physmap.h>
32
37#include <mach/hardware.h> 33#include <mach/hardware.h>
34
38#include <asm/mach-types.h> 35#include <asm/mach-types.h>
39#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
40 37
38
41static struct physmap_flash_data edb93xx_flash_data; 39static struct physmap_flash_data edb93xx_flash_data;
42 40
43static struct resource edb93xx_flash_resource = { 41static struct resource edb93xx_flash_resource = {
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 3bad500b71b6..3da7ca816d19 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -12,18 +12,15 @@
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/mtd/physmap.h>
20#include <linux/platform_device.h> 15#include <linux/platform_device.h>
21#include <linux/io.h> 16#include <linux/mtd/physmap.h>
22#include <linux/i2c.h> 17
23#include <mach/hardware.h> 18#include <mach/hardware.h>
19
24#include <asm/mach-types.h> 20#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
26 22
23
27static struct physmap_flash_data gesbc9312_flash_data = { 24static struct physmap_flash_data gesbc9312_flash_data = {
28 .width = 4, 25 .width = 4,
29}; 26};
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 482cf3d2fbcd..1ea8871e03a9 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -17,15 +17,16 @@
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/seq_file.h> 18#include <linux/seq_file.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/irq.h>
20 22
21#include <mach/ep93xx-regs.h> 23#include <mach/hardware.h>
22#include <asm/gpio.h>
23 24
24struct ep93xx_gpio_chip { 25struct ep93xx_gpio_chip {
25 struct gpio_chip chip; 26 struct gpio_chip chip;
26 27
27 unsigned int data_reg; 28 void __iomem *data_reg;
28 unsigned int data_dir_reg; 29 void __iomem *data_dir_reg;
29}; 30};
30 31
31#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip) 32#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
@@ -111,15 +112,61 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
111{ 112{
112 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); 113 struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
113 u8 data_reg, data_dir_reg; 114 u8 data_reg, data_dir_reg;
114 int i; 115 int gpio, i;
115 116
116 data_reg = __raw_readb(ep93xx_chip->data_reg); 117 data_reg = __raw_readb(ep93xx_chip->data_reg);
117 data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg); 118 data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
118 119
119 for (i = 0; i < chip->ngpio; i++) 120 gpio = ep93xx_chip->chip.base;
120 seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i, 121 for (i = 0; i < chip->ngpio; i++, gpio++) {
121 (data_reg & (1 << i)) ? "set" : "clear", 122 int is_out = data_dir_reg & (1 << i);
122 (data_dir_reg & (1 << i)) ? "out" : "in"); 123
124 seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s",
125 chip->label, i, gpio,
126 gpiochip_is_requested(chip, i) ? : "",
127 is_out ? "out" : "in ",
128 (data_reg & (1 << i)) ? "hi" : "lo");
129
130 if (!is_out) {
131 int irq = gpio_to_irq(gpio);
132 struct irq_desc *desc = irq_desc + irq;
133
134 if (irq >= 0 && desc->action) {
135 char *trigger;
136
137 switch (desc->status & IRQ_TYPE_SENSE_MASK) {
138 case IRQ_TYPE_NONE:
139 trigger = "(default)";
140 break;
141 case IRQ_TYPE_EDGE_FALLING:
142 trigger = "edge-falling";
143 break;
144 case IRQ_TYPE_EDGE_RISING:
145 trigger = "edge-rising";
146 break;
147 case IRQ_TYPE_EDGE_BOTH:
148 trigger = "edge-both";
149 break;
150 case IRQ_TYPE_LEVEL_HIGH:
151 trigger = "level-high";
152 break;
153 case IRQ_TYPE_LEVEL_LOW:
154 trigger = "level-low";
155 break;
156 default:
157 trigger = "?trigger?";
158 break;
159 }
160
161 seq_printf(s, " irq-%d %s%s",
162 irq, trigger,
163 (desc->status & IRQ_WAKEUP)
164 ? " wakeup" : "");
165 }
166 }
167
168 seq_printf(s, "\n");
169 }
123} 170}
124 171
125#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ 172#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 967c079180db..ea78e908fc82 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -52,40 +52,43 @@
52#define EP93XX_AHB_VIRT_BASE 0xfef00000 52#define EP93XX_AHB_VIRT_BASE 0xfef00000
53#define EP93XX_AHB_SIZE 0x00100000 53#define EP93XX_AHB_SIZE 0x00100000
54 54
55#define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x))
56
55#define EP93XX_APB_PHYS_BASE 0x80800000 57#define EP93XX_APB_PHYS_BASE 0x80800000
56#define EP93XX_APB_VIRT_BASE 0xfed00000 58#define EP93XX_APB_VIRT_BASE 0xfed00000
57#define EP93XX_APB_SIZE 0x00200000 59#define EP93XX_APB_SIZE 0x00200000
58 60
61#define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x))
62
59 63
60/* AHB peripherals */ 64/* AHB peripherals */
61#define EP93XX_DMA_BASE ((void __iomem *) \ 65#define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000)
62 (EP93XX_AHB_VIRT_BASE + 0x00000000))
63 66
64#define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000)
65#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) 67#define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000)
68#define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000)
66 69
67#define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000)
68#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) 70#define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000)
71#define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000)
69 72
70#define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) 73#define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000)
71 74
72#define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) 75#define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000)
73 76
74#define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) 77#define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000)
75 78
76#define EP93XX_PCMCIA_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00080000) 79#define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000)
77 80
78#define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) 81#define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000)
79 82
80#define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) 83#define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000)
81 84
82#define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) 85#define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000)
83 86
84#define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) 87#define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000)
85 88
86 89
87/* APB peripherals */ 90/* APB peripherals */
88#define EP93XX_TIMER_BASE (EP93XX_APB_VIRT_BASE + 0x00010000) 91#define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000)
89#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) 92#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
90#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) 93#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
91#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) 94#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
@@ -102,11 +105,11 @@
102#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) 105#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
103#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) 106#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
104 107
105#define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000) 108#define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000)
106 109
107#define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) 110#define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000)
108 111
109#define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) 112#define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000)
110#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) 113#define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x))
111#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c) 114#define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c)
112#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50) 115#define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50)
@@ -124,32 +127,33 @@
124#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) 127#define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8)
125#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) 128#define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc)
126 129
127#define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) 130#define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000)
128 131
129#define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000) 132#define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000)
130 133
131#define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000) 134#define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000)
132 135
133#define EP93XX_UART1_BASE (EP93XX_APB_VIRT_BASE + 0x000c0000)
134#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000) 136#define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000)
137#define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000)
135 138
136#define EP93XX_UART2_BASE (EP93XX_APB_VIRT_BASE + 0x000d0000)
137#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000) 139#define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000)
140#define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000)
138 141
139#define EP93XX_UART3_BASE (EP93XX_APB_VIRT_BASE + 0x000e0000)
140#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000) 142#define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000)
143#define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000)
141 144
142#define EP93XX_KEY_MATRIX_BASE (EP93XX_APB_VIRT_BASE + 0x000f0000) 145#define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000)
143 146
144#define EP93XX_ADC_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) 147#define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000)
145#define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) 148#define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000)
146 149
147#define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) 150#define EP93XX_PWM_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00110000)
151#define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000)
148 152
149#define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000)
150#define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000) 153#define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000)
154#define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000)
151 155
152#define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) 156#define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000)
153#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) 157#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
154#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) 158#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
155#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) 159#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
@@ -172,14 +176,45 @@
172#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) 176#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
173#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) 177#define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20)
174#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) 178#define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24)
175#define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) 179#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
176#define EP93XX_SYSCON_DEVICE_CONFIG_U3EN (1<<24) 180#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
177#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE (1<<23) 181#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
178#define EP93XX_SYSCON_DEVICE_CONFIG_U2EN (1<<20) 182#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
179#define EP93XX_SYSCON_DEVICE_CONFIG_U1EN (1<<18) 183#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
184#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
185#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
186#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
187#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
188#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
189#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
190#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
191#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
192#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
193#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
194#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
195#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
196#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
197#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
198#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
199#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
200#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
201#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
202#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
203#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
204#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
205#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
206#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
207#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
208#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
209#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
210#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
211#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
212#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
213#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
214#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
180#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) 215#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
181 216
182#define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) 217#define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000)
183 218
184 219
185#endif 220#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 2866297310b7..349fa7cb72d5 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -4,12 +4,23 @@
4#ifndef __ASM_ARCH_HARDWARE_H 4#ifndef __ASM_ARCH_HARDWARE_H
5#define __ASM_ARCH_HARDWARE_H 5#define __ASM_ARCH_HARDWARE_H
6 6
7#include "ep93xx-regs.h" 7#include <mach/ep93xx-regs.h>
8#include <mach/platform.h>
8 9
9#define pcibios_assign_all_busses() 0 10#define pcibios_assign_all_busses() 0
10 11
11#include "platform.h" 12/*
13 * The EP93xx has two external crystal oscillators. To generate the
14 * required high-frequency clocks, the processor uses two phase-locked-
15 * loops (PLLs) to multiply the incoming external clock signal to much
16 * higher frequencies that are then divided down by programmable dividers
17 * to produce the needed clocks. The PLLs operate independently of one
18 * another.
19 */
20#define EP93XX_EXT_CLK_RATE 14745600
21#define EP93XX_EXT_RTC_RATE 32768
12 22
13#include "ts72xx.h" 23#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4)
24#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16)
14 25
15#endif 26#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index fd5f081cc8b7..cebcc1c53d63 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -1,8 +1,21 @@
1/* 1/*
2 * arch/arm/mach-ep93xx/include/mach/io.h 2 * arch/arm/mach-ep93xx/include/mach/io.h
3 */ 3 */
4#ifndef __ASM_MACH_IO_H
5#define __ASM_MACH_IO_H
4 6
5#define IO_SPACE_LIMIT 0xffffffff 7#define IO_SPACE_LIMIT 0xffffffff
6 8
7#define __io(p) __typesafe_io(p) 9#define __io(p) __typesafe_io(p)
8#define __mem_pci(p) (p) 10#define __mem_pci(p) (p)
11
12/*
13 * A typesafe __io() variation for variable initialisers
14 */
15#ifdef __ASSEMBLER__
16#define IOMEM(p) p
17#else
18#define IOMEM(p) ((void __iomem __force *)(p))
19#endif
20
21#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 05f0f4f2f3ce..5f5fa6574d34 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -5,6 +5,7 @@
5#ifndef __ASSEMBLY__ 5#ifndef __ASSEMBLY__
6 6
7struct i2c_board_info; 7struct i2c_board_info;
8struct platform_device;
8 9
9struct ep93xx_eth_data 10struct ep93xx_eth_data
10{ 11{
@@ -15,8 +16,27 @@ struct ep93xx_eth_data
15void ep93xx_map_io(void); 16void ep93xx_map_io(void);
16void ep93xx_init_irq(void); 17void ep93xx_init_irq(void);
17void ep93xx_init_time(unsigned long); 18void ep93xx_init_time(unsigned long);
19
20/* EP93xx System Controller software locked register write */
21void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
22void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
23
24static inline void ep93xx_devcfg_set_bits(unsigned int bits)
25{
26 ep93xx_devcfg_set_clear(bits, 0x00);
27}
28
29static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
30{
31 ep93xx_devcfg_set_clear(0x00, bits);
32}
33
18void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); 34void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
19void ep93xx_register_i2c(struct i2c_board_info *devices, int num); 35void ep93xx_register_i2c(struct i2c_board_info *devices, int num);
36void ep93xx_register_pwm(int pwm0, int pwm1);
37int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
38void ep93xx_pwm_release_gpio(struct platform_device *pdev);
39
20void ep93xx_init_devices(void); 40void ep93xx_init_devices(void);
21extern struct sys_timer ep93xx_timer; 41extern struct sys_timer ep93xx_timer;
22 42
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
index ed8f35e4f068..6d661fe9d66c 100644
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ b/arch/arm/mach-ep93xx/include/mach/system.h
@@ -11,15 +11,13 @@ static inline void arch_idle(void)
11 11
12static inline void arch_reset(char mode, const char *cmd) 12static inline void arch_reset(char mode, const char *cmd)
13{ 13{
14 u32 devicecfg;
15
16 local_irq_disable(); 14 local_irq_disable();
17 15
18 devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG); 16 /*
19 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 17 * Set then clear the SWRST bit to initiate a software reset
20 __raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG); 18 */
21 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); 19 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
22 __raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG); 20 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
23 21
24 while (1) 22 while (1)
25 ; 23 ;
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
index 411734422c1d..3bd934e9a7f1 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -67,7 +67,6 @@
67 67
68 68
69#ifndef __ASSEMBLY__ 69#ifndef __ASSEMBLY__
70#include <linux/io.h>
71 70
72static inline int board_is_ts7200(void) 71static inline int board_is_ts7200(void)
73{ 72{
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 15d6815d78c4..0a313e82fb74 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -9,21 +9,16 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/ioport.h>
15#include <linux/kernel.h> 12#include <linux/kernel.h>
16#include <linux/mm.h> 13#include <linux/init.h>
17#include <linux/platform_device.h> 14#include <linux/platform_device.h>
18#include <linux/sched.h>
19#include <linux/io.h>
20#include <linux/i2c.h>
21#include <linux/mtd/physmap.h> 15#include <linux/mtd/physmap.h>
22 16
23#include <mach/hardware.h> 17#include <mach/hardware.h>
24 18
25#include <asm/mach/arch.h>
26#include <asm/mach-types.h> 19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21
27 22
28static struct ep93xx_eth_data micro9_eth_data = { 23static struct ep93xx_eth_data micro9_eth_data = {
29 .phy_id = 0x1f, 24 .phy_id = 0x1f,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index aaf1371412af..259f7822ba52 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -12,19 +12,18 @@
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/mtd/physmap.h>
20#include <linux/platform_device.h> 15#include <linux/platform_device.h>
21#include <linux/m48t86.h>
22#include <linux/io.h> 16#include <linux/io.h>
23#include <linux/i2c.h> 17#include <linux/m48t86.h>
18#include <linux/mtd/physmap.h>
19
24#include <mach/hardware.h> 20#include <mach/hardware.h>
21#include <mach/ts72xx.h>
22
25#include <asm/mach-types.h> 23#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h> 24#include <asm/mach/map.h>
25#include <asm/mach/arch.h>
26
28 27
29static struct map_desc ts72xx_io_desc[] __initdata = { 28static struct map_desc ts72xx_io_desc[] __initdata = {
30 { 29 {
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 15:03:45 -0500