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-rw-r--r--arch/arm/mach-dove/common.c68
1 files changed, 45 insertions, 23 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 00247c771313..bc22056200ae 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -27,6 +27,22 @@
27#include <plat/time.h> 27#include <plat/time.h>
28#include "common.h" 28#include "common.h"
29 29
30/* These can go away once Dove uses the mvebu-mbus DT binding */
31#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
32#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
33#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
34#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
35#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
36#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
37#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
38#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
39#define DOVE_MBUS_CESA_TARGET 0x3
40#define DOVE_MBUS_CESA_ATTR 0x1
41#define DOVE_MBUS_BOOTROM_TARGET 0x1
42#define DOVE_MBUS_BOOTROM_ATTR 0xfd
43#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
44#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
45
30/***************************************************************************** 46/*****************************************************************************
31 * I/O Address Mapping 47 * I/O Address Mapping
32 ****************************************************************************/ 48 ****************************************************************************/
@@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void)
332{ 348{
333 /* 349 /*
334 * The PCIe windows will no longer be statically allocated 350 * The PCIe windows will no longer be statically allocated
335 * here once Dove is migrated to the pci-mvebu driver. 351 * here once Dove is migrated to the pci-mvebu driver. The
352 * non-PCIe windows will no longer be created here once Dove
353 * fully moves to DT.
336 */ 354 */
337 mvebu_mbus_add_window_remap_flags("pcie0.0", 355 mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
356 DOVE_MBUS_PCIE0_IO_ATTR,
338 DOVE_PCIE0_IO_PHYS_BASE, 357 DOVE_PCIE0_IO_PHYS_BASE,
339 DOVE_PCIE0_IO_SIZE, 358 DOVE_PCIE0_IO_SIZE,
340 DOVE_PCIE0_IO_BUS_BASE, 359 DOVE_PCIE0_IO_BUS_BASE);
341 MVEBU_MBUS_PCI_IO); 360 mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
342 mvebu_mbus_add_window_remap_flags("pcie1.0", 361 DOVE_MBUS_PCIE1_IO_ATTR,
343 DOVE_PCIE1_IO_PHYS_BASE, 362 DOVE_PCIE1_IO_PHYS_BASE,
344 DOVE_PCIE1_IO_SIZE, 363 DOVE_PCIE1_IO_SIZE,
345 DOVE_PCIE1_IO_BUS_BASE, 364 DOVE_PCIE1_IO_BUS_BASE);
346 MVEBU_MBUS_PCI_IO); 365 mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
347 mvebu_mbus_add_window_remap_flags("pcie0.0", 366 DOVE_MBUS_PCIE0_MEM_ATTR,
348 DOVE_PCIE0_MEM_PHYS_BASE, 367 DOVE_PCIE0_MEM_PHYS_BASE,
349 DOVE_PCIE0_MEM_SIZE, 368 DOVE_PCIE0_MEM_SIZE);
350 MVEBU_MBUS_NO_REMAP, 369 mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
351 MVEBU_MBUS_PCI_MEM); 370 DOVE_MBUS_PCIE1_MEM_ATTR,
352 mvebu_mbus_add_window_remap_flags("pcie1.0", 371 DOVE_PCIE1_MEM_PHYS_BASE,
353 DOVE_PCIE1_MEM_PHYS_BASE, 372 DOVE_PCIE1_MEM_SIZE);
354 DOVE_PCIE1_MEM_SIZE, 373 mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
355 MVEBU_MBUS_NO_REMAP, 374 DOVE_MBUS_CESA_ATTR,
356 MVEBU_MBUS_PCI_MEM); 375 DOVE_CESA_PHYS_BASE,
357 mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE, 376 DOVE_CESA_SIZE);
358 DOVE_CESA_SIZE); 377 mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
359 mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE, 378 DOVE_MBUS_BOOTROM_ATTR,
360 DOVE_BOOTROM_SIZE); 379 DOVE_BOOTROM_PHYS_BASE,
361 mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE, 380 DOVE_BOOTROM_SIZE);
362 DOVE_SCRATCHPAD_SIZE); 381 mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
382 DOVE_MBUS_SCRATCHPAD_ATTR,
383 DOVE_SCRATCHPAD_PHYS_BASE,
384 DOVE_SCRATCHPAD_SIZE);
363} 385}
364 386
365void __init dove_init(void) 387void __init dove_init(void)