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-rw-r--r--arch/arm/mach-davinci/Kconfig12
-rw-r--r--arch/arm/mach-davinci/Makefile2
-rw-r--r--arch/arm/mach-davinci/board-tnetv107x-evm.c287
-rw-r--r--arch/arm/mach-davinci/devices-tnetv107x.c434
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h97
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h269
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h47
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/tnetv107x.h61
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h6
-rw-r--r--arch/arm/mach-davinci/tnetv107x.c766
12 files changed, 0 insertions, 1997 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a075b3e0c5c7..3b98e348d8d5 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -51,11 +51,6 @@ config ARCH_DAVINCI_DM365
51 select AINTC 51 select AINTC
52 select ARCH_DAVINCI_DMx 52 select ARCH_DAVINCI_DMx
53 53
54config ARCH_DAVINCI_TNETV107X
55 bool "TNETV107X based system"
56 select CPU_V6
57 select CP_INTC
58
59comment "DaVinci Board Type" 54comment "DaVinci Board Type"
60 55
61config MACH_DA8XX_DT 56config MACH_DA8XX_DT
@@ -220,13 +215,6 @@ config GPIO_PCA953X
220config KEYBOARD_GPIO_POLLED 215config KEYBOARD_GPIO_POLLED
221 default MACH_DAVINCI_DA850_EVM 216 default MACH_DAVINCI_DA850_EVM
222 217
223config MACH_TNETV107X
224 bool "TI TNETV107X Reference Platform"
225 default ARCH_DAVINCI_TNETV107X
226 depends on ARCH_DAVINCI_TNETV107X
227 help
228 Say Y here to select the TI TNETV107X Evaluation Module.
229
230config MACH_MITYOMAPL138 218config MACH_MITYOMAPL138
231 bool "Critical Link MityDSP-L138/MityARM-1808 SoM" 219 bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
232 depends on ARCH_DAVINCI_DA850 220 depends on ARCH_DAVINCI_DA850
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 63997a1128e6..2204239ed243 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -16,7 +16,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += dm646x.o devices.o
16obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o 16obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o
17obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o 17obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o
18obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o 18obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o
19obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += tnetv107x.o devices-tnetv107x.o
20 19
21obj-$(CONFIG_AINTC) += irq.o 20obj-$(CONFIG_AINTC) += irq.o
22obj-$(CONFIG_CP_INTC) += cp_intc.o 21obj-$(CONFIG_CP_INTC) += cp_intc.o
@@ -32,7 +31,6 @@ obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o
32obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o 31obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
33obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o 32obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
34obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o 33obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
35obj-$(CONFIG_MACH_TNETV107X) += board-tnetv107x-evm.o
36obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o 34obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o
37obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o 35obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o
38 36
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
deleted file mode 100644
index 78ea395d2aca..000000000000
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ /dev/null
@@ -1,287 +0,0 @@
1/*
2 * Texas Instruments TNETV107X EVM Board Support
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/console.h>
18#include <linux/dma-mapping.h>
19#include <linux/interrupt.h>
20#include <linux/gpio.h>
21#include <linux/delay.h>
22#include <linux/platform_device.h>
23#include <linux/ratelimit.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h>
26#include <linux/input.h>
27#include <linux/input/matrix_keypad.h>
28#include <linux/spi/spi.h>
29#include <linux/platform_data/edma.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach-types.h>
33
34#include <mach/irqs.h>
35#include <mach/mux.h>
36#include <mach/cp_intc.h>
37#include <mach/tnetv107x.h>
38
39#define EVM_MMC_WP_GPIO 21
40#define EVM_MMC_CD_GPIO 24
41#define EVM_SPI_CS_GPIO 54
42
43static int initialize_gpio(int gpio, char *desc)
44{
45 int ret;
46
47 ret = gpio_request(gpio, desc);
48 if (ret < 0) {
49 pr_err_ratelimited("cannot open %s gpio\n", desc);
50 return -ENOSYS;
51 }
52 gpio_direction_input(gpio);
53 return gpio;
54}
55
56static int mmc_get_cd(int index)
57{
58 static int gpio;
59
60 if (!gpio)
61 gpio = initialize_gpio(EVM_MMC_CD_GPIO, "mmc card detect");
62
63 if (gpio < 0)
64 return gpio;
65
66 return gpio_get_value(gpio) ? 0 : 1;
67}
68
69static int mmc_get_ro(int index)
70{
71 static int gpio;
72
73 if (!gpio)
74 gpio = initialize_gpio(EVM_MMC_WP_GPIO, "mmc write protect");
75
76 if (gpio < 0)
77 return gpio;
78
79 return gpio_get_value(gpio) ? 1 : 0;
80}
81
82static struct davinci_mmc_config mmc_config = {
83 .get_cd = mmc_get_cd,
84 .get_ro = mmc_get_ro,
85 .wires = 4,
86 .max_freq = 50000000,
87 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
88};
89
90static const short sdio1_pins[] __initconst = {
91 TNETV107X_SDIO1_CLK_1, TNETV107X_SDIO1_CMD_1,
92 TNETV107X_SDIO1_DATA0_1, TNETV107X_SDIO1_DATA1_1,
93 TNETV107X_SDIO1_DATA2_1, TNETV107X_SDIO1_DATA3_1,
94 TNETV107X_GPIO21, TNETV107X_GPIO24,
95 -1
96};
97
98static const short uart1_pins[] __initconst = {
99 TNETV107X_UART1_RD, TNETV107X_UART1_TD,
100 -1
101};
102
103static const short ssp_pins[] __initconst = {
104 TNETV107X_SSP0_0, TNETV107X_SSP0_1, TNETV107X_SSP0_2,
105 TNETV107X_SSP1_0, TNETV107X_SSP1_1, TNETV107X_SSP1_2,
106 TNETV107X_SSP1_3, -1
107};
108
109static struct mtd_partition nand_partitions[] = {
110 /* bootloader (U-Boot, etc) in first 12 sectors */
111 {
112 .name = "bootloader",
113 .offset = 0,
114 .size = (12*SZ_128K),
115 .mask_flags = MTD_WRITEABLE, /* force read-only */
116 },
117 /* bootloader params in the next sector */
118 {
119 .name = "params",
120 .offset = MTDPART_OFS_NXTBLK,
121 .size = SZ_128K,
122 .mask_flags = MTD_WRITEABLE, /* force read-only */
123 },
124 /* kernel */
125 {
126 .name = "kernel",
127 .offset = MTDPART_OFS_NXTBLK,
128 .size = SZ_4M,
129 .mask_flags = 0,
130 },
131 /* file system */
132 {
133 .name = "filesystem",
134 .offset = MTDPART_OFS_NXTBLK,
135 .size = MTDPART_SIZ_FULL,
136 .mask_flags = 0,
137 }
138};
139
140static struct davinci_nand_pdata nand_config = {
141 .mask_cle = 0x4000,
142 .mask_ale = 0x2000,
143 .parts = nand_partitions,
144 .nr_parts = ARRAY_SIZE(nand_partitions),
145 .ecc_mode = NAND_ECC_HW,
146 .bbt_options = NAND_BBT_USE_FLASH,
147 .ecc_bits = 1,
148};
149
150static struct davinci_uart_config serial_config __initconst = {
151 .enabled_uarts = BIT(1),
152};
153
154static const uint32_t keymap[] = {
155 KEY(0, 0, KEY_NUMERIC_1),
156 KEY(0, 1, KEY_NUMERIC_2),
157 KEY(0, 2, KEY_NUMERIC_3),
158 KEY(0, 3, KEY_FN_F1),
159 KEY(0, 4, KEY_MENU),
160
161 KEY(1, 0, KEY_NUMERIC_4),
162 KEY(1, 1, KEY_NUMERIC_5),
163 KEY(1, 2, KEY_NUMERIC_6),
164 KEY(1, 3, KEY_UP),
165 KEY(1, 4, KEY_FN_F2),
166
167 KEY(2, 0, KEY_NUMERIC_7),
168 KEY(2, 1, KEY_NUMERIC_8),
169 KEY(2, 2, KEY_NUMERIC_9),
170 KEY(2, 3, KEY_LEFT),
171 KEY(2, 4, KEY_ENTER),
172
173 KEY(3, 0, KEY_NUMERIC_STAR),
174 KEY(3, 1, KEY_NUMERIC_0),
175 KEY(3, 2, KEY_NUMERIC_POUND),
176 KEY(3, 3, KEY_DOWN),
177 KEY(3, 4, KEY_RIGHT),
178
179 KEY(4, 0, KEY_FN_F3),
180 KEY(4, 1, KEY_FN_F4),
181 KEY(4, 2, KEY_MUTE),
182 KEY(4, 3, KEY_HOME),
183 KEY(4, 4, KEY_BACK),
184
185 KEY(5, 0, KEY_VOLUMEDOWN),
186 KEY(5, 1, KEY_VOLUMEUP),
187 KEY(5, 2, KEY_F1),
188 KEY(5, 3, KEY_F2),
189 KEY(5, 4, KEY_F3),
190};
191
192static const struct matrix_keymap_data keymap_data = {
193 .keymap = keymap,
194 .keymap_size = ARRAY_SIZE(keymap),
195};
196
197static struct matrix_keypad_platform_data keypad_config = {
198 .keymap_data = &keymap_data,
199 .num_row_gpios = 6,
200 .num_col_gpios = 5,
201 .debounce_ms = 0, /* minimum */
202 .active_low = 0, /* pull up realization */
203 .no_autorepeat = 0,
204};
205
206static void spi_select_device(int cs)
207{
208 static int gpio;
209
210 if (!gpio) {
211 int ret;
212 ret = gpio_request(EVM_SPI_CS_GPIO, "spi chipsel");
213 if (ret < 0) {
214 pr_err("cannot open spi chipsel gpio\n");
215 gpio = -ENOSYS;
216 return;
217 } else {
218 gpio = EVM_SPI_CS_GPIO;
219 gpio_direction_output(gpio, 0);
220 }
221 }
222
223 if (gpio < 0)
224 return;
225
226 return gpio_set_value(gpio, cs ? 1 : 0);
227}
228
229static struct ti_ssp_spi_data spi_master_data = {
230 .num_cs = 2,
231 .select = spi_select_device,
232 .iosel = SSP_PIN_SEL(0, SSP_CLOCK) | SSP_PIN_SEL(1, SSP_DATA) |
233 SSP_PIN_SEL(2, SSP_CHIPSEL) | SSP_PIN_SEL(3, SSP_IN) |
234 SSP_INPUT_SEL(3),
235};
236
237static struct ti_ssp_data ssp_config = {
238 .out_clock = 250 * 1000,
239 .dev_data = {
240 [1] = {
241 .dev_name = "ti-ssp-spi",
242 .pdata = &spi_master_data,
243 .pdata_size = sizeof(spi_master_data),
244 },
245 },
246};
247
248static struct tnetv107x_device_info evm_device_info __initconst = {
249 .serial_config = &serial_config,
250 .mmc_config[1] = &mmc_config, /* controller 1 */
251 .nand_config[0] = &nand_config, /* chip select 0 */
252 .keypad_config = &keypad_config,
253 .ssp_config = &ssp_config,
254};
255
256static struct spi_board_info spi_info[] __initconst = {
257};
258
259static __init void tnetv107x_evm_board_init(void)
260{
261 davinci_cfg_reg_list(sdio1_pins);
262 davinci_cfg_reg_list(uart1_pins);
263 davinci_cfg_reg_list(ssp_pins);
264
265 tnetv107x_devices_init(&evm_device_info);
266
267 spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
268}
269
270#ifdef CONFIG_SERIAL_8250_CONSOLE
271static int __init tnetv107x_evm_console_init(void)
272{
273 return add_preferred_console("ttyS", 0, "115200");
274}
275console_initcall(tnetv107x_evm_console_init);
276#endif
277
278MACHINE_START(TNETV107X, "TNETV107X EVM")
279 .atag_offset = 0x100,
280 .map_io = tnetv107x_init,
281 .init_irq = cp_intc_init,
282 .init_time = davinci_timer_init,
283 .init_machine = tnetv107x_evm_board_init,
284 .init_late = davinci_init_late,
285 .dma_zone_size = SZ_128M,
286 .restart = tnetv107x_restart,
287MACHINE_END
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
deleted file mode 100644
index 01d8686e553c..000000000000
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ /dev/null
@@ -1,434 +0,0 @@
1/*
2 * Texas Instruments TNETV107X SoC devices
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/clk.h>
20#include <linux/slab.h>
21#include <linux/platform_data/edma.h>
22
23#include <mach/common.h>
24#include <mach/irqs.h>
25#include <mach/tnetv107x.h>
26
27#include "clock.h"
28
29/* Base addresses for on-chip devices */
30#define TNETV107X_TPCC_BASE 0x01c00000
31#define TNETV107X_TPTC0_BASE 0x01c10000
32#define TNETV107X_TPTC1_BASE 0x01c10400
33#define TNETV107X_WDOG_BASE 0x08086700
34#define TNETV107X_TSC_BASE 0x08088500
35#define TNETV107X_SDIO0_BASE 0x08088700
36#define TNETV107X_SDIO1_BASE 0x08088800
37#define TNETV107X_KEYPAD_BASE 0x08088a00
38#define TNETV107X_SSP_BASE 0x08088c00
39#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
40#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
41#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
42#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
43#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
44
45/* TNETV107X specific EDMA3 information */
46#define EDMA_TNETV107X_NUM_DMACH 64
47#define EDMA_TNETV107X_NUM_TCC 64
48#define EDMA_TNETV107X_NUM_PARAMENTRY 128
49#define EDMA_TNETV107X_NUM_EVQUE 2
50#define EDMA_TNETV107X_NUM_TC 2
51#define EDMA_TNETV107X_CHMAP_EXIST 0
52#define EDMA_TNETV107X_NUM_REGIONS 4
53#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u
54#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu
55
56#define TNETV107X_DMACH_SDIO0_RX 26
57#define TNETV107X_DMACH_SDIO0_TX 27
58#define TNETV107X_DMACH_SDIO1_RX 28
59#define TNETV107X_DMACH_SDIO1_TX 29
60
61static s8 edma_tc_mapping[][2] = {
62 /* event queue no TC no */
63 { 0, 0 },
64 { 1, 1 },
65 { -1, -1 }
66};
67
68static s8 edma_priority_mapping[][2] = {
69 /* event queue no Prio */
70 { 0, 3 },
71 { 1, 7 },
72 { -1, -1 }
73};
74
75static struct edma_soc_info edma_cc0_info = {
76 .n_channel = EDMA_TNETV107X_NUM_DMACH,
77 .n_region = EDMA_TNETV107X_NUM_REGIONS,
78 .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY,
79 .n_tc = EDMA_TNETV107X_NUM_TC,
80 .n_cc = 1,
81 .queue_tc_mapping = edma_tc_mapping,
82 .queue_priority_mapping = edma_priority_mapping,
83 .default_queue = EVENTQ_1,
84};
85
86static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
87 &edma_cc0_info,
88};
89
90static struct resource edma_resources[] = {
91 {
92 .name = "edma_cc0",
93 .start = TNETV107X_TPCC_BASE,
94 .end = TNETV107X_TPCC_BASE + SZ_32K - 1,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .name = "edma_tc0",
99 .start = TNETV107X_TPTC0_BASE,
100 .end = TNETV107X_TPTC0_BASE + SZ_1K - 1,
101 .flags = IORESOURCE_MEM,
102 },
103 {
104 .name = "edma_tc1",
105 .start = TNETV107X_TPTC1_BASE,
106 .end = TNETV107X_TPTC1_BASE + SZ_1K - 1,
107 .flags = IORESOURCE_MEM,
108 },
109 {
110 .name = "edma0",
111 .start = IRQ_TNETV107X_TPCC,
112 .flags = IORESOURCE_IRQ,
113 },
114 {
115 .name = "edma0_err",
116 .start = IRQ_TNETV107X_TPCC_ERR,
117 .flags = IORESOURCE_IRQ,
118 },
119};
120
121static struct platform_device edma_device = {
122 .name = "edma",
123 .id = -1,
124 .num_resources = ARRAY_SIZE(edma_resources),
125 .resource = edma_resources,
126 .dev.platform_data = tnetv107x_edma_info,
127};
128
129static struct plat_serial8250_port serial0_platform_data[] = {
130 {
131 .mapbase = TNETV107X_UART0_BASE,
132 .irq = IRQ_TNETV107X_UART0,
133 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
134 UPF_FIXED_TYPE | UPF_IOREMAP,
135 .type = PORT_AR7,
136 .iotype = UPIO_MEM32,
137 .regshift = 2,
138 },
139 {
140 .flags = 0,
141 }
142};
143static struct plat_serial8250_port serial1_platform_data[] = {
144 {
145 .mapbase = TNETV107X_UART1_BASE,
146 .irq = IRQ_TNETV107X_UART1,
147 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
148 UPF_FIXED_TYPE | UPF_IOREMAP,
149 .type = PORT_AR7,
150 .iotype = UPIO_MEM32,
151 .regshift = 2,
152 },
153 {
154 .flags = 0,
155 }
156};
157static struct plat_serial8250_port serial2_platform_data[] = {
158 {
159 .mapbase = TNETV107X_UART2_BASE,
160 .irq = IRQ_TNETV107X_UART2,
161 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
162 UPF_FIXED_TYPE | UPF_IOREMAP,
163 .type = PORT_AR7,
164 .iotype = UPIO_MEM32,
165 .regshift = 2,
166 },
167 {
168 .flags = 0,
169 }
170};
171
172
173struct platform_device tnetv107x_serial_device[] = {
174 {
175 .name = "serial8250",
176 .id = PLAT8250_DEV_PLATFORM,
177 .dev.platform_data = serial0_platform_data,
178 },
179 {
180 .name = "serial8250",
181 .id = PLAT8250_DEV_PLATFORM1,
182 .dev.platform_data = serial1_platform_data,
183 },
184 {
185 .name = "serial8250",
186 .id = PLAT8250_DEV_PLATFORM2,
187 .dev.platform_data = serial2_platform_data,
188 },
189 {
190 }
191};
192
193static struct resource mmc0_resources[] = {
194 { /* Memory mapped registers */
195 .start = TNETV107X_SDIO0_BASE,
196 .end = TNETV107X_SDIO0_BASE + 0x0ff,
197 .flags = IORESOURCE_MEM
198 },
199 { /* MMC interrupt */
200 .start = IRQ_TNETV107X_MMC0,
201 .flags = IORESOURCE_IRQ
202 },
203 { /* SDIO interrupt */
204 .start = IRQ_TNETV107X_SDIO0,
205 .flags = IORESOURCE_IRQ
206 },
207 { /* DMA RX */
208 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
209 .flags = IORESOURCE_DMA
210 },
211 { /* DMA TX */
212 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
213 .flags = IORESOURCE_DMA
214 },
215};
216
217static struct resource mmc1_resources[] = {
218 { /* Memory mapped registers */
219 .start = TNETV107X_SDIO1_BASE,
220 .end = TNETV107X_SDIO1_BASE + 0x0ff,
221 .flags = IORESOURCE_MEM
222 },
223 { /* MMC interrupt */
224 .start = IRQ_TNETV107X_MMC1,
225 .flags = IORESOURCE_IRQ
226 },
227 { /* SDIO interrupt */
228 .start = IRQ_TNETV107X_SDIO1,
229 .flags = IORESOURCE_IRQ
230 },
231 { /* DMA RX */
232 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
233 .flags = IORESOURCE_DMA
234 },
235 { /* DMA TX */
236 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
237 .flags = IORESOURCE_DMA
238 },
239};
240
241static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
242static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
243
244static struct platform_device mmc_devices[2] = {
245 {
246 .name = "dm6441-mmc",
247 .id = 0,
248 .dev = {
249 .dma_mask = &mmc0_dma_mask,
250 .coherent_dma_mask = DMA_BIT_MASK(32),
251 },
252 .num_resources = ARRAY_SIZE(mmc0_resources),
253 .resource = mmc0_resources
254 },
255 {
256 .name = "dm6441-mmc",
257 .id = 1,
258 .dev = {
259 .dma_mask = &mmc1_dma_mask,
260 .coherent_dma_mask = DMA_BIT_MASK(32),
261 },
262 .num_resources = ARRAY_SIZE(mmc1_resources),
263 .resource = mmc1_resources
264 },
265};
266
267static const u32 emif_windows[] = {
268 TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
269 TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
270};
271
272static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
273
274static struct resource wdt_resources[] = {
275 {
276 .start = TNETV107X_WDOG_BASE,
277 .end = TNETV107X_WDOG_BASE + SZ_4K - 1,
278 .flags = IORESOURCE_MEM,
279 },
280};
281
282struct platform_device tnetv107x_wdt_device = {
283 .name = "tnetv107x_wdt",
284 .id = 0,
285 .num_resources = ARRAY_SIZE(wdt_resources),
286 .resource = wdt_resources,
287};
288
289static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
290{
291 struct resource res[2];
292 struct platform_device *pdev;
293 u32 range;
294 int ret;
295
296 /* Figure out the resource range from the ale/cle masks */
297 range = max(data->mask_cle, data->mask_ale);
298 range = PAGE_ALIGN(range + 4) - 1;
299
300 if (range >= emif_window_sizes[chipsel])
301 return -EINVAL;
302
303 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
304 if (!pdev)
305 return -ENOMEM;
306
307 pdev->name = "davinci_nand";
308 pdev->id = chipsel;
309 pdev->dev.platform_data = data;
310
311 memset(res, 0, sizeof(res));
312
313 res[0].start = emif_windows[chipsel];
314 res[0].end = res[0].start + range;
315 res[0].flags = IORESOURCE_MEM;
316
317 res[1].start = TNETV107X_ASYNC_EMIF_CNTRL_BASE;
318 res[1].end = res[1].start + SZ_4K - 1;
319 res[1].flags = IORESOURCE_MEM;
320
321 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
322 if (ret < 0) {
323 kfree(pdev);
324 return ret;
325 }
326
327 return platform_device_register(pdev);
328}
329
330static struct resource keypad_resources[] = {
331 {
332 .start = TNETV107X_KEYPAD_BASE,
333 .end = TNETV107X_KEYPAD_BASE + 0xff,
334 .flags = IORESOURCE_MEM,
335 },
336 {
337 .start = IRQ_TNETV107X_KEYPAD,
338 .flags = IORESOURCE_IRQ,
339 .name = "press",
340 },
341 {
342 .start = IRQ_TNETV107X_KEYPAD_FREE,
343 .flags = IORESOURCE_IRQ,
344 .name = "release",
345 },
346};
347
348static struct platform_device keypad_device = {
349 .name = "tnetv107x-keypad",
350 .num_resources = ARRAY_SIZE(keypad_resources),
351 .resource = keypad_resources,
352};
353
354static struct resource tsc_resources[] = {
355 {
356 .start = TNETV107X_TSC_BASE,
357 .end = TNETV107X_TSC_BASE + 0xff,
358 .flags = IORESOURCE_MEM,
359 },
360 {
361 .start = IRQ_TNETV107X_TSC,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366static struct platform_device tsc_device = {
367 .name = "tnetv107x-ts",
368 .num_resources = ARRAY_SIZE(tsc_resources),
369 .resource = tsc_resources,
370};
371
372static struct resource ssp_resources[] = {
373 {
374 .start = TNETV107X_SSP_BASE,
375 .end = TNETV107X_SSP_BASE + 0x1ff,
376 .flags = IORESOURCE_MEM,
377 },
378 {
379 .start = IRQ_TNETV107X_SSP,
380 .flags = IORESOURCE_IRQ,
381 },
382};
383
384static struct platform_device ssp_device = {
385 .name = "ti-ssp",
386 .id = -1,
387 .num_resources = ARRAY_SIZE(ssp_resources),
388 .resource = ssp_resources,
389};
390
391void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
392{
393 int i, error;
394 struct clk *tsc_clk;
395
396 /*
397 * The reset defaults for tnetv107x tsc clock divider is set too high.
398 * This forces the clock down to a range that allows the ADC to
399 * complete sample conversion in time.
400 */
401 tsc_clk = clk_get(NULL, "sys_tsc_clk");
402 if (!IS_ERR(tsc_clk)) {
403 error = clk_set_rate(tsc_clk, 5000000);
404 WARN_ON(error < 0);
405 clk_put(tsc_clk);
406 }
407
408 platform_device_register(&edma_device);
409 platform_device_register(&tnetv107x_wdt_device);
410 platform_device_register(&tsc_device);
411
412 if (info->serial_config)
413 davinci_serial_init(tnetv107x_serial_device);
414
415 for (i = 0; i < 2; i++)
416 if (info->mmc_config[i]) {
417 mmc_devices[i].dev.platform_data = info->mmc_config[i];
418 platform_device_register(&mmc_devices[i]);
419 }
420
421 for (i = 0; i < 4; i++)
422 if (info->nand_config[i])
423 nand_init(i, info->nand_config[i]);
424
425 if (info->keypad_config) {
426 keypad_device.dev.platform_data = info->keypad_config;
427 platform_device_register(&keypad_device);
428 }
429
430 if (info->ssp_config) {
431 ssp_device.dev.platform_data = info->ssp_config;
432 platform_device_register(&ssp_device);
433 }
434}
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 957fb87e832e..1fc84e21664d 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -33,7 +33,6 @@ struct davinci_id {
33#define DAVINCI_CPU_ID_DM365 0x03650000 33#define DAVINCI_CPU_ID_DM365 0x03650000
34#define DAVINCI_CPU_ID_DA830 0x08300000 34#define DAVINCI_CPU_ID_DA830 0x08300000
35#define DAVINCI_CPU_ID_DA850 0x08500000 35#define DAVINCI_CPU_ID_DA850 0x08500000
36#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
37 36
38#define IS_DAVINCI_CPU(type, id) \ 37#define IS_DAVINCI_CPU(type, id) \
39static inline int is_davinci_ ##type(void) \ 38static inline int is_davinci_ ##type(void) \
@@ -47,7 +46,6 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
47IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) 46IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
48IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) 47IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
49IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) 48IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
50IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
51 49
52#ifdef CONFIG_ARCH_DAVINCI_DM644x 50#ifdef CONFIG_ARCH_DAVINCI_DM644x
53#define cpu_is_davinci_dm644x() is_davinci_dm644x() 51#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -85,10 +83,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
85#define cpu_is_davinci_da850() 0 83#define cpu_is_davinci_da850() 0
86#endif 84#endif
87 85
88#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
89#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
90#else
91#define cpu_is_davinci_tnetv107x() 0
92#endif
93
94#endif 86#endif
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index ec76c7775c2e..354af71798dc 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -401,103 +401,6 @@
401 401
402#define DA850_N_CP_INTC_IRQ 101 402#define DA850_N_CP_INTC_IRQ 101
403 403
404
405/* TNETV107X specific interrupts */
406#define IRQ_TNETV107X_TDM1_TXDMA 0
407#define IRQ_TNETV107X_EXT_INT_0 1
408#define IRQ_TNETV107X_EXT_INT_1 2
409#define IRQ_TNETV107X_GPIO_INT12 3
410#define IRQ_TNETV107X_GPIO_INT13 4
411#define IRQ_TNETV107X_TIMER_0_TINT12 5
412#define IRQ_TNETV107X_TIMER_1_TINT12 6
413#define IRQ_TNETV107X_UART0 7
414#define IRQ_TNETV107X_TDM1_RXDMA 8
415#define IRQ_TNETV107X_MCDMA_INT0 9
416#define IRQ_TNETV107X_MCDMA_INT1 10
417#define IRQ_TNETV107X_TPCC 11
418#define IRQ_TNETV107X_TPCC_INT0 12
419#define IRQ_TNETV107X_TPCC_INT1 13
420#define IRQ_TNETV107X_TPCC_INT2 14
421#define IRQ_TNETV107X_TPCC_INT3 15
422#define IRQ_TNETV107X_TPTC0 16
423#define IRQ_TNETV107X_TPTC1 17
424#define IRQ_TNETV107X_TIMER_0_TINT34 18
425#define IRQ_TNETV107X_ETHSS 19
426#define IRQ_TNETV107X_TIMER_1_TINT34 20
427#define IRQ_TNETV107X_DSP2ARM_INT0 21
428#define IRQ_TNETV107X_DSP2ARM_INT1 22
429#define IRQ_TNETV107X_ARM_NPMUIRQ 23
430#define IRQ_TNETV107X_USB1 24
431#define IRQ_TNETV107X_VLYNQ 25
432#define IRQ_TNETV107X_UART0_DMATX 26
433#define IRQ_TNETV107X_UART0_DMARX 27
434#define IRQ_TNETV107X_TDM1_TXMCSP 28
435#define IRQ_TNETV107X_SSP 29
436#define IRQ_TNETV107X_MCDMA_INT2 30
437#define IRQ_TNETV107X_MCDMA_INT3 31
438#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
439#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
440#define IRQ_TNETV107X_USB0 34
441#define IRQ_TNETV107X_USB_CDMA 35
442#define IRQ_TNETV107X_LCD 36
443#define IRQ_TNETV107X_KEYPAD 37
444#define IRQ_TNETV107X_KEYPAD_FREE 38
445#define IRQ_TNETV107X_RNG 39
446#define IRQ_TNETV107X_PKA 40
447#define IRQ_TNETV107X_TDM0_TXDMA 41
448#define IRQ_TNETV107X_TDM0_RXDMA 42
449#define IRQ_TNETV107X_TDM0_TXMCSP 43
450#define IRQ_TNETV107X_TDM0_RXMCSP 44
451#define IRQ_TNETV107X_TDM1_RXMCSP 45
452#define IRQ_TNETV107X_SDIO1 46
453#define IRQ_TNETV107X_SDIO0 47
454#define IRQ_TNETV107X_TSC 48
455#define IRQ_TNETV107X_TS 49
456#define IRQ_TNETV107X_UART1 50
457#define IRQ_TNETV107X_MBX_LITE 51
458#define IRQ_TNETV107X_GPIO_INT00 52
459#define IRQ_TNETV107X_GPIO_INT01 53
460#define IRQ_TNETV107X_GPIO_INT02 54
461#define IRQ_TNETV107X_GPIO_INT03 55
462#define IRQ_TNETV107X_UART2 56
463#define IRQ_TNETV107X_UART2_DMATX 57
464#define IRQ_TNETV107X_UART2_DMARX 58
465#define IRQ_TNETV107X_IMCOP_IMX 59
466#define IRQ_TNETV107X_IMCOP_VLCD 60
467#define IRQ_TNETV107X_AES 61
468#define IRQ_TNETV107X_DES 62
469#define IRQ_TNETV107X_SHAMD5 63
470#define IRQ_TNETV107X_TPCC_ERR 68
471#define IRQ_TNETV107X_TPCC_PROT 69
472#define IRQ_TNETV107X_TPTC0_ERR 70
473#define IRQ_TNETV107X_TPTC1_ERR 71
474#define IRQ_TNETV107X_UART0_ERR 72
475#define IRQ_TNETV107X_UART1_ERR 73
476#define IRQ_TNETV107X_AEMIF_ERR 74
477#define IRQ_TNETV107X_DDR_ERR 75
478#define IRQ_TNETV107X_WDTARM_INT0 76
479#define IRQ_TNETV107X_MCDMA_ERR 77
480#define IRQ_TNETV107X_GPIO_ERR 78
481#define IRQ_TNETV107X_MPU_ADDR 79
482#define IRQ_TNETV107X_MPU_PROT 80
483#define IRQ_TNETV107X_IOPU_ADDR 81
484#define IRQ_TNETV107X_IOPU_PROT 82
485#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
486#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
487#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
488#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
489#define IRQ_TNETV107X_PLL_UNLOCK 87
490#define IRQ_TNETV107X_WDTDSP_INT0 88
491#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
492#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
493#define IRQ_TNETV107X_PBIST_CPU 91
494#define IRQ_TNETV107X_WDTARM 92
495#define IRQ_TNETV107X_PSC 93
496#define IRQ_TNETV107X_MMC0 94
497#define IRQ_TNETV107X_MMC1 95
498
499#define TNETV107X_N_CP_INTC_IRQ 96
500
501/* da850 currently has the most gpio pins (144) */ 404/* da850 currently has the most gpio pins (144) */
502#define DAVINCI_N_GPIO 144 405#define DAVINCI_N_GPIO 144
503/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ 406/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 9e95b8a1edb6..631655e68ae0 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -972,275 +972,6 @@ enum davinci_da850_index {
972 DA850_VPIF_CLKO3, 972 DA850_VPIF_CLKO3,
973}; 973};
974 974
975enum davinci_tnetv107x_index {
976 TNETV107X_ASR_A00,
977 TNETV107X_GPIO32,
978 TNETV107X_ASR_A01,
979 TNETV107X_GPIO33,
980 TNETV107X_ASR_A02,
981 TNETV107X_GPIO34,
982 TNETV107X_ASR_A03,
983 TNETV107X_GPIO35,
984 TNETV107X_ASR_A04,
985 TNETV107X_GPIO36,
986 TNETV107X_ASR_A05,
987 TNETV107X_GPIO37,
988 TNETV107X_ASR_A06,
989 TNETV107X_GPIO38,
990 TNETV107X_ASR_A07,
991 TNETV107X_GPIO39,
992 TNETV107X_ASR_A08,
993 TNETV107X_GPIO40,
994 TNETV107X_ASR_A09,
995 TNETV107X_GPIO41,
996 TNETV107X_ASR_A10,
997 TNETV107X_GPIO42,
998 TNETV107X_ASR_A11,
999 TNETV107X_BOOT_STRP_0,
1000 TNETV107X_ASR_A12,
1001 TNETV107X_BOOT_STRP_1,
1002 TNETV107X_ASR_A13,
1003 TNETV107X_GPIO43,
1004 TNETV107X_ASR_A14,
1005 TNETV107X_GPIO44,
1006 TNETV107X_ASR_A15,
1007 TNETV107X_GPIO45,
1008 TNETV107X_ASR_A16,
1009 TNETV107X_GPIO46,
1010 TNETV107X_ASR_A17,
1011 TNETV107X_GPIO47,
1012 TNETV107X_ASR_A18,
1013 TNETV107X_GPIO48,
1014 TNETV107X_SDIO1_DATA3_0,
1015 TNETV107X_ASR_A19,
1016 TNETV107X_GPIO49,
1017 TNETV107X_SDIO1_DATA2_0,
1018 TNETV107X_ASR_A20,
1019 TNETV107X_GPIO50,
1020 TNETV107X_SDIO1_DATA1_0,
1021 TNETV107X_ASR_A21,
1022 TNETV107X_GPIO51,
1023 TNETV107X_SDIO1_DATA0_0,
1024 TNETV107X_ASR_A22,
1025 TNETV107X_GPIO52,
1026 TNETV107X_SDIO1_CMD_0,
1027 TNETV107X_ASR_A23,
1028 TNETV107X_GPIO53,
1029 TNETV107X_SDIO1_CLK_0,
1030 TNETV107X_ASR_BA_1,
1031 TNETV107X_GPIO54,
1032 TNETV107X_SYS_PLL_CLK,
1033 TNETV107X_ASR_CS0,
1034 TNETV107X_ASR_CS1,
1035 TNETV107X_ASR_CS2,
1036 TNETV107X_TDM_PLL_CLK,
1037 TNETV107X_ASR_CS3,
1038 TNETV107X_ETH_PHY_CLK,
1039 TNETV107X_ASR_D00,
1040 TNETV107X_GPIO55,
1041 TNETV107X_ASR_D01,
1042 TNETV107X_GPIO56,
1043 TNETV107X_ASR_D02,
1044 TNETV107X_GPIO57,
1045 TNETV107X_ASR_D03,
1046 TNETV107X_GPIO58,
1047 TNETV107X_ASR_D04,
1048 TNETV107X_GPIO59_0,
1049 TNETV107X_ASR_D05,
1050 TNETV107X_GPIO60_0,
1051 TNETV107X_ASR_D06,
1052 TNETV107X_GPIO61_0,
1053 TNETV107X_ASR_D07,
1054 TNETV107X_GPIO62_0,
1055 TNETV107X_ASR_D08,
1056 TNETV107X_GPIO63_0,
1057 TNETV107X_ASR_D09,
1058 TNETV107X_GPIO64_0,
1059 TNETV107X_ASR_D10,
1060 TNETV107X_SDIO1_DATA3_1,
1061 TNETV107X_ASR_D11,
1062 TNETV107X_SDIO1_DATA2_1,
1063 TNETV107X_ASR_D12,
1064 TNETV107X_SDIO1_DATA1_1,
1065 TNETV107X_ASR_D13,
1066 TNETV107X_SDIO1_DATA0_1,
1067 TNETV107X_ASR_D14,
1068 TNETV107X_SDIO1_CMD_1,
1069 TNETV107X_ASR_D15,
1070 TNETV107X_SDIO1_CLK_1,
1071 TNETV107X_ASR_OE,
1072 TNETV107X_BOOT_STRP_2,
1073 TNETV107X_ASR_RNW,
1074 TNETV107X_GPIO29_0,
1075 TNETV107X_ASR_WAIT,
1076 TNETV107X_GPIO30_0,
1077 TNETV107X_ASR_WE,
1078 TNETV107X_BOOT_STRP_3,
1079 TNETV107X_ASR_WE_DQM0,
1080 TNETV107X_GPIO31,
1081 TNETV107X_LCD_PD17_0,
1082 TNETV107X_ASR_WE_DQM1,
1083 TNETV107X_ASR_BA0_0,
1084 TNETV107X_VLYNQ_CLK,
1085 TNETV107X_GPIO14,
1086 TNETV107X_LCD_PD19_0,
1087 TNETV107X_VLYNQ_RXD0,
1088 TNETV107X_GPIO15,
1089 TNETV107X_LCD_PD20_0,
1090 TNETV107X_VLYNQ_RXD1,
1091 TNETV107X_GPIO16,
1092 TNETV107X_LCD_PD21_0,
1093 TNETV107X_VLYNQ_TXD0,
1094 TNETV107X_GPIO17,
1095 TNETV107X_LCD_PD22_0,
1096 TNETV107X_VLYNQ_TXD1,
1097 TNETV107X_GPIO18,
1098 TNETV107X_LCD_PD23_0,
1099 TNETV107X_SDIO0_CLK,
1100 TNETV107X_GPIO19,
1101 TNETV107X_SDIO0_CMD,
1102 TNETV107X_GPIO20,
1103 TNETV107X_SDIO0_DATA0,
1104 TNETV107X_GPIO21,
1105 TNETV107X_SDIO0_DATA1,
1106 TNETV107X_GPIO22,
1107 TNETV107X_SDIO0_DATA2,
1108 TNETV107X_GPIO23,
1109 TNETV107X_SDIO0_DATA3,
1110 TNETV107X_GPIO24,
1111 TNETV107X_EMU0,
1112 TNETV107X_EMU1,
1113 TNETV107X_RTCK,
1114 TNETV107X_TRST_N,
1115 TNETV107X_TCK,
1116 TNETV107X_TDI,
1117 TNETV107X_TDO,
1118 TNETV107X_TMS,
1119 TNETV107X_TDM1_CLK,
1120 TNETV107X_TDM1_RX,
1121 TNETV107X_TDM1_TX,
1122 TNETV107X_TDM1_FS,
1123 TNETV107X_KEYPAD_R0,
1124 TNETV107X_KEYPAD_R1,
1125 TNETV107X_KEYPAD_R2,
1126 TNETV107X_KEYPAD_R3,
1127 TNETV107X_KEYPAD_R4,
1128 TNETV107X_KEYPAD_R5,
1129 TNETV107X_KEYPAD_R6,
1130 TNETV107X_GPIO12,
1131 TNETV107X_KEYPAD_R7,
1132 TNETV107X_GPIO10,
1133 TNETV107X_KEYPAD_C0,
1134 TNETV107X_KEYPAD_C1,
1135 TNETV107X_KEYPAD_C2,
1136 TNETV107X_KEYPAD_C3,
1137 TNETV107X_KEYPAD_C4,
1138 TNETV107X_KEYPAD_C5,
1139 TNETV107X_KEYPAD_C6,
1140 TNETV107X_GPIO13,
1141 TNETV107X_TEST_CLK_IN,
1142 TNETV107X_KEYPAD_C7,
1143 TNETV107X_GPIO11,
1144 TNETV107X_SSP0_0,
1145 TNETV107X_SCC_DCLK,
1146 TNETV107X_LCD_PD20_1,
1147 TNETV107X_SSP0_1,
1148 TNETV107X_SCC_CS_N,
1149 TNETV107X_LCD_PD21_1,
1150 TNETV107X_SSP0_2,
1151 TNETV107X_SCC_D,
1152 TNETV107X_LCD_PD22_1,
1153 TNETV107X_SSP0_3,
1154 TNETV107X_SCC_RESETN,
1155 TNETV107X_LCD_PD23_1,
1156 TNETV107X_SSP1_0,
1157 TNETV107X_GPIO25,
1158 TNETV107X_UART2_CTS,
1159 TNETV107X_SSP1_1,
1160 TNETV107X_GPIO26,
1161 TNETV107X_UART2_RD,
1162 TNETV107X_SSP1_2,
1163 TNETV107X_GPIO27,
1164 TNETV107X_UART2_RTS,
1165 TNETV107X_SSP1_3,
1166 TNETV107X_GPIO28,
1167 TNETV107X_UART2_TD,
1168 TNETV107X_UART0_CTS,
1169 TNETV107X_UART0_RD,
1170 TNETV107X_UART0_RTS,
1171 TNETV107X_UART0_TD,
1172 TNETV107X_UART1_RD,
1173 TNETV107X_UART1_TD,
1174 TNETV107X_LCD_AC_NCS,
1175 TNETV107X_LCD_HSYNC_RNW,
1176 TNETV107X_LCD_VSYNC_A0,
1177 TNETV107X_LCD_MCLK,
1178 TNETV107X_LCD_PD16_0,
1179 TNETV107X_LCD_PCLK_E,
1180 TNETV107X_LCD_PD00,
1181 TNETV107X_LCD_PD01,
1182 TNETV107X_LCD_PD02,
1183 TNETV107X_LCD_PD03,
1184 TNETV107X_LCD_PD04,
1185 TNETV107X_LCD_PD05,
1186 TNETV107X_LCD_PD06,
1187 TNETV107X_LCD_PD07,
1188 TNETV107X_LCD_PD08,
1189 TNETV107X_GPIO59_1,
1190 TNETV107X_LCD_PD09,
1191 TNETV107X_GPIO60_1,
1192 TNETV107X_LCD_PD10,
1193 TNETV107X_ASR_BA0_1,
1194 TNETV107X_GPIO61_1,
1195 TNETV107X_LCD_PD11,
1196 TNETV107X_GPIO62_1,
1197 TNETV107X_LCD_PD12,
1198 TNETV107X_GPIO63_1,
1199 TNETV107X_LCD_PD13,
1200 TNETV107X_GPIO64_1,
1201 TNETV107X_LCD_PD14,
1202 TNETV107X_GPIO29_1,
1203 TNETV107X_LCD_PD15,
1204 TNETV107X_GPIO30_1,
1205 TNETV107X_EINT0,
1206 TNETV107X_GPIO08,
1207 TNETV107X_EINT1,
1208 TNETV107X_GPIO09,
1209 TNETV107X_GPIO00,
1210 TNETV107X_LCD_PD20_2,
1211 TNETV107X_TDM_CLK_IN_2,
1212 TNETV107X_GPIO01,
1213 TNETV107X_LCD_PD21_2,
1214 TNETV107X_24M_CLK_OUT_1,
1215 TNETV107X_GPIO02,
1216 TNETV107X_LCD_PD22_2,
1217 TNETV107X_GPIO03,
1218 TNETV107X_LCD_PD23_2,
1219 TNETV107X_GPIO04,
1220 TNETV107X_LCD_PD16_1,
1221 TNETV107X_USB0_RXERR,
1222 TNETV107X_GPIO05,
1223 TNETV107X_LCD_PD17_1,
1224 TNETV107X_TDM_CLK_IN_1,
1225 TNETV107X_GPIO06,
1226 TNETV107X_LCD_PD18,
1227 TNETV107X_24M_CLK_OUT_2,
1228 TNETV107X_GPIO07,
1229 TNETV107X_LCD_PD19_1,
1230 TNETV107X_USB1_RXERR,
1231 TNETV107X_ETH_PLL_CLK,
1232 TNETV107X_MDIO,
1233 TNETV107X_MDC,
1234 TNETV107X_AIC_MUTE_STAT_N,
1235 TNETV107X_TDM0_CLK,
1236 TNETV107X_AIC_HNS_EN_N,
1237 TNETV107X_TDM0_FS,
1238 TNETV107X_AIC_HDS_EN_STAT_N,
1239 TNETV107X_TDM0_TX,
1240 TNETV107X_AIC_HNF_EN_STAT_N,
1241 TNETV107X_TDM0_RX,
1242};
1243
1244#define PINMUX(x) (4 * (x)) 975#define PINMUX(x) (4 * (x))
1245 976
1246#ifdef CONFIG_DAVINCI_MUX 977#ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 0a22710493fd..99d47cfa301f 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -182,53 +182,6 @@
182#define DA8XX_LPSC1_CR_P3_SS 26 182#define DA8XX_LPSC1_CR_P3_SS 26
183#define DA8XX_LPSC1_L3_CBA_RAM 31 183#define DA8XX_LPSC1_L3_CBA_RAM 31
184 184
185/* TNETV107X LPSC Assignments */
186#define TNETV107X_LPSC_ARM 0
187#define TNETV107X_LPSC_GEM 1
188#define TNETV107X_LPSC_DDR2_PHY 2
189#define TNETV107X_LPSC_TPCC 3
190#define TNETV107X_LPSC_TPTC0 4
191#define TNETV107X_LPSC_TPTC1 5
192#define TNETV107X_LPSC_RAM 6
193#define TNETV107X_LPSC_MBX_LITE 7
194#define TNETV107X_LPSC_LCD 8
195#define TNETV107X_LPSC_ETHSS 9
196#define TNETV107X_LPSC_AEMIF 10
197#define TNETV107X_LPSC_CHIP_CFG 11
198#define TNETV107X_LPSC_TSC 12
199#define TNETV107X_LPSC_ROM 13
200#define TNETV107X_LPSC_UART2 14
201#define TNETV107X_LPSC_PKTSEC 15
202#define TNETV107X_LPSC_SECCTL 16
203#define TNETV107X_LPSC_KEYMGR 17
204#define TNETV107X_LPSC_KEYPAD 18
205#define TNETV107X_LPSC_GPIO 19
206#define TNETV107X_LPSC_MDIO 20
207#define TNETV107X_LPSC_SDIO0 21
208#define TNETV107X_LPSC_UART0 22
209#define TNETV107X_LPSC_UART1 23
210#define TNETV107X_LPSC_TIMER0 24
211#define TNETV107X_LPSC_TIMER1 25
212#define TNETV107X_LPSC_WDT_ARM 26
213#define TNETV107X_LPSC_WDT_DSP 27
214#define TNETV107X_LPSC_SSP 28
215#define TNETV107X_LPSC_TDM0 29
216#define TNETV107X_LPSC_VLYNQ 30
217#define TNETV107X_LPSC_MCDMA 31
218#define TNETV107X_LPSC_USB0 32
219#define TNETV107X_LPSC_TDM1 33
220#define TNETV107X_LPSC_DEBUGSS 34
221#define TNETV107X_LPSC_ETHSS_RGMII 35
222#define TNETV107X_LPSC_SYSTEM 36
223#define TNETV107X_LPSC_IMCOP 37
224#define TNETV107X_LPSC_SPARE 38
225#define TNETV107X_LPSC_SDIO1 39
226#define TNETV107X_LPSC_USB1 40
227#define TNETV107X_LPSC_USBSS 41
228#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
229#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
230#define TNETV107X_LPSC_MAX 44
231
232/* PSC register offsets */ 185/* PSC register offsets */
233#define EPCPR 0x070 186#define EPCPR 0x070
234#define PTCMD 0x120 187#define PTCMD 0x120
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index ce402cd21fa0..d4b4aa87964f 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -23,14 +23,6 @@
23#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) 23#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
24#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) 24#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
25 25
26#define TNETV107X_UART0_BASE 0x08108100
27#define TNETV107X_UART1_BASE 0x08088400
28#define TNETV107X_UART2_BASE 0x08108300
29
30#define TNETV107X_UART0_VIRT IOMEM(0xfee08100)
31#define TNETV107X_UART1_VIRT IOMEM(0xfed88400)
32#define TNETV107X_UART2_VIRT IOMEM(0xfee08300)
33
34/* DaVinci UART register offsets */ 26/* DaVinci UART register offsets */
35#define UART_DAVINCI_PWREMU 0x0c 27#define UART_DAVINCI_PWREMU 0x0c
36#define UART_DM646X_SCR 0x10 28#define UART_DM646X_SCR 0x10
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
deleted file mode 100644
index 494fcf5ccfe1..000000000000
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Texas Instruments TNETV107X SoC Specific Defines
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
16#define __ASM_ARCH_DAVINCI_TNETV107X_H
17
18#include <asm/sizes.h>
19
20#define TNETV107X_DDR_BASE 0x80000000
21
22/*
23 * Fixed mapping for early init starts here. If low-level debug is enabled,
24 * this area also gets mapped via io_pg_offset and io_phys by the boot code.
25 * To fit in with the io_pg_offset calculation, the io base address selected
26 * here _must_ be a multiple of 2^20.
27 */
28#define TNETV107X_IO_BASE 0x08000000
29#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M)
30
31#define TNETV107X_N_GPIO 65
32
33#ifndef __ASSEMBLY__
34
35#include <linux/serial_8250.h>
36#include <linux/input/matrix_keypad.h>
37#include <linux/mfd/ti_ssp.h>
38#include <linux/reboot.h>
39
40#include <linux/platform_data/mmc-davinci.h>
41#include <linux/platform_data/mtd-davinci.h>
42#include <mach/serial.h>
43
44struct tnetv107x_device_info {
45 struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
46 struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
47 struct matrix_keypad_platform_data *keypad_config;
48 struct ti_ssp_data *ssp_config;
49};
50
51extern struct platform_device tnetv107x_wdt_device;
52extern struct platform_device tnetv107x_serial_device[];
53
54extern void tnetv107x_init(void);
55extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
56extern void tnetv107x_irq_init(void);
57void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
58
59#endif
60
61#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index f49c2916aa3a..8fb97b93b6bb 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -68,9 +68,6 @@ static inline void set_uart_info(u32 phys)
68#define DEBUG_LL_DA8XX(machine, port) \ 68#define DEBUG_LL_DA8XX(machine, port) \
69 _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE) 69 _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
70 70
71#define DEBUG_LL_TNETV107X(machine, port) \
72 _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
73
74static inline void __arch_decomp_setup(unsigned long arch_id) 71static inline void __arch_decomp_setup(unsigned long arch_id)
75{ 72{
76 /* 73 /*
@@ -94,9 +91,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
94 DEBUG_LL_DA8XX(davinci_da850_evm, 2); 91 DEBUG_LL_DA8XX(davinci_da850_evm, 2);
95 DEBUG_LL_DA8XX(mityomapl138, 1); 92 DEBUG_LL_DA8XX(mityomapl138, 1);
96 DEBUG_LL_DA8XX(omapl138_hawkboard, 2); 93 DEBUG_LL_DA8XX(omapl138_hawkboard, 2);
97
98 /* TNETV107x boards */
99 DEBUG_LL_TNETV107X(tnetv107x, 1);
100 } while (0); 94 } while (0);
101} 95}
102 96
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
deleted file mode 100644
index f4d7fbb24b3b..000000000000
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ /dev/null
@@ -1,766 +0,0 @@
1/*
2 * Texas Instruments TNETV107X SoC Support
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/gpio.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/err.h>
21#include <linux/platform_device.h>
22#include <linux/reboot.h>
23
24#include <asm/mach/map.h>
25
26#include <mach/common.h>
27#include <mach/time.h>
28#include <mach/cputype.h>
29#include <mach/psc.h>
30#include <mach/cp_intc.h>
31#include <mach/irqs.h>
32#include <mach/hardware.h>
33#include <mach/tnetv107x.h>
34#include <mach/gpio-davinci.h>
35
36#include "clock.h"
37#include "mux.h"
38
39/* Base addresses for on-chip devices */
40#define TNETV107X_INTC_BASE 0x03000000
41#define TNETV107X_TIMER0_BASE 0x08086500
42#define TNETV107X_TIMER1_BASE 0x08086600
43#define TNETV107X_CHIP_CFG_BASE 0x08087000
44#define TNETV107X_GPIO_BASE 0x08088000
45#define TNETV107X_CLOCK_CONTROL_BASE 0x0808a000
46#define TNETV107X_PSC_BASE 0x0808b000
47
48/* Reference clock frequencies */
49#define OSC_FREQ_ONCHIP (24000 * 1000)
50#define OSC_FREQ_OFFCHIP_SYS (25000 * 1000)
51#define OSC_FREQ_OFFCHIP_ETH (25000 * 1000)
52#define OSC_FREQ_OFFCHIP_TDM (19200 * 1000)
53
54#define N_PLLS 3
55
56/* Clock Control Registers */
57struct clk_ctrl_regs {
58 u32 pll_bypass;
59 u32 _reserved0;
60 u32 gem_lrst;
61 u32 _reserved1;
62 u32 pll_unlock_stat;
63 u32 sys_unlock;
64 u32 eth_unlock;
65 u32 tdm_unlock;
66};
67
68/* SSPLL Registers */
69struct sspll_regs {
70 u32 modes;
71 u32 post_div;
72 u32 pre_div;
73 u32 mult_factor;
74 u32 divider_range;
75 u32 bw_divider;
76 u32 spr_amount;
77 u32 spr_rate_div;
78 u32 diag;
79};
80
81/* Watchdog Timer Registers */
82struct wdt_regs {
83 u32 kick_lock;
84 u32 kick;
85 u32 change_lock;
86 u32 change ;
87 u32 disable_lock;
88 u32 disable;
89 u32 prescale_lock;
90 u32 prescale;
91};
92
93static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
94
95static struct sspll_regs __iomem *sspll_regs[N_PLLS];
96static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
97
98/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
99static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
100
101/* offchip (external) reference clock frequencies */
102static u32 pll_ext_freq[] = {
103 OSC_FREQ_OFFCHIP_SYS,
104 OSC_FREQ_OFFCHIP_TDM,
105 OSC_FREQ_OFFCHIP_ETH
106};
107
108/* PSC control registers */
109static u32 psc_regs[] = { TNETV107X_PSC_BASE };
110
111/* Host map for interrupt controller */
112static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
113
114static unsigned long clk_sspll_recalc(struct clk *clk);
115
116/* Level 1 - the PLLs */
117#define define_pll_clk(cname, pll, divmask, base) \
118 static struct pll_data pll_##cname##_data = { \
119 .num = pll, \
120 .div_ratio_mask = divmask, \
121 .phys_base = base + \
122 TNETV107X_CLOCK_CONTROL_BASE, \
123 }; \
124 static struct clk pll_##cname##_clk = { \
125 .name = "pll_" #cname "_clk", \
126 .pll_data = &pll_##cname##_data, \
127 .flags = CLK_PLL, \
128 .recalc = clk_sspll_recalc, \
129 }
130
131define_pll_clk(sys, 0, 0x1ff, 0x600);
132define_pll_clk(tdm, 1, 0x0ff, 0x200);
133define_pll_clk(eth, 2, 0x0ff, 0x400);
134
135/* Level 2 - divided outputs from the PLLs */
136#define define_pll_div_clk(pll, cname, div) \
137 static struct clk pll##_##cname##_clk = { \
138 .name = #pll "_" #cname "_clk", \
139 .parent = &pll_##pll##_clk, \
140 .flags = CLK_PLL, \
141 .div_reg = PLLDIV##div, \
142 .set_rate = davinci_set_sysclk_rate, \
143 }
144
145define_pll_div_clk(sys, arm1176, 1);
146define_pll_div_clk(sys, dsp, 2);
147define_pll_div_clk(sys, ddr, 3);
148define_pll_div_clk(sys, full, 4);
149define_pll_div_clk(sys, lcd, 5);
150define_pll_div_clk(sys, vlynq_ref, 6);
151define_pll_div_clk(sys, tsc, 7);
152define_pll_div_clk(sys, half, 8);
153
154define_pll_div_clk(eth, 5mhz, 1);
155define_pll_div_clk(eth, 50mhz, 2);
156define_pll_div_clk(eth, 125mhz, 3);
157define_pll_div_clk(eth, 250mhz, 4);
158define_pll_div_clk(eth, 25mhz, 5);
159
160define_pll_div_clk(tdm, 0, 1);
161define_pll_div_clk(tdm, extra, 2);
162define_pll_div_clk(tdm, 1, 3);
163
164
165/* Level 3 - LPSC gated clocks */
166#define __lpsc_clk(cname, _parent, mod, flg) \
167 static struct clk clk_##cname = { \
168 .name = #cname, \
169 .parent = &_parent, \
170 .lpsc = TNETV107X_LPSC_##mod,\
171 .flags = flg, \
172 }
173
174#define lpsc_clk_enabled(cname, parent, mod) \
175 __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED)
176
177#define lpsc_clk(cname, parent, mod) \
178 __lpsc_clk(cname, parent, mod, 0)
179
180lpsc_clk_enabled(arm, sys_arm1176_clk, ARM);
181lpsc_clk_enabled(gem, sys_dsp_clk, GEM);
182lpsc_clk_enabled(ddr2_phy, sys_ddr_clk, DDR2_PHY);
183lpsc_clk_enabled(tpcc, sys_full_clk, TPCC);
184lpsc_clk_enabled(tptc0, sys_full_clk, TPTC0);
185lpsc_clk_enabled(tptc1, sys_full_clk, TPTC1);
186lpsc_clk_enabled(ram, sys_full_clk, RAM);
187lpsc_clk_enabled(aemif, sys_full_clk, AEMIF);
188lpsc_clk_enabled(chipcfg, sys_half_clk, CHIP_CFG);
189lpsc_clk_enabled(rom, sys_half_clk, ROM);
190lpsc_clk_enabled(secctl, sys_half_clk, SECCTL);
191lpsc_clk_enabled(keymgr, sys_half_clk, KEYMGR);
192lpsc_clk_enabled(gpio, sys_half_clk, GPIO);
193lpsc_clk_enabled(debugss, sys_half_clk, DEBUGSS);
194lpsc_clk_enabled(system, sys_half_clk, SYSTEM);
195lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST);
196lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST);
197lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM);
198lpsc_clk_enabled(timer1, sys_half_clk, TIMER1);
199
200lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE);
201lpsc_clk(ethss, eth_125mhz_clk, ETHSS);
202lpsc_clk(tsc, sys_tsc_clk, TSC);
203lpsc_clk(uart0, sys_half_clk, UART0);
204lpsc_clk(uart1, sys_half_clk, UART1);
205lpsc_clk(uart2, sys_half_clk, UART2);
206lpsc_clk(pktsec, sys_half_clk, PKTSEC);
207lpsc_clk(keypad, sys_half_clk, KEYPAD);
208lpsc_clk(mdio, sys_half_clk, MDIO);
209lpsc_clk(sdio0, sys_half_clk, SDIO0);
210lpsc_clk(sdio1, sys_half_clk, SDIO1);
211lpsc_clk(timer0, sys_half_clk, TIMER0);
212lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP);
213lpsc_clk(ssp, sys_half_clk, SSP);
214lpsc_clk(tdm0, tdm_0_clk, TDM0);
215lpsc_clk(tdm1, tdm_1_clk, TDM1);
216lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ);
217lpsc_clk(mcdma, sys_half_clk, MCDMA);
218lpsc_clk(usbss, sys_half_clk, USBSS);
219lpsc_clk(usb0, clk_usbss, USB0);
220lpsc_clk(usb1, clk_usbss, USB1);
221lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII);
222lpsc_clk(imcop, sys_dsp_clk, IMCOP);
223lpsc_clk(spare, sys_half_clk, SPARE);
224
225/* LCD needs a full power down to clear controller state */
226__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);
227
228
229/* Level 4 - leaf clocks for LPSC modules shared across drivers */
230static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };
231static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };
232
233static struct clk_lookup clks[] = {
234 CLK(NULL, "pll_sys_clk", &pll_sys_clk),
235 CLK(NULL, "pll_eth_clk", &pll_eth_clk),
236 CLK(NULL, "pll_tdm_clk", &pll_tdm_clk),
237 CLK(NULL, "sys_arm1176_clk", &sys_arm1176_clk),
238 CLK(NULL, "sys_dsp_clk", &sys_dsp_clk),
239 CLK(NULL, "sys_ddr_clk", &sys_ddr_clk),
240 CLK(NULL, "sys_full_clk", &sys_full_clk),
241 CLK(NULL, "sys_lcd_clk", &sys_lcd_clk),
242 CLK(NULL, "sys_vlynq_ref_clk", &sys_vlynq_ref_clk),
243 CLK(NULL, "sys_tsc_clk", &sys_tsc_clk),
244 CLK(NULL, "sys_half_clk", &sys_half_clk),
245 CLK(NULL, "eth_5mhz_clk", &eth_5mhz_clk),
246 CLK(NULL, "eth_50mhz_clk", &eth_50mhz_clk),
247 CLK(NULL, "eth_125mhz_clk", &eth_125mhz_clk),
248 CLK(NULL, "eth_250mhz_clk", &eth_250mhz_clk),
249 CLK(NULL, "eth_25mhz_clk", &eth_25mhz_clk),
250 CLK(NULL, "tdm_0_clk", &tdm_0_clk),
251 CLK(NULL, "tdm_extra_clk", &tdm_extra_clk),
252 CLK(NULL, "tdm_1_clk", &tdm_1_clk),
253 CLK(NULL, "clk_arm", &clk_arm),
254 CLK(NULL, "clk_gem", &clk_gem),
255 CLK(NULL, "clk_ddr2_phy", &clk_ddr2_phy),
256 CLK(NULL, "clk_tpcc", &clk_tpcc),
257 CLK(NULL, "clk_tptc0", &clk_tptc0),
258 CLK(NULL, "clk_tptc1", &clk_tptc1),
259 CLK(NULL, "clk_ram", &clk_ram),
260 CLK(NULL, "clk_mbx_lite", &clk_mbx_lite),
261 CLK("tnetv107x-fb.0", NULL, &clk_lcd),
262 CLK(NULL, "clk_ethss", &clk_ethss),
263 CLK(NULL, "aemif", &clk_aemif),
264 CLK(NULL, "clk_chipcfg", &clk_chipcfg),
265 CLK("tnetv107x-ts.0", NULL, &clk_tsc),
266 CLK(NULL, "clk_rom", &clk_rom),
267 CLK("serial8250.2", NULL, &clk_uart2),
268 CLK(NULL, "clk_pktsec", &clk_pktsec),
269 CLK("tnetv107x-rng.0", NULL, &clk_rng),
270 CLK("tnetv107x-pka.0", NULL, &clk_pka),
271 CLK(NULL, "clk_secctl", &clk_secctl),
272 CLK(NULL, "clk_keymgr", &clk_keymgr),
273 CLK("tnetv107x-keypad.0", NULL, &clk_keypad),
274 CLK(NULL, "clk_gpio", &clk_gpio),
275 CLK(NULL, "clk_mdio", &clk_mdio),
276 CLK("dm6441-mmc.0", NULL, &clk_sdio0),
277 CLK("serial8250.0", NULL, &clk_uart0),
278 CLK("serial8250.1", NULL, &clk_uart1),
279 CLK(NULL, "timer0", &clk_timer0),
280 CLK(NULL, "timer1", &clk_timer1),
281 CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm),
282 CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp),
283 CLK("ti-ssp", NULL, &clk_ssp),
284 CLK(NULL, "clk_tdm0", &clk_tdm0),
285 CLK(NULL, "clk_vlynq", &clk_vlynq),
286 CLK(NULL, "clk_mcdma", &clk_mcdma),
287 CLK(NULL, "clk_usbss", &clk_usbss),
288 CLK(NULL, "clk_usb0", &clk_usb0),
289 CLK(NULL, "clk_usb1", &clk_usb1),
290 CLK(NULL, "clk_tdm1", &clk_tdm1),
291 CLK(NULL, "clk_debugss", &clk_debugss),
292 CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii),
293 CLK(NULL, "clk_system", &clk_system),
294 CLK(NULL, "clk_imcop", &clk_imcop),
295 CLK(NULL, "clk_spare", &clk_spare),
296 CLK("dm6441-mmc.1", NULL, &clk_sdio1),
297 CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst),
298 CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst),
299 CLK(NULL, NULL, NULL),
300};
301
302static const struct mux_config pins[] = {
303#ifdef CONFIG_DAVINCI_MUX
304 MUX_CFG(TNETV107X, ASR_A00, 0, 0, 0x1f, 0x00, false)
305 MUX_CFG(TNETV107X, GPIO32, 0, 0, 0x1f, 0x04, false)
306 MUX_CFG(TNETV107X, ASR_A01, 0, 5, 0x1f, 0x00, false)
307 MUX_CFG(TNETV107X, GPIO33, 0, 5, 0x1f, 0x04, false)
308 MUX_CFG(TNETV107X, ASR_A02, 0, 10, 0x1f, 0x00, false)
309 MUX_CFG(TNETV107X, GPIO34, 0, 10, 0x1f, 0x04, false)
310 MUX_CFG(TNETV107X, ASR_A03, 0, 15, 0x1f, 0x00, false)
311 MUX_CFG(TNETV107X, GPIO35, 0, 15, 0x1f, 0x04, false)
312 MUX_CFG(TNETV107X, ASR_A04, 0, 20, 0x1f, 0x00, false)
313 MUX_CFG(TNETV107X, GPIO36, 0, 20, 0x1f, 0x04, false)
314 MUX_CFG(TNETV107X, ASR_A05, 0, 25, 0x1f, 0x00, false)
315 MUX_CFG(TNETV107X, GPIO37, 0, 25, 0x1f, 0x04, false)
316 MUX_CFG(TNETV107X, ASR_A06, 1, 0, 0x1f, 0x00, false)
317 MUX_CFG(TNETV107X, GPIO38, 1, 0, 0x1f, 0x04, false)
318 MUX_CFG(TNETV107X, ASR_A07, 1, 5, 0x1f, 0x00, false)
319 MUX_CFG(TNETV107X, GPIO39, 1, 5, 0x1f, 0x04, false)
320 MUX_CFG(TNETV107X, ASR_A08, 1, 10, 0x1f, 0x00, false)
321 MUX_CFG(TNETV107X, GPIO40, 1, 10, 0x1f, 0x04, false)
322 MUX_CFG(TNETV107X, ASR_A09, 1, 15, 0x1f, 0x00, false)
323 MUX_CFG(TNETV107X, GPIO41, 1, 15, 0x1f, 0x04, false)
324 MUX_CFG(TNETV107X, ASR_A10, 1, 20, 0x1f, 0x00, false)
325 MUX_CFG(TNETV107X, GPIO42, 1, 20, 0x1f, 0x04, false)
326 MUX_CFG(TNETV107X, ASR_A11, 1, 25, 0x1f, 0x00, false)
327 MUX_CFG(TNETV107X, BOOT_STRP_0, 1, 25, 0x1f, 0x04, false)
328 MUX_CFG(TNETV107X, ASR_A12, 2, 0, 0x1f, 0x00, false)
329 MUX_CFG(TNETV107X, BOOT_STRP_1, 2, 0, 0x1f, 0x04, false)
330 MUX_CFG(TNETV107X, ASR_A13, 2, 5, 0x1f, 0x00, false)
331 MUX_CFG(TNETV107X, GPIO43, 2, 5, 0x1f, 0x04, false)
332 MUX_CFG(TNETV107X, ASR_A14, 2, 10, 0x1f, 0x00, false)
333 MUX_CFG(TNETV107X, GPIO44, 2, 10, 0x1f, 0x04, false)
334 MUX_CFG(TNETV107X, ASR_A15, 2, 15, 0x1f, 0x00, false)
335 MUX_CFG(TNETV107X, GPIO45, 2, 15, 0x1f, 0x04, false)
336 MUX_CFG(TNETV107X, ASR_A16, 2, 20, 0x1f, 0x00, false)
337 MUX_CFG(TNETV107X, GPIO46, 2, 20, 0x1f, 0x04, false)
338 MUX_CFG(TNETV107X, ASR_A17, 2, 25, 0x1f, 0x00, false)
339 MUX_CFG(TNETV107X, GPIO47, 2, 25, 0x1f, 0x04, false)
340 MUX_CFG(TNETV107X, ASR_A18, 3, 0, 0x1f, 0x00, false)
341 MUX_CFG(TNETV107X, GPIO48, 3, 0, 0x1f, 0x04, false)
342 MUX_CFG(TNETV107X, SDIO1_DATA3_0, 3, 0, 0x1f, 0x1c, false)
343 MUX_CFG(TNETV107X, ASR_A19, 3, 5, 0x1f, 0x00, false)
344 MUX_CFG(TNETV107X, GPIO49, 3, 5, 0x1f, 0x04, false)
345 MUX_CFG(TNETV107X, SDIO1_DATA2_0, 3, 5, 0x1f, 0x1c, false)
346 MUX_CFG(TNETV107X, ASR_A20, 3, 10, 0x1f, 0x00, false)
347 MUX_CFG(TNETV107X, GPIO50, 3, 10, 0x1f, 0x04, false)
348 MUX_CFG(TNETV107X, SDIO1_DATA1_0, 3, 10, 0x1f, 0x1c, false)
349 MUX_CFG(TNETV107X, ASR_A21, 3, 15, 0x1f, 0x00, false)
350 MUX_CFG(TNETV107X, GPIO51, 3, 15, 0x1f, 0x04, false)
351 MUX_CFG(TNETV107X, SDIO1_DATA0_0, 3, 15, 0x1f, 0x1c, false)
352 MUX_CFG(TNETV107X, ASR_A22, 3, 20, 0x1f, 0x00, false)
353 MUX_CFG(TNETV107X, GPIO52, 3, 20, 0x1f, 0x04, false)
354 MUX_CFG(TNETV107X, SDIO1_CMD_0, 3, 20, 0x1f, 0x1c, false)
355 MUX_CFG(TNETV107X, ASR_A23, 3, 25, 0x1f, 0x00, false)
356 MUX_CFG(TNETV107X, GPIO53, 3, 25, 0x1f, 0x04, false)
357 MUX_CFG(TNETV107X, SDIO1_CLK_0, 3, 25, 0x1f, 0x1c, false)
358 MUX_CFG(TNETV107X, ASR_BA_1, 4, 0, 0x1f, 0x00, false)
359 MUX_CFG(TNETV107X, GPIO54, 4, 0, 0x1f, 0x04, false)
360 MUX_CFG(TNETV107X, SYS_PLL_CLK, 4, 0, 0x1f, 0x1c, false)
361 MUX_CFG(TNETV107X, ASR_CS0, 4, 5, 0x1f, 0x00, false)
362 MUX_CFG(TNETV107X, ASR_CS1, 4, 10, 0x1f, 0x00, false)
363 MUX_CFG(TNETV107X, ASR_CS2, 4, 15, 0x1f, 0x00, false)
364 MUX_CFG(TNETV107X, TDM_PLL_CLK, 4, 15, 0x1f, 0x1c, false)
365 MUX_CFG(TNETV107X, ASR_CS3, 4, 20, 0x1f, 0x00, false)
366 MUX_CFG(TNETV107X, ETH_PHY_CLK, 4, 20, 0x1f, 0x0c, false)
367 MUX_CFG(TNETV107X, ASR_D00, 4, 25, 0x1f, 0x00, false)
368 MUX_CFG(TNETV107X, GPIO55, 4, 25, 0x1f, 0x1c, false)
369 MUX_CFG(TNETV107X, ASR_D01, 5, 0, 0x1f, 0x00, false)
370 MUX_CFG(TNETV107X, GPIO56, 5, 0, 0x1f, 0x1c, false)
371 MUX_CFG(TNETV107X, ASR_D02, 5, 5, 0x1f, 0x00, false)
372 MUX_CFG(TNETV107X, GPIO57, 5, 5, 0x1f, 0x1c, false)
373 MUX_CFG(TNETV107X, ASR_D03, 5, 10, 0x1f, 0x00, false)
374 MUX_CFG(TNETV107X, GPIO58, 5, 10, 0x1f, 0x1c, false)
375 MUX_CFG(TNETV107X, ASR_D04, 5, 15, 0x1f, 0x00, false)
376 MUX_CFG(TNETV107X, GPIO59_0, 5, 15, 0x1f, 0x1c, false)
377 MUX_CFG(TNETV107X, ASR_D05, 5, 20, 0x1f, 0x00, false)
378 MUX_CFG(TNETV107X, GPIO60_0, 5, 20, 0x1f, 0x1c, false)
379 MUX_CFG(TNETV107X, ASR_D06, 5, 25, 0x1f, 0x00, false)
380 MUX_CFG(TNETV107X, GPIO61_0, 5, 25, 0x1f, 0x1c, false)
381 MUX_CFG(TNETV107X, ASR_D07, 6, 0, 0x1f, 0x00, false)
382 MUX_CFG(TNETV107X, GPIO62_0, 6, 0, 0x1f, 0x1c, false)
383 MUX_CFG(TNETV107X, ASR_D08, 6, 5, 0x1f, 0x00, false)
384 MUX_CFG(TNETV107X, GPIO63_0, 6, 5, 0x1f, 0x1c, false)
385 MUX_CFG(TNETV107X, ASR_D09, 6, 10, 0x1f, 0x00, false)
386 MUX_CFG(TNETV107X, GPIO64_0, 6, 10, 0x1f, 0x1c, false)
387 MUX_CFG(TNETV107X, ASR_D10, 6, 15, 0x1f, 0x00, false)
388 MUX_CFG(TNETV107X, SDIO1_DATA3_1, 6, 15, 0x1f, 0x1c, false)
389 MUX_CFG(TNETV107X, ASR_D11, 6, 20, 0x1f, 0x00, false)
390 MUX_CFG(TNETV107X, SDIO1_DATA2_1, 6, 20, 0x1f, 0x1c, false)
391 MUX_CFG(TNETV107X, ASR_D12, 6, 25, 0x1f, 0x00, false)
392 MUX_CFG(TNETV107X, SDIO1_DATA1_1, 6, 25, 0x1f, 0x1c, false)
393 MUX_CFG(TNETV107X, ASR_D13, 7, 0, 0x1f, 0x00, false)
394 MUX_CFG(TNETV107X, SDIO1_DATA0_1, 7, 0, 0x1f, 0x1c, false)
395 MUX_CFG(TNETV107X, ASR_D14, 7, 5, 0x1f, 0x00, false)
396 MUX_CFG(TNETV107X, SDIO1_CMD_1, 7, 5, 0x1f, 0x1c, false)
397 MUX_CFG(TNETV107X, ASR_D15, 7, 10, 0x1f, 0x00, false)
398 MUX_CFG(TNETV107X, SDIO1_CLK_1, 7, 10, 0x1f, 0x1c, false)
399 MUX_CFG(TNETV107X, ASR_OE, 7, 15, 0x1f, 0x00, false)
400 MUX_CFG(TNETV107X, BOOT_STRP_2, 7, 15, 0x1f, 0x04, false)
401 MUX_CFG(TNETV107X, ASR_RNW, 7, 20, 0x1f, 0x00, false)
402 MUX_CFG(TNETV107X, GPIO29_0, 7, 20, 0x1f, 0x04, false)
403 MUX_CFG(TNETV107X, ASR_WAIT, 7, 25, 0x1f, 0x00, false)
404 MUX_CFG(TNETV107X, GPIO30_0, 7, 25, 0x1f, 0x04, false)
405 MUX_CFG(TNETV107X, ASR_WE, 8, 0, 0x1f, 0x00, false)
406 MUX_CFG(TNETV107X, BOOT_STRP_3, 8, 0, 0x1f, 0x04, false)
407 MUX_CFG(TNETV107X, ASR_WE_DQM0, 8, 5, 0x1f, 0x00, false)
408 MUX_CFG(TNETV107X, GPIO31, 8, 5, 0x1f, 0x04, false)
409 MUX_CFG(TNETV107X, LCD_PD17_0, 8, 5, 0x1f, 0x1c, false)
410 MUX_CFG(TNETV107X, ASR_WE_DQM1, 8, 10, 0x1f, 0x00, false)
411 MUX_CFG(TNETV107X, ASR_BA0_0, 8, 10, 0x1f, 0x04, false)
412 MUX_CFG(TNETV107X, VLYNQ_CLK, 9, 0, 0x1f, 0x00, false)
413 MUX_CFG(TNETV107X, GPIO14, 9, 0, 0x1f, 0x04, false)
414 MUX_CFG(TNETV107X, LCD_PD19_0, 9, 0, 0x1f, 0x1c, false)
415 MUX_CFG(TNETV107X, VLYNQ_RXD0, 9, 5, 0x1f, 0x00, false)
416 MUX_CFG(TNETV107X, GPIO15, 9, 5, 0x1f, 0x04, false)
417 MUX_CFG(TNETV107X, LCD_PD20_0, 9, 5, 0x1f, 0x1c, false)
418 MUX_CFG(TNETV107X, VLYNQ_RXD1, 9, 10, 0x1f, 0x00, false)
419 MUX_CFG(TNETV107X, GPIO16, 9, 10, 0x1f, 0x04, false)
420 MUX_CFG(TNETV107X, LCD_PD21_0, 9, 10, 0x1f, 0x1c, false)
421 MUX_CFG(TNETV107X, VLYNQ_TXD0, 9, 15, 0x1f, 0x00, false)
422 MUX_CFG(TNETV107X, GPIO17, 9, 15, 0x1f, 0x04, false)
423 MUX_CFG(TNETV107X, LCD_PD22_0, 9, 15, 0x1f, 0x1c, false)
424 MUX_CFG(TNETV107X, VLYNQ_TXD1, 9, 20, 0x1f, 0x00, false)
425 MUX_CFG(TNETV107X, GPIO18, 9, 20, 0x1f, 0x04, false)
426 MUX_CFG(TNETV107X, LCD_PD23_0, 9, 20, 0x1f, 0x1c, false)
427 MUX_CFG(TNETV107X, SDIO0_CLK, 10, 0, 0x1f, 0x00, false)
428 MUX_CFG(TNETV107X, GPIO19, 10, 0, 0x1f, 0x04, false)
429 MUX_CFG(TNETV107X, SDIO0_CMD, 10, 5, 0x1f, 0x00, false)
430 MUX_CFG(TNETV107X, GPIO20, 10, 5, 0x1f, 0x04, false)
431 MUX_CFG(TNETV107X, SDIO0_DATA0, 10, 10, 0x1f, 0x00, false)
432 MUX_CFG(TNETV107X, GPIO21, 10, 10, 0x1f, 0x04, false)
433 MUX_CFG(TNETV107X, SDIO0_DATA1, 10, 15, 0x1f, 0x00, false)
434 MUX_CFG(TNETV107X, GPIO22, 10, 15, 0x1f, 0x04, false)
435 MUX_CFG(TNETV107X, SDIO0_DATA2, 10, 20, 0x1f, 0x00, false)
436 MUX_CFG(TNETV107X, GPIO23, 10, 20, 0x1f, 0x04, false)
437 MUX_CFG(TNETV107X, SDIO0_DATA3, 10, 25, 0x1f, 0x00, false)
438 MUX_CFG(TNETV107X, GPIO24, 10, 25, 0x1f, 0x04, false)
439 MUX_CFG(TNETV107X, EMU0, 11, 0, 0x1f, 0x00, false)
440 MUX_CFG(TNETV107X, EMU1, 11, 5, 0x1f, 0x00, false)
441 MUX_CFG(TNETV107X, RTCK, 12, 0, 0x1f, 0x00, false)
442 MUX_CFG(TNETV107X, TRST_N, 12, 5, 0x1f, 0x00, false)
443 MUX_CFG(TNETV107X, TCK, 12, 10, 0x1f, 0x00, false)
444 MUX_CFG(TNETV107X, TDI, 12, 15, 0x1f, 0x00, false)
445 MUX_CFG(TNETV107X, TDO, 12, 20, 0x1f, 0x00, false)
446 MUX_CFG(TNETV107X, TMS, 12, 25, 0x1f, 0x00, false)
447 MUX_CFG(TNETV107X, TDM1_CLK, 13, 0, 0x1f, 0x00, false)
448 MUX_CFG(TNETV107X, TDM1_RX, 13, 5, 0x1f, 0x00, false)
449 MUX_CFG(TNETV107X, TDM1_TX, 13, 10, 0x1f, 0x00, false)
450 MUX_CFG(TNETV107X, TDM1_FS, 13, 15, 0x1f, 0x00, false)
451 MUX_CFG(TNETV107X, KEYPAD_R0, 14, 0, 0x1f, 0x00, false)
452 MUX_CFG(TNETV107X, KEYPAD_R1, 14, 5, 0x1f, 0x00, false)
453 MUX_CFG(TNETV107X, KEYPAD_R2, 14, 10, 0x1f, 0x00, false)
454 MUX_CFG(TNETV107X, KEYPAD_R3, 14, 15, 0x1f, 0x00, false)
455 MUX_CFG(TNETV107X, KEYPAD_R4, 14, 20, 0x1f, 0x00, false)
456 MUX_CFG(TNETV107X, KEYPAD_R5, 14, 25, 0x1f, 0x00, false)
457 MUX_CFG(TNETV107X, KEYPAD_R6, 15, 0, 0x1f, 0x00, false)
458 MUX_CFG(TNETV107X, GPIO12, 15, 0, 0x1f, 0x04, false)
459 MUX_CFG(TNETV107X, KEYPAD_R7, 15, 5, 0x1f, 0x00, false)
460 MUX_CFG(TNETV107X, GPIO10, 15, 5, 0x1f, 0x04, false)
461 MUX_CFG(TNETV107X, KEYPAD_C0, 15, 10, 0x1f, 0x00, false)
462 MUX_CFG(TNETV107X, KEYPAD_C1, 15, 15, 0x1f, 0x00, false)
463 MUX_CFG(TNETV107X, KEYPAD_C2, 15, 20, 0x1f, 0x00, false)
464 MUX_CFG(TNETV107X, KEYPAD_C3, 15, 25, 0x1f, 0x00, false)
465 MUX_CFG(TNETV107X, KEYPAD_C4, 16, 0, 0x1f, 0x00, false)
466 MUX_CFG(TNETV107X, KEYPAD_C5, 16, 5, 0x1f, 0x00, false)
467 MUX_CFG(TNETV107X, KEYPAD_C6, 16, 10, 0x1f, 0x00, false)
468 MUX_CFG(TNETV107X, GPIO13, 16, 10, 0x1f, 0x04, false)
469 MUX_CFG(TNETV107X, TEST_CLK_IN, 16, 10, 0x1f, 0x0c, false)
470 MUX_CFG(TNETV107X, KEYPAD_C7, 16, 15, 0x1f, 0x00, false)
471 MUX_CFG(TNETV107X, GPIO11, 16, 15, 0x1f, 0x04, false)
472 MUX_CFG(TNETV107X, SSP0_0, 17, 0, 0x1f, 0x00, false)
473 MUX_CFG(TNETV107X, SCC_DCLK, 17, 0, 0x1f, 0x04, false)
474 MUX_CFG(TNETV107X, LCD_PD20_1, 17, 0, 0x1f, 0x0c, false)
475 MUX_CFG(TNETV107X, SSP0_1, 17, 5, 0x1f, 0x00, false)
476 MUX_CFG(TNETV107X, SCC_CS_N, 17, 5, 0x1f, 0x04, false)
477 MUX_CFG(TNETV107X, LCD_PD21_1, 17, 5, 0x1f, 0x0c, false)
478 MUX_CFG(TNETV107X, SSP0_2, 17, 10, 0x1f, 0x00, false)
479 MUX_CFG(TNETV107X, SCC_D, 17, 10, 0x1f, 0x04, false)
480 MUX_CFG(TNETV107X, LCD_PD22_1, 17, 10, 0x1f, 0x0c, false)
481 MUX_CFG(TNETV107X, SSP0_3, 17, 15, 0x1f, 0x00, false)
482 MUX_CFG(TNETV107X, SCC_RESETN, 17, 15, 0x1f, 0x04, false)
483 MUX_CFG(TNETV107X, LCD_PD23_1, 17, 15, 0x1f, 0x0c, false)
484 MUX_CFG(TNETV107X, SSP1_0, 18, 0, 0x1f, 0x00, false)
485 MUX_CFG(TNETV107X, GPIO25, 18, 0, 0x1f, 0x04, false)
486 MUX_CFG(TNETV107X, UART2_CTS, 18, 0, 0x1f, 0x0c, false)
487 MUX_CFG(TNETV107X, SSP1_1, 18, 5, 0x1f, 0x00, false)
488 MUX_CFG(TNETV107X, GPIO26, 18, 5, 0x1f, 0x04, false)
489 MUX_CFG(TNETV107X, UART2_RD, 18, 5, 0x1f, 0x0c, false)
490 MUX_CFG(TNETV107X, SSP1_2, 18, 10, 0x1f, 0x00, false)
491 MUX_CFG(TNETV107X, GPIO27, 18, 10, 0x1f, 0x04, false)
492 MUX_CFG(TNETV107X, UART2_RTS, 18, 10, 0x1f, 0x0c, false)
493 MUX_CFG(TNETV107X, SSP1_3, 18, 15, 0x1f, 0x00, false)
494 MUX_CFG(TNETV107X, GPIO28, 18, 15, 0x1f, 0x04, false)
495 MUX_CFG(TNETV107X, UART2_TD, 18, 15, 0x1f, 0x0c, false)
496 MUX_CFG(TNETV107X, UART0_CTS, 19, 0, 0x1f, 0x00, false)
497 MUX_CFG(TNETV107X, UART0_RD, 19, 5, 0x1f, 0x00, false)
498 MUX_CFG(TNETV107X, UART0_RTS, 19, 10, 0x1f, 0x00, false)
499 MUX_CFG(TNETV107X, UART0_TD, 19, 15, 0x1f, 0x00, false)
500 MUX_CFG(TNETV107X, UART1_RD, 19, 20, 0x1f, 0x00, false)
501 MUX_CFG(TNETV107X, UART1_TD, 19, 25, 0x1f, 0x00, false)
502 MUX_CFG(TNETV107X, LCD_AC_NCS, 20, 0, 0x1f, 0x00, false)
503 MUX_CFG(TNETV107X, LCD_HSYNC_RNW, 20, 5, 0x1f, 0x00, false)
504 MUX_CFG(TNETV107X, LCD_VSYNC_A0, 20, 10, 0x1f, 0x00, false)
505 MUX_CFG(TNETV107X, LCD_MCLK, 20, 15, 0x1f, 0x00, false)
506 MUX_CFG(TNETV107X, LCD_PD16_0, 20, 15, 0x1f, 0x0c, false)
507 MUX_CFG(TNETV107X, LCD_PCLK_E, 20, 20, 0x1f, 0x00, false)
508 MUX_CFG(TNETV107X, LCD_PD00, 20, 25, 0x1f, 0x00, false)
509 MUX_CFG(TNETV107X, LCD_PD01, 21, 0, 0x1f, 0x00, false)
510 MUX_CFG(TNETV107X, LCD_PD02, 21, 5, 0x1f, 0x00, false)
511 MUX_CFG(TNETV107X, LCD_PD03, 21, 10, 0x1f, 0x00, false)
512 MUX_CFG(TNETV107X, LCD_PD04, 21, 15, 0x1f, 0x00, false)
513 MUX_CFG(TNETV107X, LCD_PD05, 21, 20, 0x1f, 0x00, false)
514 MUX_CFG(TNETV107X, LCD_PD06, 21, 25, 0x1f, 0x00, false)
515 MUX_CFG(TNETV107X, LCD_PD07, 22, 0, 0x1f, 0x00, false)
516 MUX_CFG(TNETV107X, LCD_PD08, 22, 5, 0x1f, 0x00, false)
517 MUX_CFG(TNETV107X, GPIO59_1, 22, 5, 0x1f, 0x0c, false)
518 MUX_CFG(TNETV107X, LCD_PD09, 22, 10, 0x1f, 0x00, false)
519 MUX_CFG(TNETV107X, GPIO60_1, 22, 10, 0x1f, 0x0c, false)
520 MUX_CFG(TNETV107X, LCD_PD10, 22, 15, 0x1f, 0x00, false)
521 MUX_CFG(TNETV107X, ASR_BA0_1, 22, 15, 0x1f, 0x04, false)
522 MUX_CFG(TNETV107X, GPIO61_1, 22, 15, 0x1f, 0x0c, false)
523 MUX_CFG(TNETV107X, LCD_PD11, 22, 20, 0x1f, 0x00, false)
524 MUX_CFG(TNETV107X, GPIO62_1, 22, 20, 0x1f, 0x0c, false)
525 MUX_CFG(TNETV107X, LCD_PD12, 22, 25, 0x1f, 0x00, false)
526 MUX_CFG(TNETV107X, GPIO63_1, 22, 25, 0x1f, 0x0c, false)
527 MUX_CFG(TNETV107X, LCD_PD13, 23, 0, 0x1f, 0x00, false)
528 MUX_CFG(TNETV107X, GPIO64_1, 23, 0, 0x1f, 0x0c, false)
529 MUX_CFG(TNETV107X, LCD_PD14, 23, 5, 0x1f, 0x00, false)
530 MUX_CFG(TNETV107X, GPIO29_1, 23, 5, 0x1f, 0x0c, false)
531 MUX_CFG(TNETV107X, LCD_PD15, 23, 10, 0x1f, 0x00, false)
532 MUX_CFG(TNETV107X, GPIO30_1, 23, 10, 0x1f, 0x0c, false)
533 MUX_CFG(TNETV107X, EINT0, 24, 0, 0x1f, 0x00, false)
534 MUX_CFG(TNETV107X, GPIO08, 24, 0, 0x1f, 0x04, false)
535 MUX_CFG(TNETV107X, EINT1, 24, 5, 0x1f, 0x00, false)
536 MUX_CFG(TNETV107X, GPIO09, 24, 5, 0x1f, 0x04, false)
537 MUX_CFG(TNETV107X, GPIO00, 24, 10, 0x1f, 0x00, false)
538 MUX_CFG(TNETV107X, LCD_PD20_2, 24, 10, 0x1f, 0x04, false)
539 MUX_CFG(TNETV107X, TDM_CLK_IN_2, 24, 10, 0x1f, 0x0c, false)
540 MUX_CFG(TNETV107X, GPIO01, 24, 15, 0x1f, 0x00, false)
541 MUX_CFG(TNETV107X, LCD_PD21_2, 24, 15, 0x1f, 0x04, false)
542 MUX_CFG(TNETV107X, 24M_CLK_OUT_1, 24, 15, 0x1f, 0x0c, false)
543 MUX_CFG(TNETV107X, GPIO02, 24, 20, 0x1f, 0x00, false)
544 MUX_CFG(TNETV107X, LCD_PD22_2, 24, 20, 0x1f, 0x04, false)
545 MUX_CFG(TNETV107X, GPIO03, 24, 25, 0x1f, 0x00, false)
546 MUX_CFG(TNETV107X, LCD_PD23_2, 24, 25, 0x1f, 0x04, false)
547 MUX_CFG(TNETV107X, GPIO04, 25, 0, 0x1f, 0x00, false)
548 MUX_CFG(TNETV107X, LCD_PD16_1, 25, 0, 0x1f, 0x04, false)
549 MUX_CFG(TNETV107X, USB0_RXERR, 25, 0, 0x1f, 0x0c, false)
550 MUX_CFG(TNETV107X, GPIO05, 25, 5, 0x1f, 0x00, false)
551 MUX_CFG(TNETV107X, LCD_PD17_1, 25, 5, 0x1f, 0x04, false)
552 MUX_CFG(TNETV107X, TDM_CLK_IN_1, 25, 5, 0x1f, 0x0c, false)
553 MUX_CFG(TNETV107X, GPIO06, 25, 10, 0x1f, 0x00, false)
554 MUX_CFG(TNETV107X, LCD_PD18, 25, 10, 0x1f, 0x04, false)
555 MUX_CFG(TNETV107X, 24M_CLK_OUT_2, 25, 10, 0x1f, 0x0c, false)
556 MUX_CFG(TNETV107X, GPIO07, 25, 15, 0x1f, 0x00, false)
557 MUX_CFG(TNETV107X, LCD_PD19_1, 25, 15, 0x1f, 0x04, false)
558 MUX_CFG(TNETV107X, USB1_RXERR, 25, 15, 0x1f, 0x0c, false)
559 MUX_CFG(TNETV107X, ETH_PLL_CLK, 25, 15, 0x1f, 0x1c, false)
560 MUX_CFG(TNETV107X, MDIO, 26, 0, 0x1f, 0x00, false)
561 MUX_CFG(TNETV107X, MDC, 26, 5, 0x1f, 0x00, false)
562 MUX_CFG(TNETV107X, AIC_MUTE_STAT_N, 26, 10, 0x1f, 0x00, false)
563 MUX_CFG(TNETV107X, TDM0_CLK, 26, 10, 0x1f, 0x04, false)
564 MUX_CFG(TNETV107X, AIC_HNS_EN_N, 26, 15, 0x1f, 0x00, false)
565 MUX_CFG(TNETV107X, TDM0_FS, 26, 15, 0x1f, 0x04, false)
566 MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N, 26, 20, 0x1f, 0x00, false)
567 MUX_CFG(TNETV107X, TDM0_TX, 26, 20, 0x1f, 0x04, false)
568 MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N, 26, 25, 0x1f, 0x00, false)
569 MUX_CFG(TNETV107X, TDM0_RX, 26, 25, 0x1f, 0x04, false)
570#endif
571};
572
573/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
574static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
575 /* fill in default priority 7 */
576 [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)] = 7,
577 /* now override as needed, e.g. [xxx] = 5 */
578};
579
580/* Contents of JTAG ID register used to identify exact cpu type */
581static struct davinci_id ids[] = {
582 {
583 .variant = 0x0,
584 .part_no = 0xb8a1,
585 .manufacturer = 0x017,
586 .cpu_id = DAVINCI_CPU_ID_TNETV107X,
587 .name = "tnetv107x rev 1.0",
588 },
589 {
590 .variant = 0x1,
591 .part_no = 0xb8a1,
592 .manufacturer = 0x017,
593 .cpu_id = DAVINCI_CPU_ID_TNETV107X,
594 .name = "tnetv107x rev 1.1/1.2",
595 },
596};
597
598static struct davinci_timer_instance timer_instance[2] = {
599 {
600 .base = TNETV107X_TIMER0_BASE,
601 .bottom_irq = IRQ_TNETV107X_TIMER_0_TINT12,
602 .top_irq = IRQ_TNETV107X_TIMER_0_TINT34,
603 },
604 {
605 .base = TNETV107X_TIMER1_BASE,
606 .bottom_irq = IRQ_TNETV107X_TIMER_1_TINT12,
607 .top_irq = IRQ_TNETV107X_TIMER_1_TINT34,
608 },
609};
610
611static struct davinci_timer_info timer_info = {
612 .timers = timer_instance,
613 .clockevent_id = T0_BOT,
614 .clocksource_id = T0_TOP,
615};
616
617/*
618 * TNETV107X platforms do not use the static mappings from Davinci
619 * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
620 * and changing IO_PHYS would break away from existing Davinci SOCs.
621 *
622 * The primary impact of the current model is that IO_ADDRESS() is not to be
623 * used to map registers on TNETV107X.
624 *
625 * 1. The first chunk is for INTC: This needs to be mapped in via iotable
626 * because ioremap() does not seem to be operational at the time when
627 * irqs are initialized. Without this, consistent dma init bombs.
628 *
629 * 2. The second chunk maps in register areas that need to be populated into
630 * davinci_soc_info. Note that alignment restrictions come into play if
631 * low-level debug is enabled (see note in <mach/tnetv107x.h>).
632 */
633static struct map_desc io_desc[] = {
634 { /* INTC */
635 .virtual = IO_VIRT,
636 .pfn = __phys_to_pfn(TNETV107X_INTC_BASE),
637 .length = SZ_16K,
638 .type = MT_DEVICE
639 },
640 { /* Most of the rest */
641 .virtual = TNETV107X_IO_VIRT,
642 .pfn = __phys_to_pfn(TNETV107X_IO_BASE),
643 .length = IO_SIZE - SZ_1M,
644 .type = MT_DEVICE
645 },
646};
647
648static unsigned long clk_sspll_recalc(struct clk *clk)
649{
650 int pll;
651 unsigned long mult = 0, prediv = 1, postdiv = 1;
652 unsigned long ref = OSC_FREQ_ONCHIP, ret;
653 u32 tmp;
654
655 if (WARN_ON(!clk->pll_data))
656 return clk->rate;
657
658 if (!clk_ctrl_regs) {
659 void __iomem *tmp;
660
661 tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
662
663 if (WARN(!tmp, "failed ioremap for clock control regs\n"))
664 return clk->parent ? clk->parent->rate : 0;
665
666 for (pll = 0; pll < N_PLLS; pll++)
667 sspll_regs[pll] = tmp + sspll_regs_base[pll];
668
669 clk_ctrl_regs = tmp;
670 }
671
672 pll = clk->pll_data->num;
673
674 tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
675 if (!(tmp & bypass_mask[pll])) {
676 mult = __raw_readl(&sspll_regs[pll]->mult_factor);
677 prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1;
678 postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1;
679 }
680
681 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
682 if (tmp & PLLCTL_CLKMODE)
683 ref = pll_ext_freq[pll];
684
685 clk->pll_data->input_rate = ref;
686
687 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
688 if (!(tmp & PLLCTL_PLLEN))
689 return ref;
690
691 ret = ref;
692 if (mult)
693 ret += ((unsigned long long)ref * mult) / 256;
694
695 ret /= (prediv * postdiv);
696
697 return ret;
698}
699
700static void tnetv107x_watchdog_reset(struct platform_device *pdev)
701{
702 struct wdt_regs __iomem *regs;
703
704 regs = ioremap(pdev->resource[0].start, SZ_4K);
705
706 /* disable watchdog */
707 __raw_writel(0x7777, &regs->disable_lock);
708 __raw_writel(0xcccc, &regs->disable_lock);
709 __raw_writel(0xdddd, &regs->disable_lock);
710 __raw_writel(0, &regs->disable);
711
712 /* program prescale */
713 __raw_writel(0x5a5a, &regs->prescale_lock);
714 __raw_writel(0xa5a5, &regs->prescale_lock);
715 __raw_writel(0, &regs->prescale);
716
717 /* program countdown */
718 __raw_writel(0x6666, &regs->change_lock);
719 __raw_writel(0xbbbb, &regs->change_lock);
720 __raw_writel(1, &regs->change);
721
722 /* enable watchdog */
723 __raw_writel(0x7777, &regs->disable_lock);
724 __raw_writel(0xcccc, &regs->disable_lock);
725 __raw_writel(0xdddd, &regs->disable_lock);
726 __raw_writel(1, &regs->disable);
727
728 /* kick */
729 __raw_writel(0x5555, &regs->kick_lock);
730 __raw_writel(0xaaaa, &regs->kick_lock);
731 __raw_writel(1, &regs->kick);
732}
733
734void tnetv107x_restart(enum reboot_mode mode, const char *cmd)
735{
736 tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
737}
738
739static struct davinci_soc_info tnetv107x_soc_info = {
740 .io_desc = io_desc,
741 .io_desc_num = ARRAY_SIZE(io_desc),
742 .ids = ids,
743 .ids_num = ARRAY_SIZE(ids),
744 .jtag_id_reg = TNETV107X_CHIP_CFG_BASE + 0x018,
745 .cpu_clks = clks,
746 .psc_bases = psc_regs,
747 .psc_bases_num = ARRAY_SIZE(psc_regs),
748 .pinmux_base = TNETV107X_CHIP_CFG_BASE + 0x150,
749 .pinmux_pins = pins,
750 .pinmux_pins_num = ARRAY_SIZE(pins),
751 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
752 .intc_base = TNETV107X_INTC_BASE,
753 .intc_irq_prios = irq_prios,
754 .intc_irq_num = TNETV107X_N_CP_INTC_IRQ,
755 .intc_host_map = intc_host_map,
756 .gpio_base = TNETV107X_GPIO_BASE,
757 .gpio_type = GPIO_TYPE_TNETV107X,
758 .gpio_num = TNETV107X_N_GPIO,
759 .timer_info = &timer_info,
760 .serial_dev = tnetv107x_serial_device,
761};
762
763void __init tnetv107x_init(void)
764{
765 davinci_common_init(&tnetv107x_soc_info);
766}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 11:08:15 -0500