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-rw-r--r--arch/arm/mach-davinci/Kconfig63
-rw-r--r--arch/arm/mach-davinci/Makefile8
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c466
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c493
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c19
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c13
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c151
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c18
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c203
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c323
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c20
-rw-r--r--arch/arm/mach-davinci/cdce949.c293
-rw-r--r--arch/arm/mach-davinci/clock.c298
-rw-r--r--arch/arm/mach-davinci/clock.h62
-rw-r--r--arch/arm/mach-davinci/common.c6
-rw-r--r--arch/arm/mach-davinci/cp_intc.c14
-rw-r--r--arch/arm/mach-davinci/cpufreq.c226
-rw-r--r--arch/arm/mach-davinci/cpuidle.c169
-rw-r--r--arch/arm/mach-davinci/da830.c79
-rw-r--r--arch/arm/mach-davinci/da850.c358
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c255
-rw-r--r--arch/arm/mach-davinci/devices.c6
-rw-r--r--arch/arm/mach-davinci/dm355.c94
-rw-r--r--arch/arm/mach-davinci/dm365.c320
-rw-r--r--arch/arm/mach-davinci/dm644x.c40
-rw-r--r--arch/arm/mach-davinci/dm646x.c25
-rw-r--r--arch/arm/mach-davinci/dma.c176
-rw-r--r--arch/arm/mach-davinci/gpio.c9
-rw-r--r--arch/arm/mach-davinci/include/mach/asp.h11
-rw-r--r--arch/arm/mach-davinci/include/mach/cdce949.h19
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/cpufreq.h26
-rw-r--r--arch/arm/mach-davinci/include/mach/cpuidle.h18
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h46
-rw-r--r--arch/arm/mach-davinci/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365.h21
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/emac.h36
-rw-r--r--arch/arm/mach-davinci/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/i2c.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/keyscan.h42
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h5
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h23
-rw-r--r--arch/arm/mach-davinci/include/mach/nand.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/pm.h54
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h15
-rw-r--r--arch/arm/mach-davinci/include/mach/spi.h44
-rw-r--r--arch/arm/mach-davinci/include/mach/system.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/timex.h7
-rw-r--r--arch/arm/mach-davinci/include/mach/usb.h59
-rw-r--r--arch/arm/mach-davinci/io.c2
-rw-r--r--arch/arm/mach-davinci/mux.c1
-rw-r--r--arch/arm/mach-davinci/pm.c158
-rw-r--r--arch/arm/mach-davinci/psc.c14
-rw-r--r--arch/arm/mach-davinci/serial.c6
-rw-r--r--arch/arm/mach-davinci/sleep.S224
-rw-r--r--arch/arm/mach-davinci/sram.c3
-rw-r--r--arch/arm/mach-davinci/time.c12
-rw-r--r--arch/arm/mach-davinci/usb.c84
62 files changed, 4520 insertions, 650 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 40866c643f13..0ebe185610bf 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -32,11 +32,13 @@ config ARCH_DAVINCI_DA830
32 bool "DA830/OMAP-L137 based system" 32 bool "DA830/OMAP-L137 based system"
33 select CP_INTC 33 select CP_INTC
34 select ARCH_DAVINCI_DA8XX 34 select ARCH_DAVINCI_DA8XX
35 select CPU_DCACHE_WRITETHROUGH # needed on silicon revs 1.0, 1.1
35 36
36config ARCH_DAVINCI_DA850 37config ARCH_DAVINCI_DA850
37 bool "DA850/OMAP-L138 based system" 38 bool "DA850/OMAP-L138 based system"
38 select CP_INTC 39 select CP_INTC
39 select ARCH_DAVINCI_DA8XX 40 select ARCH_DAVINCI_DA8XX
41 select ARCH_HAS_CPUFREQ
40 42
41config ARCH_DAVINCI_DA8XX 43config ARCH_DAVINCI_DA8XX
42 bool 44 bool
@@ -63,6 +65,13 @@ config MACH_SFFSDR
63 Say Y here to select the Lyrtech Small Form Factor 65 Say Y here to select the Lyrtech Small Form Factor
64 Software Defined Radio (SFFSDR) board. 66 Software Defined Radio (SFFSDR) board.
65 67
68config MACH_NEUROS_OSD2
69 bool "Neuros OSD2 Open Television Set Top Box"
70 depends on ARCH_DAVINCI_DM644x
71 help
72 Configure this option to specify the whether the board used
73 for development is a Neuros OSD2 Open Set Top Box.
74
66config MACH_DAVINCI_DM355_EVM 75config MACH_DAVINCI_DM355_EVM
67 bool "TI DM355 EVM" 76 bool "TI DM355 EVM"
68 default ARCH_DAVINCI_DM355 77 default ARCH_DAVINCI_DM355
@@ -82,10 +91,14 @@ config MACH_DAVINCI_DM6467_EVM
82 bool "TI DM6467 EVM" 91 bool "TI DM6467 EVM"
83 default ARCH_DAVINCI_DM646x 92 default ARCH_DAVINCI_DM646x
84 depends on ARCH_DAVINCI_DM646x 93 depends on ARCH_DAVINCI_DM646x
94 select MACH_DAVINCI_DM6467TEVM
85 help 95 help
86 Configure this option to specify the whether the board used 96 Configure this option to specify the whether the board used
87 for development is a DM6467 EVM 97 for development is a DM6467 EVM
88 98
99config MACH_DAVINCI_DM6467TEVM
100 bool
101
89config MACH_DAVINCI_DM365_EVM 102config MACH_DAVINCI_DM365_EVM
90 bool "TI DM365 EVM" 103 bool "TI DM365 EVM"
91 default ARCH_DAVINCI_DM365 104 default ARCH_DAVINCI_DM365
@@ -98,16 +111,66 @@ config MACH_DAVINCI_DA830_EVM
98 bool "TI DA830/OMAP-L137 Reference Platform" 111 bool "TI DA830/OMAP-L137 Reference Platform"
99 default ARCH_DAVINCI_DA830 112 default ARCH_DAVINCI_DA830
100 depends on ARCH_DAVINCI_DA830 113 depends on ARCH_DAVINCI_DA830
114 select GPIO_PCF857X
101 help 115 help
102 Say Y here to select the TI DA830/OMAP-L137 Evaluation Module. 116 Say Y here to select the TI DA830/OMAP-L137 Evaluation Module.
103 117
118choice
119 prompt "Select DA830/OMAP-L137 UI board peripheral"
120 depends on MACH_DAVINCI_DA830_EVM
121 help
122 The presence of UI card on the DA830/OMAP-L137 EVM is detected
123 automatically based on successful probe of the I2C based GPIO
124 expander on that board. This option selected in this menu has
125 an effect only in case of a successful UI card detection.
126
127config DA830_UI_LCD
128 bool "LCD"
129 help
130 Say Y here to use the LCD as a framebuffer or simple character
131 display.
132
133config DA830_UI_NAND
134 bool "NAND flash"
135 help
136 Say Y here to use the NAND flash. Do not forget to setup
137 the switch correctly.
138endchoice
139
104config MACH_DAVINCI_DA850_EVM 140config MACH_DAVINCI_DA850_EVM
105 bool "TI DA850/OMAP-L138 Reference Platform" 141 bool "TI DA850/OMAP-L138 Reference Platform"
106 default ARCH_DAVINCI_DA850 142 default ARCH_DAVINCI_DA850
107 depends on ARCH_DAVINCI_DA850 143 depends on ARCH_DAVINCI_DA850
144 select GPIO_PCA953X
108 help 145 help
109 Say Y here to select the TI DA850/OMAP-L138 Evaluation Module. 146 Say Y here to select the TI DA850/OMAP-L138 Evaluation Module.
110 147
148choice
149 prompt "Select peripherals connected to expander on UI board"
150 depends on MACH_DAVINCI_DA850_EVM
151 help
152 The presence of User Interface (UI) card on the DA850/OMAP-L138
153 EVM is detected automatically based on successful probe of the I2C
154 based GPIO expander on that card. This option selected in this
155 menu has an effect only in case of a successful UI card detection.
156
157config DA850_UI_NONE
158 bool "No peripheral is enabled"
159 help
160 Say Y if you do not want to enable any of the peripherals connected
161 to TCA6416 expander on DA850/OMAP-L138 EVM UI card
162
163config DA850_UI_RMII
164 bool "RMII Ethernet PHY"
165 help
166 Say Y if you want to use the RMII PHY on the DA850/OMAP-L138 EVM.
167 This PHY is found on the UI daughter card that is supplied with
168 the EVM.
169 NOTE: Please take care while choosing this option, MII PHY will
170 not be functional if RMII mode is selected.
171
172endchoice
173
111config DAVINCI_MUX 174config DAVINCI_MUX
112 bool "DAVINCI multiplexing support" 175 bool "DAVINCI multiplexing support"
113 depends on ARCH_DAVINCI 176 depends on ARCH_DAVINCI
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2e11e847313b..6aac880eb794 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -23,9 +23,15 @@ obj-$(CONFIG_CP_INTC) += cp_intc.o
23# Board specific 23# Board specific
24obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o 24obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
25obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o 25obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
26obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
26obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o 27obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
27obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o 28obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
28obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o 29obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o
29obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o 30obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
30obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o 31obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
31obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o 32obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
33
34# Power Management
35obj-$(CONFIG_CPU_FREQ) += cpufreq.o
36obj-$(CONFIG_CPU_IDLE) += cpuidle.o
37obj-$(CONFIG_SUSPEND) += pm.o sleep.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index bfbb63936f33..dc19870b23cd 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -10,51 +10,194 @@
10 * or implied. 10 * or implied.
11 */ 11 */
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h> 13#include <linux/init.h>
15#include <linux/console.h> 14#include <linux/console.h>
15#include <linux/interrupt.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
16#include <linux/i2c.h> 18#include <linux/i2c.h>
19#include <linux/i2c/pcf857x.h>
17#include <linux/i2c/at24.h> 20#include <linux/i2c/at24.h>
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/partitions.h>
18 23
19#include <asm/mach-types.h> 24#include <asm/mach-types.h>
20#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
21 26
22#include <mach/common.h>
23#include <mach/irqs.h>
24#include <mach/cp_intc.h> 27#include <mach/cp_intc.h>
28#include <mach/mux.h>
29#include <mach/nand.h>
25#include <mach/da8xx.h> 30#include <mach/da8xx.h>
26#include <mach/asp.h> 31#include <mach/usb.h>
27 32
28#define DA830_EVM_PHY_MASK 0x0 33#define DA830_EVM_PHY_MASK 0x0
29#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ 34#define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
30 35
31static struct at24_platform_data da830_evm_i2c_eeprom_info = { 36#define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000
32 .byte_len = SZ_256K / 8, 37#define DA830_EMIF25_CONTROL_BASE 0x68000000
33 .page_size = 64,
34 .flags = AT24_FLAG_ADDR16,
35 .setup = davinci_get_mac_addr,
36 .context = (void *)0x7f00,
37};
38 38
39static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { 39/*
40 { 40 * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4].
41 I2C_BOARD_INFO("24c256", 0x50), 41 */
42 .platform_data = &da830_evm_i2c_eeprom_info, 42#define ON_BD_USB_DRV GPIO_TO_PIN(1, 15)
43 }, 43#define ON_BD_USB_OVC GPIO_TO_PIN(2, 4)
44 { 44
45 I2C_BOARD_INFO("tlv320aic3x", 0x18), 45static const short da830_evm_usb11_pins[] = {
46 } 46 DA830_GPIO1_15, DA830_GPIO2_4,
47 -1
47}; 48};
48 49
49static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { 50static da8xx_ocic_handler_t da830_evm_usb_ocic_handler;
50 .bus_freq = 100, /* kHz */ 51
51 .bus_delay = 0, /* usec */ 52static int da830_evm_usb_set_power(unsigned port, int on)
53{
54 gpio_set_value(ON_BD_USB_DRV, on);
55 return 0;
56}
57
58static int da830_evm_usb_get_power(unsigned port)
59{
60 return gpio_get_value(ON_BD_USB_DRV);
61}
62
63static int da830_evm_usb_get_oci(unsigned port)
64{
65 return !gpio_get_value(ON_BD_USB_OVC);
66}
67
68static irqreturn_t da830_evm_usb_ocic_irq(int, void *);
69
70static int da830_evm_usb_ocic_notify(da8xx_ocic_handler_t handler)
71{
72 int irq = gpio_to_irq(ON_BD_USB_OVC);
73 int error = 0;
74
75 if (handler != NULL) {
76 da830_evm_usb_ocic_handler = handler;
77
78 error = request_irq(irq, da830_evm_usb_ocic_irq, IRQF_DISABLED |
79 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
80 "OHCI over-current indicator", NULL);
81 if (error)
82 printk(KERN_ERR "%s: could not request IRQ to watch "
83 "over-current indicator changes\n", __func__);
84 } else
85 free_irq(irq, NULL);
86
87 return error;
88}
89
90static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = {
91 .set_power = da830_evm_usb_set_power,
92 .get_power = da830_evm_usb_get_power,
93 .get_oci = da830_evm_usb_get_oci,
94 .ocic_notify = da830_evm_usb_ocic_notify,
95
96 /* TPS2065 switch @ 5V */
97 .potpgt = (3 + 1) / 2, /* 3 ms max */
52}; 98};
53 99
100static irqreturn_t da830_evm_usb_ocic_irq(int irq, void *dev_id)
101{
102 da830_evm_usb_ocic_handler(&da830_evm_usb11_pdata, 1);
103 return IRQ_HANDLED;
104}
105
106static __init void da830_evm_usb_init(void)
107{
108 u32 cfgchip2;
109 int ret;
110
111 /*
112 * Set up USB clock/mode in the CFGCHIP2 register.
113 * FYI: CFGCHIP2 is 0x0000ef00 initially.
114 */
115 cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
116
117 /* USB2.0 PHY reference clock is 24 MHz */
118 cfgchip2 &= ~CFGCHIP2_REFFREQ;
119 cfgchip2 |= CFGCHIP2_REFFREQ_24MHZ;
120
121 /*
122 * Select internal reference clock for USB 2.0 PHY
123 * and use it as a clock source for USB 1.1 PHY
124 * (this is the default setting anyway).
125 */
126 cfgchip2 &= ~CFGCHIP2_USB1PHYCLKMUX;
127 cfgchip2 |= CFGCHIP2_USB2PHYCLKMUX;
128
129 /*
130 * We have to override VBUS/ID signals when MUSB is configured into the
131 * host-only mode -- ID pin will float if no cable is connected, so the
132 * controller won't be able to drive VBUS thinking that it's a B-device.
133 * Otherwise, we want to use the OTG mode and enable VBUS comparators.
134 */
135 cfgchip2 &= ~CFGCHIP2_OTGMODE;
136#ifdef CONFIG_USB_MUSB_HOST
137 cfgchip2 |= CFGCHIP2_FORCE_HOST;
138#else
139 cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
140#endif
141
142 __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
143
144 /* USB_REFCLKIN is not used. */
145 ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
146 if (ret)
147 pr_warning("%s: USB 2.0 PinMux setup failed: %d\n",
148 __func__, ret);
149 else {
150 /*
151 * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A),
152 * with the power on to power good time of 3 ms.
153 */
154 ret = da8xx_register_usb20(1000, 3);
155 if (ret)
156 pr_warning("%s: USB 2.0 registration failed: %d\n",
157 __func__, ret);
158 }
159
160 ret = da8xx_pinmux_setup(da830_evm_usb11_pins);
161 if (ret) {
162 pr_warning("%s: USB 1.1 PinMux setup failed: %d\n",
163 __func__, ret);
164 return;
165 }
166
167 ret = gpio_request(ON_BD_USB_DRV, "ON_BD_USB_DRV");
168 if (ret) {
169 printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
170 "power control: %d\n", __func__, ret);
171 return;
172 }
173 gpio_direction_output(ON_BD_USB_DRV, 0);
174
175 ret = gpio_request(ON_BD_USB_OVC, "ON_BD_USB_OVC");
176 if (ret) {
177 printk(KERN_ERR "%s: failed to request GPIO for USB 1.1 port "
178 "over-current indicator: %d\n", __func__, ret);
179 return;
180 }
181 gpio_direction_input(ON_BD_USB_OVC);
182
183 ret = da8xx_register_usb11(&da830_evm_usb11_pdata);
184 if (ret)
185 pr_warning("%s: USB 1.1 registration failed: %d\n",
186 __func__, ret);
187}
188
54static struct davinci_uart_config da830_evm_uart_config __initdata = { 189static struct davinci_uart_config da830_evm_uart_config __initdata = {
55 .enabled_uarts = 0x7, 190 .enabled_uarts = 0x7,
56}; 191};
57 192
193static const short da830_evm_mcasp1_pins[] = {
194 DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
195 DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
196 DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10,
197 DA830_AXR1_11,
198 -1
199};
200
58static u8 da830_iis_serializer_direction[] = { 201static u8 da830_iis_serializer_direction[] = {
59 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 202 RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
60 INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, 203 INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE,
@@ -74,6 +217,271 @@ static struct snd_platform_data da830_evm_snd_data = {
74 .rxnumevt = 1, 217 .rxnumevt = 1,
75}; 218};
76 219
220/*
221 * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS.
222 */
223static const short da830_evm_mmc_sd_pins[] = {
224 DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
225 DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
226 DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
227 DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2,
228 -1
229};
230
231#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
232
233static int da830_evm_mmc_get_ro(int index)
234{
235 return gpio_get_value(DA830_MMCSD_WP_PIN);
236}
237
238static struct davinci_mmc_config da830_evm_mmc_config = {
239 .get_ro = da830_evm_mmc_get_ro,
240 .wires = 4,
241 .max_freq = 50000000,
242 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
243 .version = MMC_CTLR_VERSION_2,
244};
245
246static inline void da830_evm_init_mmc(void)
247{
248 int ret;
249
250 ret = da8xx_pinmux_setup(da830_evm_mmc_sd_pins);
251 if (ret) {
252 pr_warning("da830_evm_init: mmc/sd mux setup failed: %d\n",
253 ret);
254 return;
255 }
256
257 ret = gpio_request(DA830_MMCSD_WP_PIN, "MMC WP");
258 if (ret) {
259 pr_warning("da830_evm_init: can not open GPIO %d\n",
260 DA830_MMCSD_WP_PIN);
261 return;
262 }
263 gpio_direction_input(DA830_MMCSD_WP_PIN);
264
265 ret = da8xx_register_mmcsd0(&da830_evm_mmc_config);
266 if (ret) {
267 pr_warning("da830_evm_init: mmc/sd registration failed: %d\n",
268 ret);
269 gpio_free(DA830_MMCSD_WP_PIN);
270 }
271}
272
273/*
274 * UI board NAND/NOR flashes only use 8-bit data bus.
275 */
276static const short da830_evm_emif25_pins[] = {
277 DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
278 DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
279 DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
280 DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
281 DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
282 DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE,
283 DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0,
284 -1
285};
286
287#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
288#define HAS_MMC 1
289#else
290#define HAS_MMC 0
291#endif
292
293#ifdef CONFIG_DA830_UI_NAND
294static struct mtd_partition da830_evm_nand_partitions[] = {
295 /* bootloader (U-Boot, etc) in first sector */
296 [0] = {
297 .name = "bootloader",
298 .offset = 0,
299 .size = SZ_128K,
300 .mask_flags = MTD_WRITEABLE, /* force read-only */
301 },
302 /* bootloader params in the next sector */
303 [1] = {
304 .name = "params",
305 .offset = MTDPART_OFS_APPEND,
306 .size = SZ_128K,
307 .mask_flags = MTD_WRITEABLE, /* force read-only */
308 },
309 /* kernel */
310 [2] = {
311 .name = "kernel",
312 .offset = MTDPART_OFS_APPEND,
313 .size = SZ_2M,
314 .mask_flags = 0,
315 },
316 /* file system */
317 [3] = {
318 .name = "filesystem",
319 .offset = MTDPART_OFS_APPEND,
320 .size = MTDPART_SIZ_FULL,
321 .mask_flags = 0,
322 }
323};
324
325/* flash bbt decriptors */
326static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' };
327static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' };
328
329static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = {
330 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
331 NAND_BBT_WRITE | NAND_BBT_2BIT |
332 NAND_BBT_VERSION | NAND_BBT_PERCHIP,
333 .offs = 2,
334 .len = 4,
335 .veroffs = 16,
336 .maxblocks = 4,
337 .pattern = da830_evm_nand_bbt_pattern
338};
339
340static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = {
341 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE |
342 NAND_BBT_WRITE | NAND_BBT_2BIT |
343 NAND_BBT_VERSION | NAND_BBT_PERCHIP,
344 .offs = 2,
345 .len = 4,
346 .veroffs = 16,
347 .maxblocks = 4,
348 .pattern = da830_evm_nand_mirror_pattern
349};
350
351static struct davinci_nand_pdata da830_evm_nand_pdata = {
352 .parts = da830_evm_nand_partitions,
353 .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions),
354 .ecc_mode = NAND_ECC_HW,
355 .ecc_bits = 4,
356 .options = NAND_USE_FLASH_BBT,
357 .bbt_td = &da830_evm_nand_bbt_main_descr,
358 .bbt_md = &da830_evm_nand_bbt_mirror_descr,
359};
360
361static struct resource da830_evm_nand_resources[] = {
362 [0] = { /* First memory resource is NAND I/O window */
363 .start = DA830_EMIF25_ASYNC_DATA_CE3_BASE,
364 .end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 [1] = { /* Second memory resource is AEMIF control registers */
368 .start = DA830_EMIF25_CONTROL_BASE,
369 .end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1,
370 .flags = IORESOURCE_MEM,
371 },
372};
373
374static struct platform_device da830_evm_nand_device = {
375 .name = "davinci_nand",
376 .id = 1,
377 .dev = {
378 .platform_data = &da830_evm_nand_pdata,
379 },
380 .num_resources = ARRAY_SIZE(da830_evm_nand_resources),
381 .resource = da830_evm_nand_resources,
382};
383
384static inline void da830_evm_init_nand(int mux_mode)
385{
386 int ret;
387
388 if (HAS_MMC) {
389 pr_warning("WARNING: both MMC/SD and NAND are "
390 "enabled, but they share AEMIF pins.\n"
391 "\tDisable MMC/SD for NAND support.\n");
392 return;
393 }
394
395 ret = da8xx_pinmux_setup(da830_evm_emif25_pins);
396 if (ret)
397 pr_warning("da830_evm_init: emif25 mux setup failed: %d\n",
398 ret);
399
400 ret = platform_device_register(&da830_evm_nand_device);
401 if (ret)
402 pr_warning("da830_evm_init: NAND device not registered.\n");
403
404 gpio_direction_output(mux_mode, 1);
405}
406#else
407static inline void da830_evm_init_nand(int mux_mode) { }
408#endif
409
410#ifdef CONFIG_DA830_UI_LCD
411static inline void da830_evm_init_lcdc(int mux_mode)
412{
413 int ret;
414
415 ret = da8xx_pinmux_setup(da830_lcdcntl_pins);
416 if (ret)
417 pr_warning("da830_evm_init: lcdcntl mux setup failed: %d\n",
418 ret);
419
420 ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata);
421 if (ret)
422 pr_warning("da830_evm_init: lcd setup failed: %d\n", ret);
423
424 gpio_direction_output(mux_mode, 0);
425}
426#else
427static inline void da830_evm_init_lcdc(int mux_mode) { }
428#endif
429
430static struct at24_platform_data da830_evm_i2c_eeprom_info = {
431 .byte_len = SZ_256K / 8,
432 .page_size = 64,
433 .flags = AT24_FLAG_ADDR16,
434 .setup = davinci_get_mac_addr,
435 .context = (void *)0x7f00,
436};
437
438static int __init da830_evm_ui_expander_setup(struct i2c_client *client,
439 int gpio, unsigned ngpio, void *context)
440{
441 gpio_request(gpio + 6, "UI MUX_MODE");
442
443 /* Drive mux mode low to match the default without UI card */
444 gpio_direction_output(gpio + 6, 0);
445
446 da830_evm_init_lcdc(gpio + 6);
447
448 da830_evm_init_nand(gpio + 6);
449
450 return 0;
451}
452
453static int da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio,
454 unsigned ngpio, void *context)
455{
456 gpio_free(gpio + 6);
457 return 0;
458}
459
460static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = {
461 .gpio_base = DAVINCI_N_GPIO,
462 .setup = da830_evm_ui_expander_setup,
463 .teardown = da830_evm_ui_expander_teardown,
464};
465
466static struct i2c_board_info __initdata da830_evm_i2c_devices[] = {
467 {
468 I2C_BOARD_INFO("24c256", 0x50),
469 .platform_data = &da830_evm_i2c_eeprom_info,
470 },
471 {
472 I2C_BOARD_INFO("tlv320aic3x", 0x18),
473 },
474 {
475 I2C_BOARD_INFO("pcf8574", 0x3f),
476 .platform_data = &da830_evm_ui_expander_info,
477 },
478};
479
480static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = {
481 .bus_freq = 100, /* kHz */
482 .bus_delay = 0, /* usec */
483};
484
77static __init void da830_evm_init(void) 485static __init void da830_evm_init(void)
78{ 486{
79 struct davinci_soc_info *soc_info = &davinci_soc_info; 487 struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -94,6 +502,8 @@ static __init void da830_evm_init(void)
94 pr_warning("da830_evm_init: i2c0 registration failed: %d\n", 502 pr_warning("da830_evm_init: i2c0 registration failed: %d\n",
95 ret); 503 ret);
96 504
505 da830_evm_usb_init();
506
97 soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK; 507 soc_info->emac_pdata->phy_mask = DA830_EVM_PHY_MASK;
98 soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY; 508 soc_info->emac_pdata->mdio_max_freq = DA830_EVM_MDIO_FREQUENCY;
99 soc_info->emac_pdata->rmii_en = 1; 509 soc_info->emac_pdata->rmii_en = 1;
@@ -117,12 +527,18 @@ static __init void da830_evm_init(void)
117 i2c_register_board_info(1, da830_evm_i2c_devices, 527 i2c_register_board_info(1, da830_evm_i2c_devices,
118 ARRAY_SIZE(da830_evm_i2c_devices)); 528 ARRAY_SIZE(da830_evm_i2c_devices));
119 529
120 ret = da8xx_pinmux_setup(da830_mcasp1_pins); 530 ret = da8xx_pinmux_setup(da830_evm_mcasp1_pins);
121 if (ret) 531 if (ret)
122 pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n", 532 pr_warning("da830_evm_init: mcasp1 mux setup failed: %d\n",
123 ret); 533 ret);
124 534
125 da8xx_init_mcasp(1, &da830_evm_snd_data); 535 da8xx_register_mcasp(1, &da830_evm_snd_data);
536
537 da830_evm_init_mmc();
538
539 ret = da8xx_register_rtc();
540 if (ret)
541 pr_warning("da830_evm_init: rtc setup failed: %d\n", ret);
126} 542}
127 543
128#ifdef CONFIG_SERIAL_8250_CONSOLE 544#ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -146,7 +562,7 @@ static void __init da830_evm_map_io(void)
146 da830_init(); 562 da830_init();
147} 563}
148 564
149MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP L137 EVM") 565MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
150 .phys_io = IO_PHYS, 566 .phys_io = IO_PHYS,
151 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 567 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
152 .boot_params = (DA8XX_DDR_BASE + 0x100), 568 .boot_params = (DA8XX_DDR_BASE + 0x100),
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index c759d72494e0..411284d0b0fa 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -12,40 +12,54 @@
12 * or implied. 12 * or implied.
13 */ 13 */
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h> 15#include <linux/init.h>
17#include <linux/console.h> 16#include <linux/console.h>
18#include <linux/i2c.h> 17#include <linux/i2c.h>
19#include <linux/i2c/at24.h> 18#include <linux/i2c/at24.h>
19#include <linux/i2c/pca953x.h>
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/mtd/mtd.h> 22#include <linux/mtd/mtd.h>
23#include <linux/mtd/nand.h> 23#include <linux/mtd/nand.h>
24#include <linux/mtd/partitions.h> 24#include <linux/mtd/partitions.h>
25#include <linux/mtd/physmap.h> 25#include <linux/mtd/physmap.h>
26#include <linux/regulator/machine.h>
26 27
27#include <asm/mach-types.h> 28#include <asm/mach-types.h>
28#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
29 30
30#include <mach/common.h>
31#include <mach/irqs.h>
32#include <mach/cp_intc.h> 31#include <mach/cp_intc.h>
33#include <mach/da8xx.h> 32#include <mach/da8xx.h>
34#include <mach/nand.h> 33#include <mach/nand.h>
34#include <mach/mux.h>
35 35
36#define DA850_EVM_PHY_MASK 0x1 36#define DA850_EVM_PHY_MASK 0x1
37#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ 37#define DA850_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
38 38
39#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
39#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) 40#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
40#define DA850_LCD_PWR_PIN GPIO_TO_PIN(8, 10)
41 41
42#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) 42#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
43#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) 43#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
44 44
45#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6)
46
45static struct mtd_partition da850_evm_norflash_partition[] = { 47static struct mtd_partition da850_evm_norflash_partition[] = {
46 { 48 {
47 .name = "NOR filesystem", 49 .name = "bootloaders + env",
48 .offset = 0, 50 .offset = 0,
51 .size = SZ_512K,
52 .mask_flags = MTD_WRITEABLE,
53 },
54 {
55 .name = "kernel",
56 .offset = MTDPART_OFS_APPEND,
57 .size = SZ_2M,
58 .mask_flags = 0,
59 },
60 {
61 .name = "filesystem",
62 .offset = MTDPART_OFS_APPEND,
49 .size = MTDPART_SIZ_FULL, 63 .size = MTDPART_SIZ_FULL,
50 .mask_flags = 0, 64 .mask_flags = 0,
51 }, 65 },
@@ -75,6 +89,18 @@ static struct platform_device da850_evm_norflash_device = {
75 .resource = da850_evm_norflash_resource, 89 .resource = da850_evm_norflash_resource,
76}; 90};
77 91
92static struct davinci_pm_config da850_pm_pdata = {
93 .sleepcount = 128,
94};
95
96static struct platform_device da850_pm_device = {
97 .name = "pm-davinci",
98 .dev = {
99 .platform_data = &da850_pm_pdata,
100 },
101 .id = -1,
102};
103
78/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash 104/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
79 * (128K blocks). It may be used instead of the (default) SPI flash 105 * (128K blocks). It may be used instead of the (default) SPI flash
80 * to boot, using TI's tools to install the secondary boot loader 106 * to boot, using TI's tools to install the secondary boot loader
@@ -117,6 +143,7 @@ static struct davinci_nand_pdata da850_evm_nandflash_data = {
117 .parts = da850_evm_nandflash_partition, 143 .parts = da850_evm_nandflash_partition,
118 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), 144 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
119 .ecc_mode = NAND_ECC_HW, 145 .ecc_mode = NAND_ECC_HW,
146 .ecc_bits = 4,
120 .options = NAND_USE_FLASH_BBT, 147 .options = NAND_USE_FLASH_BBT,
121}; 148};
122 149
@@ -143,10 +170,149 @@ static struct platform_device da850_evm_nandflash_device = {
143 .resource = da850_evm_nandflash_resource, 170 .resource = da850_evm_nandflash_resource,
144}; 171};
145 172
173static struct platform_device *da850_evm_devices[] __initdata = {
174 &da850_evm_nandflash_device,
175 &da850_evm_norflash_device,
176};
177
178#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10
179#define DA8XX_AEMIF_ASIZE_16BIT 0x1
180
181static void __init da850_evm_init_nor(void)
182{
183 void __iomem *aemif_addr;
184
185 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K);
186
187 /* Configure data bus width of CS2 to 16 bit */
188 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) |
189 DA8XX_AEMIF_ASIZE_16BIT,
190 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET);
191
192 iounmap(aemif_addr);
193}
194
195static u32 ui_card_detected;
196
197#if defined(CONFIG_MMC_DAVINCI) || \
198 defined(CONFIG_MMC_DAVINCI_MODULE)
199#define HAS_MMC 1
200#else
201#define HAS_MMC 0
202#endif
203
204static __init void da850_evm_setup_nor_nand(void)
205{
206 int ret = 0;
207
208 if (ui_card_detected & !HAS_MMC) {
209 ret = da8xx_pinmux_setup(da850_nand_pins);
210 if (ret)
211 pr_warning("da850_evm_init: nand mux setup failed: "
212 "%d\n", ret);
213
214 ret = da8xx_pinmux_setup(da850_nor_pins);
215 if (ret)
216 pr_warning("da850_evm_init: nor mux setup failed: %d\n",
217 ret);
218
219 da850_evm_init_nor();
220
221 platform_add_devices(da850_evm_devices,
222 ARRAY_SIZE(da850_evm_devices));
223 }
224}
225
226#ifdef CONFIG_DA850_UI_RMII
227static inline void da850_evm_setup_emac_rmii(int rmii_sel)
228{
229 struct davinci_soc_info *soc_info = &davinci_soc_info;
230
231 soc_info->emac_pdata->rmii_en = 1;
232 gpio_set_value(rmii_sel, 0);
233}
234#else
235static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
236#endif
237
238static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
239 unsigned ngpio, void *c)
240{
241 int sel_a, sel_b, sel_c, ret;
242
243 sel_a = gpio + 7;
244 sel_b = gpio + 6;
245 sel_c = gpio + 5;
246
247 ret = gpio_request(sel_a, "sel_a");
248 if (ret) {
249 pr_warning("Cannot open UI expander pin %d\n", sel_a);
250 goto exp_setup_sela_fail;
251 }
252
253 ret = gpio_request(sel_b, "sel_b");
254 if (ret) {
255 pr_warning("Cannot open UI expander pin %d\n", sel_b);
256 goto exp_setup_selb_fail;
257 }
258
259 ret = gpio_request(sel_c, "sel_c");
260 if (ret) {
261 pr_warning("Cannot open UI expander pin %d\n", sel_c);
262 goto exp_setup_selc_fail;
263 }
264
265 /* deselect all functionalities */
266 gpio_direction_output(sel_a, 1);
267 gpio_direction_output(sel_b, 1);
268 gpio_direction_output(sel_c, 1);
269
270 ui_card_detected = 1;
271 pr_info("DA850/OMAP-L138 EVM UI card detected\n");
272
273 da850_evm_setup_nor_nand();
274
275 da850_evm_setup_emac_rmii(sel_a);
276
277 return 0;
278
279exp_setup_selc_fail:
280 gpio_free(sel_b);
281exp_setup_selb_fail:
282 gpio_free(sel_a);
283exp_setup_sela_fail:
284 return ret;
285}
286
287static int da850_evm_ui_expander_teardown(struct i2c_client *client,
288 unsigned gpio, unsigned ngpio, void *c)
289{
290 /* deselect all functionalities */
291 gpio_set_value(gpio + 5, 1);
292 gpio_set_value(gpio + 6, 1);
293 gpio_set_value(gpio + 7, 1);
294
295 gpio_free(gpio + 5);
296 gpio_free(gpio + 6);
297 gpio_free(gpio + 7);
298
299 return 0;
300}
301
302static struct pca953x_platform_data da850_evm_ui_expander_info = {
303 .gpio_base = DAVINCI_N_GPIO,
304 .setup = da850_evm_ui_expander_setup,
305 .teardown = da850_evm_ui_expander_teardown,
306};
307
146static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { 308static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
147 { 309 {
148 I2C_BOARD_INFO("tlv320aic3x", 0x18), 310 I2C_BOARD_INFO("tlv320aic3x", 0x18),
149 } 311 },
312 {
313 I2C_BOARD_INFO("tca6416", 0x20),
314 .platform_data = &da850_evm_ui_expander_info,
315 },
150}; 316};
151 317
152static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { 318static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
@@ -158,11 +324,6 @@ static struct davinci_uart_config da850_evm_uart_config __initdata = {
158 .enabled_uarts = 0x7, 324 .enabled_uarts = 0x7,
159}; 325};
160 326
161static struct platform_device *da850_evm_devices[] __initdata = {
162 &da850_evm_nandflash_device,
163 &da850_evm_norflash_device,
164};
165
166/* davinci da850 evm audio machine driver */ 327/* davinci da850 evm audio machine driver */
167static u8 da850_iis_serializer_direction[] = { 328static u8 da850_iis_serializer_direction[] = {
168 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 329 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
@@ -198,9 +359,20 @@ static struct davinci_mmc_config da850_mmc_config = {
198 .get_ro = da850_evm_mmc_get_ro, 359 .get_ro = da850_evm_mmc_get_ro,
199 .get_cd = da850_evm_mmc_get_cd, 360 .get_cd = da850_evm_mmc_get_cd,
200 .wires = 4, 361 .wires = 4,
362 .max_freq = 50000000,
363 .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
201 .version = MMC_CTLR_VERSION_2, 364 .version = MMC_CTLR_VERSION_2,
202}; 365};
203 366
367static void da850_panel_power_ctrl(int val)
368{
369 /* lcd backlight */
370 gpio_set_value(DA850_LCD_BL_PIN, val);
371
372 /* lcd power */
373 gpio_set_value(DA850_LCD_PWR_PIN, val);
374}
375
204static int da850_lcd_hw_init(void) 376static int da850_lcd_hw_init(void)
205{ 377{
206 int status; 378 int status;
@@ -218,71 +390,236 @@ static int da850_lcd_hw_init(void)
218 gpio_direction_output(DA850_LCD_BL_PIN, 0); 390 gpio_direction_output(DA850_LCD_BL_PIN, 0);
219 gpio_direction_output(DA850_LCD_PWR_PIN, 0); 391 gpio_direction_output(DA850_LCD_PWR_PIN, 0);
220 392
221 /* disable lcd backlight */ 393 /* Switch off panel power and backlight */
222 gpio_set_value(DA850_LCD_BL_PIN, 0); 394 da850_panel_power_ctrl(0);
223 395
224 /* disable lcd power */ 396 /* Switch on panel power and backlight */
225 gpio_set_value(DA850_LCD_PWR_PIN, 0); 397 da850_panel_power_ctrl(1);
226
227 /* enable lcd power */
228 gpio_set_value(DA850_LCD_PWR_PIN, 1);
229
230 /* enable lcd backlight */
231 gpio_set_value(DA850_LCD_BL_PIN, 1);
232 398
233 return 0; 399 return 0;
234} 400}
235 401
236#define DA8XX_AEMIF_CE2CFG_OFFSET 0x10 402/* TPS65070 voltage regulator support */
237#define DA8XX_AEMIF_ASIZE_16BIT 0x1
238 403
239static void __init da850_evm_init_nor(void) 404/* 3.3V */
240{ 405struct regulator_consumer_supply tps65070_dcdc1_consumers[] = {
241 void __iomem *aemif_addr; 406 {
407 .supply = "usb0_vdda33",
408 },
409 {
410 .supply = "usb1_vdda33",
411 },
412};
242 413
243 aemif_addr = ioremap(DA8XX_AEMIF_CTL_BASE, SZ_32K); 414/* 3.3V or 1.8V */
415struct regulator_consumer_supply tps65070_dcdc2_consumers[] = {
416 {
417 .supply = "dvdd3318_a",
418 },
419 {
420 .supply = "dvdd3318_b",
421 },
422 {
423 .supply = "dvdd3318_c",
424 },
425};
244 426
245 /* Configure data bus width of CS2 to 16 bit */ 427/* 1.2V */
246 writel(readl(aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET) | 428struct regulator_consumer_supply tps65070_dcdc3_consumers[] = {
247 DA8XX_AEMIF_ASIZE_16BIT, 429 {
248 aemif_addr + DA8XX_AEMIF_CE2CFG_OFFSET); 430 .supply = "cvdd",
431 },
432};
249 433
250 iounmap(aemif_addr); 434/* 1.8V LDO */
251} 435struct regulator_consumer_supply tps65070_ldo1_consumers[] = {
436 {
437 .supply = "sata_vddr",
438 },
439 {
440 .supply = "usb0_vdda18",
441 },
442 {
443 .supply = "usb1_vdda18",
444 },
445 {
446 .supply = "ddr_dvdd18",
447 },
448};
252 449
253#if defined(CONFIG_MTD_PHYSMAP) || \ 450/* 1.2V LDO */
254 defined(CONFIG_MTD_PHYSMAP_MODULE) 451struct regulator_consumer_supply tps65070_ldo2_consumers[] = {
255#define HAS_NOR 1 452 {
256#else 453 .supply = "sata_vdd",
257#define HAS_NOR 0 454 },
258#endif 455 {
456 .supply = "pll0_vdda",
457 },
458 {
459 .supply = "pll1_vdda",
460 },
461 {
462 .supply = "usbs_cvdd",
463 },
464 {
465 .supply = "vddarnwa1",
466 },
467};
259 468
260#if defined(CONFIG_MMC_DAVINCI) || \ 469struct regulator_init_data tps65070_regulator_data[] = {
261 defined(CONFIG_MMC_DAVINCI_MODULE) 470 /* dcdc1 */
262#define HAS_MMC 1 471 {
263#else 472 .constraints = {
264#define HAS_MMC 0 473 .min_uV = 3150000,
265#endif 474 .max_uV = 3450000,
475 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
476 REGULATOR_CHANGE_STATUS),
477 .boot_on = 1,
478 },
479 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers),
480 .consumer_supplies = tps65070_dcdc1_consumers,
481 },
266 482
267static __init void da850_evm_init(void) 483 /* dcdc2 */
484 {
485 .constraints = {
486 .min_uV = 1710000,
487 .max_uV = 3450000,
488 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
489 REGULATOR_CHANGE_STATUS),
490 .boot_on = 1,
491 },
492 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers),
493 .consumer_supplies = tps65070_dcdc2_consumers,
494 },
495
496 /* dcdc3 */
497 {
498 .constraints = {
499 .min_uV = 950000,
500 .max_uV = 1320000,
501 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
502 REGULATOR_CHANGE_STATUS),
503 .boot_on = 1,
504 },
505 .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers),
506 .consumer_supplies = tps65070_dcdc3_consumers,
507 },
508
509 /* ldo1 */
510 {
511 .constraints = {
512 .min_uV = 1710000,
513 .max_uV = 1890000,
514 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
515 REGULATOR_CHANGE_STATUS),
516 .boot_on = 1,
517 },
518 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers),
519 .consumer_supplies = tps65070_ldo1_consumers,
520 },
521
522 /* ldo2 */
523 {
524 .constraints = {
525 .min_uV = 1140000,
526 .max_uV = 1320000,
527 .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
528 REGULATOR_CHANGE_STATUS),
529 .boot_on = 1,
530 },
531 .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers),
532 .consumer_supplies = tps65070_ldo2_consumers,
533 },
534};
535
536static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
537 {
538 I2C_BOARD_INFO("tps6507x", 0x48),
539 .platform_data = &tps65070_regulator_data[0],
540 },
541};
542
543static int __init pmic_tps65070_init(void)
268{ 544{
269 struct davinci_soc_info *soc_info = &davinci_soc_info; 545 return i2c_register_board_info(1, da850evm_tps65070_info,
546 ARRAY_SIZE(da850evm_tps65070_info));
547}
548
549static const short da850_evm_lcdc_pins[] = {
550 DA850_GPIO2_8, DA850_GPIO2_15,
551 -1
552};
553
554static int __init da850_evm_config_emac(void)
555{
556 void __iomem *cfg_chip3_base;
270 int ret; 557 int ret;
558 u32 val;
559 struct davinci_soc_info *soc_info = &davinci_soc_info;
560 u8 rmii_en = soc_info->emac_pdata->rmii_en;
561
562 if (!machine_is_davinci_da850_evm())
563 return 0;
564
565 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
566
567 val = __raw_readl(cfg_chip3_base);
568
569 if (rmii_en) {
570 val |= BIT(8);
571 ret = da8xx_pinmux_setup(da850_rmii_pins);
572 pr_info("EMAC: RMII PHY configured, MII PHY will not be"
573 " functional\n");
574 } else {
575 val &= ~BIT(8);
576 ret = da8xx_pinmux_setup(da850_cpgmac_pins);
577 pr_info("EMAC: MII PHY configured, RMII PHY will not be"
578 " functional\n");
579 }
271 580
272 ret = da8xx_pinmux_setup(da850_nand_pins);
273 if (ret) 581 if (ret)
274 pr_warning("da850_evm_init: nand mux setup failed: %d\n", 582 pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n",
275 ret); 583 ret);
276 584
277 ret = da8xx_pinmux_setup(da850_nor_pins); 585 /* configure the CFGCHIP3 register for RMII or MII */
586 __raw_writel(val, cfg_chip3_base);
587
588 ret = davinci_cfg_reg(DA850_GPIO2_6);
589 if (ret)
590 pr_warning("da850_evm_init:GPIO(2,6) mux setup "
591 "failed\n");
592
593 ret = gpio_request(DA850_MII_MDIO_CLKEN_PIN, "mdio_clk_en");
594 if (ret) {
595 pr_warning("Cannot open GPIO %d\n",
596 DA850_MII_MDIO_CLKEN_PIN);
597 return ret;
598 }
599
600 /* Enable/Disable MII MDIO clock */
601 gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
602
603 soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
604 soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
605
606 ret = da8xx_register_emac();
278 if (ret) 607 if (ret)
279 pr_warning("da850_evm_init: nor mux setup failed: %d\n", 608 pr_warning("da850_evm_init: emac registration failed: %d\n",
280 ret); 609 ret);
281 610
282 da850_evm_init_nor(); 611 return 0;
612}
613device_initcall(da850_evm_config_emac);
283 614
284 platform_add_devices(da850_evm_devices, 615static __init void da850_evm_init(void)
285 ARRAY_SIZE(da850_evm_devices)); 616{
617 int ret;
618
619 ret = pmic_tps65070_init();
620 if (ret)
621 pr_warning("da850_evm_init: TPS65070 PMIC init failed: %d\n",
622 ret);
286 623
287 ret = da8xx_register_edma(); 624 ret = da8xx_register_edma();
288 if (ret) 625 if (ret)
@@ -299,19 +636,6 @@ static __init void da850_evm_init(void)
299 pr_warning("da850_evm_init: i2c0 registration failed: %d\n", 636 pr_warning("da850_evm_init: i2c0 registration failed: %d\n",
300 ret); 637 ret);
301 638
302 soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
303 soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
304 soc_info->emac_pdata->rmii_en = 0;
305
306 ret = da8xx_pinmux_setup(da850_cpgmac_pins);
307 if (ret)
308 pr_warning("da850_evm_init: cpgmac mux setup failed: %d\n",
309 ret);
310
311 ret = da8xx_register_emac();
312 if (ret)
313 pr_warning("da850_evm_init: emac registration failed: %d\n",
314 ret);
315 639
316 ret = da8xx_register_watchdog(); 640 ret = da8xx_register_watchdog();
317 if (ret) 641 if (ret)
@@ -319,11 +643,6 @@ static __init void da850_evm_init(void)
319 ret); 643 ret);
320 644
321 if (HAS_MMC) { 645 if (HAS_MMC) {
322 if (HAS_NOR)
323 pr_warning("WARNING: both NOR Flash and MMC/SD are "
324 "enabled, but they share AEMIF pins.\n"
325 "\tDisable one of them.\n");
326
327 ret = da8xx_pinmux_setup(da850_mmcsd0_pins); 646 ret = da8xx_pinmux_setup(da850_mmcsd0_pins);
328 if (ret) 647 if (ret)
329 pr_warning("da850_evm_init: mmcsd0 mux setup failed:" 648 pr_warning("da850_evm_init: mmcsd0 mux setup failed:"
@@ -365,22 +684,48 @@ static __init void da850_evm_init(void)
365 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n", 684 pr_warning("da850_evm_init: mcasp mux setup failed: %d\n",
366 ret); 685 ret);
367 686
368 da8xx_init_mcasp(0, &da850_evm_snd_data); 687 da8xx_register_mcasp(0, &da850_evm_snd_data);
369 688
370 ret = da8xx_pinmux_setup(da850_lcdcntl_pins); 689 ret = da8xx_pinmux_setup(da850_lcdcntl_pins);
371 if (ret) 690 if (ret)
372 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n", 691 pr_warning("da850_evm_init: lcdcntl mux setup failed: %d\n",
373 ret); 692 ret);
374 693
694 /* Handle board specific muxing for LCD here */
695 ret = da8xx_pinmux_setup(da850_evm_lcdc_pins);
696 if (ret)
697 pr_warning("da850_evm_init: evm specific lcd mux setup "
698 "failed: %d\n", ret);
699
375 ret = da850_lcd_hw_init(); 700 ret = da850_lcd_hw_init();
376 if (ret) 701 if (ret)
377 pr_warning("da850_evm_init: lcd initialization failed: %d\n", 702 pr_warning("da850_evm_init: lcd initialization failed: %d\n",
378 ret); 703 ret);
379 704
380 ret = da8xx_register_lcdc(); 705 sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl,
706 ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata);
381 if (ret) 707 if (ret)
382 pr_warning("da850_evm_init: lcdc registration failed: %d\n", 708 pr_warning("da850_evm_init: lcdc registration failed: %d\n",
383 ret); 709 ret);
710
711 ret = da8xx_register_rtc();
712 if (ret)
713 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
714
715 ret = da850_register_cpufreq();
716 if (ret)
717 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
718 ret);
719
720 ret = da8xx_register_cpuidle();
721 if (ret)
722 pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
723 ret);
724
725 ret = da850_register_pm(&da850_pm_device);
726 if (ret)
727 pr_warning("da850_evm_init: suspend registration failed: %d\n",
728 ret);
384} 729}
385 730
386#ifdef CONFIG_SERIAL_8250_CONSOLE 731#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 77e806798822..aa48e3f69715 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -9,15 +9,13 @@
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/dma-mapping.h> 13#include <linux/err.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
16#include <linux/mtd/mtd.h> 15#include <linux/mtd/mtd.h>
17#include <linux/mtd/partitions.h> 16#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h> 17#include <linux/mtd/nand.h>
19#include <linux/i2c.h> 18#include <linux/i2c.h>
20#include <linux/io.h>
21#include <linux/gpio.h> 19#include <linux/gpio.h>
22#include <linux/clk.h> 20#include <linux/clk.h>
23#include <linux/videodev2.h> 21#include <linux/videodev2.h>
@@ -25,20 +23,15 @@
25#include <linux/spi/spi.h> 23#include <linux/spi/spi.h>
26#include <linux/spi/eeprom.h> 24#include <linux/spi/eeprom.h>
27 25
28#include <asm/setup.h>
29#include <asm/mach-types.h> 26#include <asm/mach-types.h>
30#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
31#include <asm/mach/map.h>
32#include <asm/mach/flash.h>
33 28
34#include <mach/hardware.h>
35#include <mach/dm355.h> 29#include <mach/dm355.h>
36#include <mach/psc.h>
37#include <mach/common.h>
38#include <mach/i2c.h> 30#include <mach/i2c.h>
39#include <mach/serial.h> 31#include <mach/serial.h>
40#include <mach/nand.h> 32#include <mach/nand.h>
41#include <mach/mmc.h> 33#include <mach/mmc.h>
34#include <mach/usb.h>
42 35
43#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 36#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
44#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 37#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
@@ -86,8 +79,9 @@ static struct davinci_nand_pdata davinci_nand_data = {
86 .mask_chipsel = BIT(14), 79 .mask_chipsel = BIT(14),
87 .parts = davinci_nand_partitions, 80 .parts = davinci_nand_partitions,
88 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 81 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
89 .ecc_mode = NAND_ECC_HW_SYNDROME, 82 .ecc_mode = NAND_ECC_HW,
90 .options = NAND_USE_FLASH_BBT, 83 .options = NAND_USE_FLASH_BBT,
84 .ecc_bits = 4,
91}; 85};
92 86
93static struct resource davinci_nand_resources[] = { 87static struct resource davinci_nand_resources[] = {
@@ -117,6 +111,8 @@ static struct platform_device davinci_nand_device = {
117static struct davinci_i2c_platform_data i2c_pdata = { 111static struct davinci_i2c_platform_data i2c_pdata = {
118 .bus_freq = 400 /* kHz */, 112 .bus_freq = 400 /* kHz */,
119 .bus_delay = 0 /* usec */, 113 .bus_delay = 0 /* usec */,
114 .sda_pin = 15,
115 .scl_pin = 14,
120}; 116};
121 117
122static struct snd_platform_data dm355_evm_snd_data; 118static struct snd_platform_data dm355_evm_snd_data;
@@ -242,6 +238,7 @@ static struct vpfe_subdev_info vpfe_sub_devs[] = {
242 238
243static struct vpfe_config vpfe_cfg = { 239static struct vpfe_config vpfe_cfg = {
244 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), 240 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
241 .i2c_adapter_id = 1,
245 .sub_devs = vpfe_sub_devs, 242 .sub_devs = vpfe_sub_devs,
246 .card_name = "DM355 EVM", 243 .card_name = "DM355 EVM",
247 .ccdc = "DM355 CCDC", 244 .ccdc = "DM355 CCDC",
@@ -344,7 +341,7 @@ static __init void dm355_evm_init(void)
344 gpio_request(2, "usb_id_toggle"); 341 gpio_request(2, "usb_id_toggle");
345 gpio_direction_output(2, USB_ID_VALUE); 342 gpio_direction_output(2, USB_ID_VALUE);
346 /* irlml6401 switches over 1A in under 8 msec */ 343 /* irlml6401 switches over 1A in under 8 msec */
347 setup_usb(500, 8); 344 davinci_setup_usb(1000, 8);
348 345
349 davinci_setup_mmc(0, &dm355evm_mmc_config); 346 davinci_setup_mmc(0, &dm355evm_mmc_config);
350 davinci_setup_mmc(1, &dm355evm_mmc_config); 347 davinci_setup_mmc(1, &dm355evm_mmc_config);
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 84ad5d161a87..21f32eb41e8c 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -8,34 +8,27 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10#include <linux/kernel.h> 10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/dma-mapping.h> 12#include <linux/err.h>
14#include <linux/platform_device.h> 13#include <linux/platform_device.h>
15#include <linux/mtd/mtd.h> 14#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h> 15#include <linux/mtd/partitions.h>
17#include <linux/mtd/nand.h> 16#include <linux/mtd/nand.h>
18#include <linux/i2c.h> 17#include <linux/i2c.h>
19#include <linux/io.h>
20#include <linux/gpio.h> 18#include <linux/gpio.h>
21#include <linux/clk.h> 19#include <linux/clk.h>
22#include <linux/spi/spi.h> 20#include <linux/spi/spi.h>
23#include <linux/spi/eeprom.h> 21#include <linux/spi/eeprom.h>
24 22
25#include <asm/setup.h>
26#include <asm/mach-types.h> 23#include <asm/mach-types.h>
27#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/flash.h>
30 25
31#include <mach/hardware.h>
32#include <mach/dm355.h> 26#include <mach/dm355.h>
33#include <mach/psc.h>
34#include <mach/common.h>
35#include <mach/i2c.h> 27#include <mach/i2c.h>
36#include <mach/serial.h> 28#include <mach/serial.h>
37#include <mach/nand.h> 29#include <mach/nand.h>
38#include <mach/mmc.h> 30#include <mach/mmc.h>
31#include <mach/usb.h>
39 32
40#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000 33#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e10000
41#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 34#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
@@ -270,7 +263,7 @@ static __init void dm355_leopard_init(void)
270 gpio_request(2, "usb_id_toggle"); 263 gpio_request(2, "usb_id_toggle");
271 gpio_direction_output(2, USB_ID_VALUE); 264 gpio_direction_output(2, USB_ID_VALUE);
272 /* irlml6401 switches over 1A in under 8 msec */ 265 /* irlml6401 switches over 1A in under 8 msec */
273 setup_usb(500, 8); 266 davinci_setup_usb(1000, 8);
274 267
275 davinci_setup_mmc(0, &dm355leopard_mmc_config); 268 davinci_setup_mmc(0, &dm355leopard_mmc_config);
276 davinci_setup_mmc(1, &dm355leopard_mmc_config); 269 davinci_setup_mmc(1, &dm355leopard_mmc_config);
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 52dd8046b305..df4ab2105869 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -13,9 +13,8 @@
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/init.h> 16#include <linux/init.h>
18#include <linux/dma-mapping.h> 17#include <linux/err.h>
19#include <linux/i2c.h> 18#include <linux/i2c.h>
20#include <linux/io.h> 19#include <linux/io.h>
21#include <linux/clk.h> 20#include <linux/clk.h>
@@ -23,21 +22,25 @@
23#include <linux/leds.h> 22#include <linux/leds.h>
24#include <linux/mtd/mtd.h> 23#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h> 24#include <linux/mtd/partitions.h>
25#include <linux/slab.h>
26#include <linux/mtd/nand.h> 26#include <linux/mtd/nand.h>
27#include <asm/setup.h> 27#include <linux/input.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/eeprom.h>
30
28#include <asm/mach-types.h> 31#include <asm/mach-types.h>
29#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
30#include <asm/mach/map.h> 33
31#include <mach/mux.h> 34#include <mach/mux.h>
32#include <mach/hardware.h>
33#include <mach/dm365.h> 35#include <mach/dm365.h>
34#include <mach/psc.h>
35#include <mach/common.h> 36#include <mach/common.h>
36#include <mach/i2c.h> 37#include <mach/i2c.h>
37#include <mach/serial.h> 38#include <mach/serial.h>
38#include <mach/mmc.h> 39#include <mach/mmc.h>
39#include <mach/nand.h> 40#include <mach/nand.h>
41#include <mach/keyscan.h>
40 42
43#include <media/tvp514x.h>
41 44
42static inline int have_imager(void) 45static inline int have_imager(void)
43{ 46{
@@ -144,6 +147,7 @@ static struct davinci_nand_pdata davinci_nand_data = {
144 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 147 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
145 .ecc_mode = NAND_ECC_HW, 148 .ecc_mode = NAND_ECC_HW,
146 .options = NAND_USE_FLASH_BBT, 149 .options = NAND_USE_FLASH_BBT,
150 .ecc_bits = 4,
147}; 151};
148 152
149static struct resource davinci_nand_resources[] = { 153static struct resource davinci_nand_resources[] = {
@@ -176,11 +180,16 @@ static struct at24_platform_data eeprom_info = {
176 .context = (void *)0x7f00, 180 .context = (void *)0x7f00,
177}; 181};
178 182
183static struct snd_platform_data dm365_evm_snd_data;
184
179static struct i2c_board_info i2c_info[] = { 185static struct i2c_board_info i2c_info[] = {
180 { 186 {
181 I2C_BOARD_INFO("24c256", 0x50), 187 I2C_BOARD_INFO("24c256", 0x50),
182 .platform_data = &eeprom_info, 188 .platform_data = &eeprom_info,
183 }, 189 },
190 {
191 I2C_BOARD_INFO("tlv320aic3x", 0x18),
192 },
184}; 193};
185 194
186static struct davinci_i2c_platform_data i2c_pdata = { 195static struct davinci_i2c_platform_data i2c_pdata = {
@@ -188,6 +197,42 @@ static struct davinci_i2c_platform_data i2c_pdata = {
188 .bus_delay = 0 /* usec */, 197 .bus_delay = 0 /* usec */,
189}; 198};
190 199
200static int dm365evm_keyscan_enable(struct device *dev)
201{
202 return davinci_cfg_reg(DM365_KEYSCAN);
203}
204
205static unsigned short dm365evm_keymap[] = {
206 KEY_KP2,
207 KEY_LEFT,
208 KEY_EXIT,
209 KEY_DOWN,
210 KEY_ENTER,
211 KEY_UP,
212 KEY_KP1,
213 KEY_RIGHT,
214 KEY_MENU,
215 KEY_RECORD,
216 KEY_REWIND,
217 KEY_KPMINUS,
218 KEY_STOP,
219 KEY_FASTFORWARD,
220 KEY_KPPLUS,
221 KEY_PLAYPAUSE,
222 0
223};
224
225static struct davinci_ks_platform_data dm365evm_ks_data = {
226 .device_enable = dm365evm_keyscan_enable,
227 .keymap = dm365evm_keymap,
228 .keymapsize = ARRAY_SIZE(dm365evm_keymap),
229 .rep = 1,
230 /* Scan period = strobe + interval */
231 .strobe = 0x5,
232 .interval = 0x2,
233 .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4,
234};
235
191static int cpld_mmc_get_cd(int module) 236static int cpld_mmc_get_cd(int module)
192{ 237{
193 if (!cpld) 238 if (!cpld)
@@ -266,6 +311,73 @@ static void dm365evm_mmc_configure(void)
266 davinci_cfg_reg(DM365_SD1_DATA0); 311 davinci_cfg_reg(DM365_SD1_DATA0);
267} 312}
268 313
314static struct tvp514x_platform_data tvp5146_pdata = {
315 .clk_polarity = 0,
316 .hs_polarity = 1,
317 .vs_polarity = 1
318};
319
320#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
321/* Inputs available at the TVP5146 */
322static struct v4l2_input tvp5146_inputs[] = {
323 {
324 .index = 0,
325 .name = "Composite",
326 .type = V4L2_INPUT_TYPE_CAMERA,
327 .std = TVP514X_STD_ALL,
328 },
329 {
330 .index = 1,
331 .name = "S-Video",
332 .type = V4L2_INPUT_TYPE_CAMERA,
333 .std = TVP514X_STD_ALL,
334 },
335};
336
337/*
338 * this is the route info for connecting each input to decoder
339 * ouput that goes to vpfe. There is a one to one correspondence
340 * with tvp5146_inputs
341 */
342static struct vpfe_route tvp5146_routes[] = {
343 {
344 .input = INPUT_CVBS_VI2B,
345 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
346 },
347{
348 .input = INPUT_SVIDEO_VI2C_VI1C,
349 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
350 },
351};
352
353static struct vpfe_subdev_info vpfe_sub_devs[] = {
354 {
355 .name = "tvp5146",
356 .grp_id = 0,
357 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
358 .inputs = tvp5146_inputs,
359 .routes = tvp5146_routes,
360 .can_route = 1,
361 .ccdc_if_params = {
362 .if_type = VPFE_BT656,
363 .hdpol = VPFE_PINPOL_POSITIVE,
364 .vdpol = VPFE_PINPOL_POSITIVE,
365 },
366 .board_info = {
367 I2C_BOARD_INFO("tvp5146", 0x5d),
368 .platform_data = &tvp5146_pdata,
369 },
370 },
371};
372
373static struct vpfe_config vpfe_cfg = {
374 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
375 .sub_devs = vpfe_sub_devs,
376 .i2c_adapter_id = 1,
377 .card_name = "DM365 EVM",
378 .ccdc = "ISIF",
379};
380
269static void __init evm_init_i2c(void) 381static void __init evm_init_i2c(void)
270{ 382{
271 davinci_init_i2c(&i2c_pdata); 383 davinci_init_i2c(&i2c_pdata);
@@ -457,9 +569,29 @@ static struct davinci_uart_config uart_config __initdata = {
457 569
458static void __init dm365_evm_map_io(void) 570static void __init dm365_evm_map_io(void)
459{ 571{
572 /* setup input configuration for VPFE input devices */
573 dm365_set_vpfe_config(&vpfe_cfg);
460 dm365_init(); 574 dm365_init();
461} 575}
462 576
577static struct spi_eeprom at25640 = {
578 .byte_len = SZ_64K / 8,
579 .name = "at25640",
580 .page_size = 32,
581 .flags = EE_ADDR2,
582};
583
584static struct spi_board_info dm365_evm_spi_info[] __initconst = {
585 {
586 .modalias = "at25",
587 .platform_data = &at25640,
588 .max_speed_hz = 10 * 1000 * 1000,
589 .bus_num = 0,
590 .chip_select = 0,
591 .mode = SPI_MODE_0,
592 },
593};
594
463static __init void dm365_evm_init(void) 595static __init void dm365_evm_init(void)
464{ 596{
465 evm_init_i2c(); 597 evm_init_i2c();
@@ -472,6 +604,13 @@ static __init void dm365_evm_init(void)
472 604
473 /* maybe setup mmc1/etc ... _after_ mmc0 */ 605 /* maybe setup mmc1/etc ... _after_ mmc0 */
474 evm_init_cpld(); 606 evm_init_cpld();
607
608 dm365_init_asp(&dm365_evm_snd_data);
609 dm365_init_rtc();
610 dm365_init_ks(&dm365evm_ks_data);
611
612 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
613 ARRAY_SIZE(dm365_evm_spi_info));
475} 614}
476 615
477static __init void dm365_evm_irq_init(void) 616static __init void dm365_evm_irq_init(void)
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 1213a0087ad4..976e11b7fa4a 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -9,45 +9,34 @@
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/dma-mapping.h> 13#include <linux/dma-mapping.h>
15#include <linux/platform_device.h> 14#include <linux/platform_device.h>
16#include <linux/gpio.h> 15#include <linux/gpio.h>
17#include <linux/leds.h>
18#include <linux/memory.h>
19
20#include <linux/i2c.h> 16#include <linux/i2c.h>
21#include <linux/i2c/pcf857x.h> 17#include <linux/i2c/pcf857x.h>
22#include <linux/i2c/at24.h> 18#include <linux/i2c/at24.h>
23#include <linux/etherdevice.h>
24#include <linux/mtd/mtd.h> 19#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h> 20#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h> 21#include <linux/mtd/partitions.h>
27#include <linux/mtd/physmap.h> 22#include <linux/mtd/physmap.h>
28#include <linux/io.h>
29#include <linux/phy.h> 23#include <linux/phy.h>
30#include <linux/clk.h> 24#include <linux/clk.h>
31#include <linux/videodev2.h> 25#include <linux/videodev2.h>
32 26
33#include <media/tvp514x.h> 27#include <media/tvp514x.h>
34 28
35#include <asm/setup.h>
36#include <asm/mach-types.h> 29#include <asm/mach-types.h>
37
38#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/flash.h>
41 31
42#include <mach/dm644x.h> 32#include <mach/dm644x.h>
43#include <mach/common.h> 33#include <mach/common.h>
44#include <mach/i2c.h> 34#include <mach/i2c.h>
45#include <mach/serial.h> 35#include <mach/serial.h>
46#include <mach/mux.h> 36#include <mach/mux.h>
47#include <mach/psc.h>
48#include <mach/nand.h> 37#include <mach/nand.h>
49#include <mach/mmc.h> 38#include <mach/mmc.h>
50#include <mach/emac.h> 39#include <mach/usb.h>
51 40
52#define DM644X_EVM_PHY_MASK (0x2) 41#define DM644X_EVM_PHY_MASK (0x2)
53#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 42#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
@@ -258,6 +247,7 @@ static struct vpfe_subdev_info vpfe_sub_devs[] = {
258 247
259static struct vpfe_config vpfe_cfg = { 248static struct vpfe_config vpfe_cfg = {
260 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), 249 .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
250 .i2c_adapter_id = 1,
261 .sub_devs = vpfe_sub_devs, 251 .sub_devs = vpfe_sub_devs,
262 .card_name = "DM6446 EVM", 252 .card_name = "DM6446 EVM",
263 .ccdc = "DM6446 CCDC", 253 .ccdc = "DM6446 CCDC",
@@ -477,7 +467,7 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
477 /* irlml6401 switches over 1A, in under 8 msec; 467 /* irlml6401 switches over 1A, in under 8 msec;
478 * now it can be managed by nDRV_VBUS ... 468 * now it can be managed by nDRV_VBUS ...
479 */ 469 */
480 setup_usb(500, 8); 470 davinci_setup_usb(1000, 8);
481 471
482 return 0; 472 return 0;
483} 473}
@@ -639,6 +629,8 @@ static struct i2c_board_info __initdata i2c_info[] = {
639static struct davinci_i2c_platform_data i2c_pdata = { 629static struct davinci_i2c_platform_data i2c_pdata = {
640 .bus_freq = 20 /* kHz */, 630 .bus_freq = 20 /* kHz */,
641 .bus_delay = 100 /* usec */, 631 .bus_delay = 100 /* usec */,
632 .sda_pin = 44,
633 .scl_pin = 43,
642}; 634};
643 635
644static void __init evm_init_i2c(void) 636static void __init evm_init_i2c(void)
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 24e0e13b1492..5ba3cb2daaa0 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -17,38 +17,95 @@
17 **************************************************************************/ 17 **************************************************************************/
18 18
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h> 20#include <linux/init.h>
22#include <linux/fs.h>
23#include <linux/major.h>
24#include <linux/root_dev.h>
25#include <linux/dma-mapping.h>
26#include <linux/serial.h>
27#include <linux/serial_8250.h>
28#include <linux/leds.h> 21#include <linux/leds.h>
29#include <linux/gpio.h> 22#include <linux/gpio.h>
30#include <linux/io.h>
31#include <linux/platform_device.h> 23#include <linux/platform_device.h>
32#include <linux/i2c.h> 24#include <linux/i2c.h>
33#include <linux/i2c/at24.h> 25#include <linux/i2c/at24.h>
34#include <linux/i2c/pcf857x.h> 26#include <linux/i2c/pcf857x.h>
35#include <linux/etherdevice.h>
36 27
37#include <media/tvp514x.h> 28#include <media/tvp514x.h>
38 29
39#include <asm/setup.h> 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h>
33#include <linux/clk.h>
34
40#include <asm/mach-types.h> 35#include <asm/mach-types.h>
41#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
42#include <asm/mach/map.h>
43#include <asm/mach/flash.h>
44 37
45#include <mach/dm646x.h> 38#include <mach/dm646x.h>
46#include <mach/common.h> 39#include <mach/common.h>
47#include <mach/psc.h>
48#include <mach/serial.h> 40#include <mach/serial.h>
49#include <mach/i2c.h> 41#include <mach/i2c.h>
50#include <mach/mmc.h> 42#include <mach/nand.h>
51#include <mach/emac.h> 43#include <mach/clock.h>
44#include <mach/cdce949.h>
45
46#include "clock.h"
47
48#define NAND_BLOCK_SIZE SZ_128K
49
50/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
51 * and U-Boot environment this avoids dependency on any particular combination
52 * of UBL, U-Boot or flashing tools etc.
53 */
54static struct mtd_partition davinci_nand_partitions[] = {
55 {
56 /* UBL, U-Boot with environment */
57 .name = "bootloader",
58 .offset = MTDPART_OFS_APPEND,
59 .size = 16 * NAND_BLOCK_SIZE,
60 .mask_flags = MTD_WRITEABLE, /* force read-only */
61 }, {
62 .name = "kernel",
63 .offset = MTDPART_OFS_APPEND,
64 .size = SZ_4M,
65 .mask_flags = 0,
66 }, {
67 .name = "filesystem",
68 .offset = MTDPART_OFS_APPEND,
69 .size = MTDPART_SIZ_FULL,
70 .mask_flags = 0,
71 }
72};
73
74static struct davinci_nand_pdata davinci_nand_data = {
75 .mask_cle = 0x80000,
76 .mask_ale = 0x40000,
77 .parts = davinci_nand_partitions,
78 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
79 .ecc_mode = NAND_ECC_HW,
80 .options = 0,
81};
82
83#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
84#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
85
86static struct resource davinci_nand_resources[] = {
87 {
88 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
89 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
90 .flags = IORESOURCE_MEM,
91 }, {
92 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
93 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
94 .flags = IORESOURCE_MEM,
95 },
96};
97
98static struct platform_device davinci_nand_device = {
99 .name = "davinci_nand",
100 .id = 0,
101
102 .num_resources = ARRAY_SIZE(davinci_nand_resources),
103 .resource = davinci_nand_resources,
104
105 .dev = {
106 .platform_data = &davinci_nand_data,
107 },
108};
52 109
53#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 110#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
54 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) 111 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
@@ -61,37 +118,6 @@
61#define DM646X_EVM_ATA_RST BIT(0) 118#define DM646X_EVM_ATA_RST BIT(0)
62#define DM646X_EVM_ATA_PWD BIT(1) 119#define DM646X_EVM_ATA_PWD BIT(1)
63 120
64#define DM646X_EVM_PHY_MASK (0x2)
65#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
66
67#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
68#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
69#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
70#define VCH2CLK_SYSCLK8 (BIT(9))
71#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
72#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
73#define VCH3CLK_SYSCLK8 (BIT(13))
74#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
75
76#define VIDCH2CLK (BIT(10))
77#define VIDCH3CLK (BIT(11))
78#define VIDCH1CLK (BIT(4))
79#define TVP7002_INPUT (BIT(4))
80#define TVP5147_INPUT (~BIT(4))
81#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
82#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
83#define TVP5147_CH0 "tvp514x-0"
84#define TVP5147_CH1 "tvp514x-1"
85
86static void __iomem *vpif_vidclkctl_reg;
87static void __iomem *vpif_vsclkdis_reg;
88/* spin lock for updating above registers */
89static spinlock_t vpif_reg_lock;
90
91static struct davinci_uart_config uart_config __initdata = {
92 .enabled_uarts = (1 << 0),
93};
94
95/* CPLD Register 0 Client: used for I/O Control */ 121/* CPLD Register 0 Client: used for I/O Control */
96static int cpld_reg0_probe(struct i2c_client *client, 122static int cpld_reg0_probe(struct i2c_client *client,
97 const struct i2c_device_id *id) 123 const struct i2c_device_id *id)
@@ -142,7 +168,7 @@ static struct gpio_led evm_leds[] = {
142 { .name = "DS4", .active_low = 1, }, 168 { .name = "DS4", .active_low = 1, },
143}; 169};
144 170
145static __initconst struct gpio_led_platform_data evm_led_data = { 171static const struct gpio_led_platform_data evm_led_data = {
146 .num_leds = ARRAY_SIZE(evm_leds), 172 .num_leds = ARRAY_SIZE(evm_leds),
147 .leds = evm_leds, 173 .leds = evm_leds,
148}; 174};
@@ -365,6 +391,9 @@ static struct i2c_board_info __initdata i2c_info[] = {
365 { 391 {
366 I2C_BOARD_INFO("cpld_video", 0x3b), 392 I2C_BOARD_INFO("cpld_video", 0x3b),
367 }, 393 },
394 {
395 I2C_BOARD_INFO("cdce949", 0x6c),
396 },
368}; 397};
369 398
370static struct davinci_i2c_platform_data i2c_pdata = { 399static struct davinci_i2c_platform_data i2c_pdata = {
@@ -372,6 +401,30 @@ static struct davinci_i2c_platform_data i2c_pdata = {
372 .bus_delay = 0 /* usec */, 401 .bus_delay = 0 /* usec */,
373}; 402};
374 403
404#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
405#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
406#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
407#define VCH2CLK_SYSCLK8 (BIT(9))
408#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
409#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
410#define VCH3CLK_SYSCLK8 (BIT(13))
411#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
412
413#define VIDCH2CLK (BIT(10))
414#define VIDCH3CLK (BIT(11))
415#define VIDCH1CLK (BIT(4))
416#define TVP7002_INPUT (BIT(4))
417#define TVP5147_INPUT (~BIT(4))
418#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
419#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
420#define TVP5147_CH0 "tvp514x-0"
421#define TVP5147_CH1 "tvp514x-1"
422
423static void __iomem *vpif_vidclkctl_reg;
424static void __iomem *vpif_vsclkdis_reg;
425/* spin lock for updating above registers */
426static spinlock_t vpif_reg_lock;
427
375static int set_vpif_clock(int mux_mode, int hd) 428static int set_vpif_clock(int mux_mode, int hd)
376{ 429{
377 unsigned long flags; 430 unsigned long flags;
@@ -633,11 +686,44 @@ static void __init evm_init_i2c(void)
633 evm_init_video(); 686 evm_init_video();
634} 687}
635 688
689#define CDCE949_XIN_RATE 27000000
690
691/* CDCE949 support - "lpsc" field is overridden to work as clock number */
692static struct clk cdce_clk_in = {
693 .name = "cdce_xin",
694 .rate = CDCE949_XIN_RATE,
695};
696
697static struct clk_lookup cdce_clks[] = {
698 CLK(NULL, "xin", &cdce_clk_in),
699 CLK(NULL, NULL, NULL),
700};
701
702static void __init cdce_clk_init(void)
703{
704 struct clk_lookup *c;
705 struct clk *clk;
706
707 for (c = cdce_clks; c->clk; c++) {
708 clk = c->clk;
709 clkdev_add(c);
710 clk_register(clk);
711 }
712}
713
636static void __init davinci_map_io(void) 714static void __init davinci_map_io(void)
637{ 715{
638 dm646x_init(); 716 dm646x_init();
717 cdce_clk_init();
639} 718}
640 719
720static struct davinci_uart_config uart_config __initdata = {
721 .enabled_uarts = (1 << 0),
722};
723
724#define DM646X_EVM_PHY_MASK (0x2)
725#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
726
641static __init void evm_init(void) 727static __init void evm_init(void)
642{ 728{
643 struct davinci_soc_info *soc_info = &davinci_soc_info; 729 struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -647,6 +733,8 @@ static __init void evm_init(void)
647 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); 733 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
648 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); 734 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
649 735
736 platform_device_register(&davinci_nand_device);
737
650 if (HAS_ATA) 738 if (HAS_ATA)
651 dm646x_init_ide(); 739 dm646x_init_ide();
652 740
@@ -659,6 +747,17 @@ static __init void davinci_dm646x_evm_irq_init(void)
659 davinci_irq_init(); 747 davinci_irq_init();
660} 748}
661 749
750#define DM646X_EVM_REF_FREQ 27000000
751#define DM6467T_EVM_REF_FREQ 33000000
752
753void __init dm646x_board_setup_refclk(struct clk *clk)
754{
755 if (machine_is_davinci_dm6467tevm())
756 clk->rate = DM6467T_EVM_REF_FREQ;
757 else
758 clk->rate = DM646X_EVM_REF_FREQ;
759}
760
662MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") 761MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
663 .phys_io = IO_PHYS, 762 .phys_io = IO_PHYS,
664 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 763 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
@@ -669,3 +768,13 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
669 .init_machine = evm_init, 768 .init_machine = evm_init,
670MACHINE_END 769MACHINE_END
671 770
771MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
772 .phys_io = IO_PHYS,
773 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
774 .boot_params = (0x80000100),
775 .map_io = davinci_map_io,
776 .init_irq = davinci_dm646x_evm_irq_init,
777 .timer = &davinci_timer,
778 .init_machine = evm_init,
779MACHINE_END
780
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
new file mode 100644
index 000000000000..bd9ca079b69d
--- /dev/null
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -0,0 +1,323 @@
1/*
2 * Neuros Technologies OSD2 board support
3 *
4 * Modified from original 644X-EVM board support.
5 * 2008 (c) Neuros Technology, LLC.
6 * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
7 * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
8 *
9 * The Neuros OSD 2.0 is the hardware component of the Neuros Open
10 * Internet Television Platform. Hardware is very close to TI
11 * DM644X-EVM board. It has:
12 * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
13 * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
14 * Additionaly realtime clock, IR remote control receiver,
15 * IR Blaster based on MSP430 (firmware although is different
16 * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
17 * with PATA interface, two muxed red-green leds.
18 *
19 * For more information please refer to
20 * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
21 *
22 * This file is licensed under the terms of the GNU General Public
23 * License version 2. This program is licensed "as is" without any
24 * warranty of any kind, whether express or implied.
25 */
26#include <linux/platform_device.h>
27#include <linux/gpio.h>
28#include <linux/mtd/partitions.h>
29
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
33#include <mach/dm644x.h>
34#include <mach/i2c.h>
35#include <mach/serial.h>
36#include <mach/mux.h>
37#include <mach/nand.h>
38#include <mach/mmc.h>
39#include <mach/usb.h>
40
41#define NEUROS_OSD2_PHY_MASK 0x2
42#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
43
44#define DAVINCI_CFC_ATA_BASE 0x01C66000
45
46#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
47#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
48
49#define LXT971_PHY_ID 0x001378e2
50#define LXT971_PHY_MASK 0xfffffff0
51
52#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
53#define NTOSD2_MSP430_I2C_ADDR 0x59
54#define NTOSD2_MSP430_IRQ 2
55
56/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
57 * 2048 blocks in the device, 64 pages per block, 2048 bytes per
58 * page.
59 */
60
61#define NAND_BLOCK_SIZE SZ_128K
62
63struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
64 {
65 /* UBL (a few copies) plus U-Boot */
66 .name = "bootloader",
67 .offset = 0,
68 .size = 15 * NAND_BLOCK_SIZE,
69 .mask_flags = MTD_WRITEABLE, /* force read-only */
70 }, {
71 /* U-Boot environment */
72 .name = "params",
73 .offset = MTDPART_OFS_APPEND,
74 .size = 1 * NAND_BLOCK_SIZE,
75 .mask_flags = 0,
76 }, {
77 /* Kernel */
78 .name = "kernel",
79 .offset = MTDPART_OFS_APPEND,
80 .size = SZ_4M,
81 .mask_flags = 0,
82 }, {
83 /* File System */
84 .name = "filesystem",
85 .offset = MTDPART_OFS_APPEND,
86 .size = MTDPART_SIZ_FULL,
87 .mask_flags = 0,
88 }
89 /* A few blocks at end hold a flash Bad Block Table. */
90};
91
92static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
93 .parts = davinci_ntosd2_nandflash_partition,
94 .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
95 .ecc_mode = NAND_ECC_HW,
96 .options = NAND_USE_FLASH_BBT,
97};
98
99static struct resource davinci_ntosd2_nandflash_resource[] = {
100 {
101 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
102 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
103 .flags = IORESOURCE_MEM,
104 }, {
105 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
106 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
107 .flags = IORESOURCE_MEM,
108 },
109};
110
111static struct platform_device davinci_ntosd2_nandflash_device = {
112 .name = "davinci_nand",
113 .id = 0,
114 .dev = {
115 .platform_data = &davinci_ntosd2_nandflash_data,
116 },
117 .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
118 .resource = davinci_ntosd2_nandflash_resource,
119};
120
121static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
122
123static struct platform_device davinci_fb_device = {
124 .name = "davincifb",
125 .id = -1,
126 .dev = {
127 .dma_mask = &davinci_fb_dma_mask,
128 .coherent_dma_mask = DMA_BIT_MASK(32),
129 },
130 .num_resources = 0,
131};
132
133static struct resource ide_resources[] = {
134 {
135 .start = DAVINCI_CFC_ATA_BASE,
136 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
137 .flags = IORESOURCE_MEM,
138 },
139 {
140 .start = IRQ_IDE,
141 .end = IRQ_IDE,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static u64 ide_dma_mask = DMA_BIT_MASK(32);
147
148static struct platform_device ide_dev = {
149 .name = "palm_bk3710",
150 .id = -1,
151 .resource = ide_resources,
152 .num_resources = ARRAY_SIZE(ide_resources),
153 .dev = {
154 .dma_mask = &ide_dma_mask,
155 .coherent_dma_mask = DMA_BIT_MASK(32),
156 },
157};
158
159static struct snd_platform_data dm644x_ntosd2_snd_data;
160
161static struct gpio_led ntosd2_leds[] = {
162 { .name = "led1_green", .gpio = GPIO(10), },
163 { .name = "led1_red", .gpio = GPIO(11), },
164 { .name = "led2_green", .gpio = GPIO(12), },
165 { .name = "led2_red", .gpio = GPIO(13), },
166};
167
168static struct gpio_led_platform_data ntosd2_leds_data = {
169 .num_leds = ARRAY_SIZE(ntosd2_leds),
170 .leds = ntosd2_leds,
171};
172
173static struct platform_device ntosd2_leds_dev = {
174 .name = "leds-gpio",
175 .id = -1,
176 .dev = {
177 .platform_data = &ntosd2_leds_data,
178 },
179};
180
181
182static struct platform_device *davinci_ntosd2_devices[] __initdata = {
183 &davinci_fb_device,
184 &ntosd2_leds_dev,
185};
186
187static struct davinci_uart_config uart_config __initdata = {
188 .enabled_uarts = (1 << 0),
189};
190
191static void __init davinci_ntosd2_map_io(void)
192{
193 dm644x_init();
194}
195
196/*
197 I2C initialization
198*/
199static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
200 .bus_freq = 20 /* kHz */,
201 .bus_delay = 100 /* usec */,
202};
203
204static struct i2c_board_info __initdata ntosd2_i2c_info[] = {
205};
206
207static int ntosd2_init_i2c(void)
208{
209 int status;
210
211 davinci_init_i2c(&ntosd2_i2c_pdata);
212 status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
213 if (status == 0) {
214 status = gpio_direction_input(NTOSD2_MSP430_IRQ);
215 if (status == 0) {
216 status = gpio_to_irq(NTOSD2_MSP430_IRQ);
217 if (status > 0) {
218 ntosd2_i2c_info[0].irq = status;
219 i2c_register_board_info(1,
220 ntosd2_i2c_info,
221 ARRAY_SIZE(ntosd2_i2c_info));
222 }
223 }
224 }
225 return status;
226}
227
228static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
229 .wires = 4,
230 .version = MMC_CTLR_VERSION_1
231};
232
233
234#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
235 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
236#define HAS_ATA 1
237#else
238#define HAS_ATA 0
239#endif
240
241#if defined(CONFIG_MTD_NAND_DAVINCI) || \
242 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
243#define HAS_NAND 1
244#else
245#define HAS_NAND 0
246#endif
247
248static __init void davinci_ntosd2_init(void)
249{
250 struct clk *aemif_clk;
251 struct davinci_soc_info *soc_info = &davinci_soc_info;
252 int status;
253
254 aemif_clk = clk_get(NULL, "aemif");
255 clk_enable(aemif_clk);
256
257 if (HAS_ATA) {
258 if (HAS_NAND)
259 pr_warning("WARNING: both IDE and Flash are "
260 "enabled, but they share AEMIF pins.\n"
261 "\tDisable IDE for NAND/NOR support.\n");
262 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
263 davinci_cfg_reg(DM644X_ATAEN);
264 davinci_cfg_reg(DM644X_HDIREN);
265 platform_device_register(&ide_dev);
266 } else if (HAS_NAND) {
267 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
268 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
269
270 /* only one device will be jumpered and detected */
271 if (HAS_NAND)
272 platform_device_register(
273 &davinci_ntosd2_nandflash_device);
274 }
275
276 platform_add_devices(davinci_ntosd2_devices,
277 ARRAY_SIZE(davinci_ntosd2_devices));
278
279 /* Initialize I2C interface specific for this board */
280 status = ntosd2_init_i2c();
281 if (status < 0)
282 pr_warning("davinci_ntosd2_init: msp430 irq setup failed:"
283 " %d\n", status);
284
285 davinci_serial_init(&uart_config);
286 dm644x_init_asp(&dm644x_ntosd2_snd_data);
287
288 soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
289 soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
290
291 davinci_setup_usb(1000, 8);
292 /*
293 * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
294 * The AEAWx are five new AEAW pins that can be muxed by separately.
295 * They are a bitmask for GPIO management. According TI
296 * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
297 * gpio(10,11,12,13) for leds any combination of bits works except
298 * four last. So we are to reset all five.
299 */
300 davinci_cfg_reg(DM644X_AEAW0);
301 davinci_cfg_reg(DM644X_AEAW1);
302 davinci_cfg_reg(DM644X_AEAW2);
303 davinci_cfg_reg(DM644X_AEAW3);
304 davinci_cfg_reg(DM644X_AEAW4);
305
306 davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
307}
308
309static __init void davinci_ntosd2_irq_init(void)
310{
311 davinci_irq_init();
312}
313
314MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
315 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
316 .phys_io = IO_PHYS,
317 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
318 .boot_params = (DAVINCI_DDR_BASE + 0x100),
319 .map_io = davinci_ntosd2_map_io,
320 .init_irq = davinci_ntosd2_irq_init,
321 .timer = &davinci_timer,
322 .init_machine = davinci_ntosd2_init,
323MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 7acdfd8ac071..08d373bfcc8a 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -23,35 +23,24 @@
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */ 24 */
25 25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/init.h> 26#include <linux/init.h>
29#include <linux/dma-mapping.h>
30#include <linux/platform_device.h> 27#include <linux/platform_device.h>
31#include <linux/gpio.h>
32
33#include <linux/i2c.h> 28#include <linux/i2c.h>
34#include <linux/i2c/at24.h> 29#include <linux/i2c/at24.h>
35#include <linux/etherdevice.h>
36#include <linux/mtd/mtd.h> 30#include <linux/mtd/mtd.h>
37#include <linux/mtd/nand.h> 31#include <linux/mtd/nand.h>
38#include <linux/mtd/partitions.h> 32#include <linux/mtd/partitions.h>
39#include <linux/mtd/physmap.h>
40#include <linux/io.h>
41 33
42#include <asm/setup.h>
43#include <asm/mach-types.h> 34#include <asm/mach-types.h>
44
45#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
46#include <asm/mach/map.h>
47#include <asm/mach/flash.h> 36#include <asm/mach/flash.h>
48 37
49#include <mach/dm644x.h> 38#include <mach/dm644x.h>
50#include <mach/common.h> 39#include <mach/common.h>
51#include <mach/i2c.h> 40#include <mach/i2c.h>
52#include <mach/serial.h> 41#include <mach/serial.h>
53#include <mach/psc.h>
54#include <mach/mux.h> 42#include <mach/mux.h>
43#include <mach/usb.h>
55 44
56#define SFFSDR_PHY_MASK (0x2) 45#define SFFSDR_PHY_MASK (0x2)
57#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ 46#define SFFSDR_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
@@ -107,11 +96,6 @@ static struct platform_device davinci_sffsdr_nandflash_device = {
107 .resource = davinci_sffsdr_nandflash_resource, 96 .resource = davinci_sffsdr_nandflash_resource,
108}; 97};
109 98
110static struct emac_platform_data sffsdr_emac_pdata = {
111 .phy_mask = SFFSDR_PHY_MASK,
112 .mdio_max_freq = SFFSDR_MDIO_FREQUENCY,
113};
114
115static struct at24_platform_data eeprom_info = { 99static struct at24_platform_data eeprom_info = {
116 .byte_len = (64*1024) / 8, 100 .byte_len = (64*1024) / 8,
117 .page_size = 32, 101 .page_size = 32,
@@ -164,7 +148,7 @@ static __init void davinci_sffsdr_init(void)
164 davinci_serial_init(&uart_config); 148 davinci_serial_init(&uart_config);
165 soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK; 149 soc_info->emac_pdata->phy_mask = SFFSDR_PHY_MASK;
166 soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY; 150 soc_info->emac_pdata->mdio_max_freq = SFFSDR_MDIO_FREQUENCY;
167 setup_usb(0, 0); /* We support only peripheral mode. */ 151 davinci_setup_usb(0, 0); /* We support only peripheral mode. */
168 152
169 /* mux VLYNQ pins */ 153 /* mux VLYNQ pins */
170 davinci_cfg_reg(DM644X_VLYNQEN); 154 davinci_cfg_reg(DM644X_VLYNQEN);
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
new file mode 100644
index 000000000000..aec375690543
--- /dev/null
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -0,0 +1,293 @@
1/*
2 * TI CDCE949 clock synthesizer driver
3 *
4 * Note: This implementation assumes an input of 27MHz to the CDCE.
5 * This is by no means constrained by CDCE hardware although the datasheet
6 * does use this as an example for all illustrations and more importantly:
7 * that is the crystal input on boards it is currently used on.
8 *
9 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20
21#include <mach/clock.h>
22
23#include "clock.h"
24
25static struct i2c_client *cdce_i2c_client;
26static DEFINE_MUTEX(cdce_mutex);
27
28/* CDCE register descriptor */
29struct cdce_reg {
30 u8 addr;
31 u8 val;
32};
33
34/* Per-Output (Y1, Y2 etc.) frequency descriptor */
35struct cdce_freq {
36 /* Frequency in KHz */
37 unsigned long frequency;
38 /*
39 * List of registers to program to obtain a particular frequency.
40 * 0x0 in register address and value is the end of list marker.
41 */
42 struct cdce_reg *reglist;
43};
44
45#define CDCE_FREQ_TABLE_ENTRY(line, out) \
46{ \
47 .reglist = cdce_y ##line## _ ##out, \
48 .frequency = out, \
49}
50
51/* List of CDCE outputs */
52struct cdce_output {
53 /* List of frequencies on this output */
54 struct cdce_freq *freq_table;
55 /* Number of possible frequencies */
56 int size;
57};
58
59/*
60 * Finding out the values to program into CDCE949 registers for a particular
61 * frequency output is not a simple calculation. Have a look at the datasheet
62 * for the details. There is desktop software available to help users with
63 * the calculations. Here, we just depend on the output of that software
64 * (or hand calculations) instead trying to runtime calculate the register
65 * values and inflicting misery on ourselves.
66 */
67static struct cdce_reg cdce_y1_148500[] = {
68 { 0x13, 0x00 },
69 /* program PLL1_0 multiplier */
70 { 0x18, 0xaf },
71 { 0x19, 0x50 },
72 { 0x1a, 0x02 },
73 { 0x1b, 0xc9 },
74 /* program PLL1_11 multiplier */
75 { 0x1c, 0x00 },
76 { 0x1d, 0x40 },
77 { 0x1e, 0x02 },
78 { 0x1f, 0xc9 },
79 /* output state selection */
80 { 0x15, 0x00 },
81 { 0x14, 0xef },
82 /* switch MUX to PLL1 output */
83 { 0x14, 0x6f },
84 { 0x16, 0x06 },
85 /* set P2DIV divider, P3DIV and input crystal */
86 { 0x17, 0x06 },
87 { 0x01, 0x00 },
88 { 0x05, 0x48 },
89 { 0x02, 0x80 },
90 /* enable and disable PLL */
91 { 0x02, 0xbc },
92 { 0x03, 0x01 },
93 { },
94};
95
96static struct cdce_reg cdce_y1_74250[] = {
97 { 0x13, 0x00 },
98 { 0x18, 0xaf },
99 { 0x19, 0x50 },
100 { 0x1a, 0x02 },
101 { 0x1b, 0xc9 },
102 { 0x1c, 0x00 },
103 { 0x1d, 0x40 },
104 { 0x1e, 0x02 },
105 { 0x1f, 0xc9 },
106 /* output state selection */
107 { 0x15, 0x00 },
108 { 0x14, 0xef },
109 /* switch MUX to PLL1 output */
110 { 0x14, 0x6f },
111 { 0x16, 0x06 },
112 /* set P2DIV divider, P3DIV and input crystal */
113 { 0x17, 0x06 },
114 { 0x01, 0x00 },
115 { 0x05, 0x48 },
116 { 0x02, 0x80 },
117 /* enable and disable PLL */
118 { 0x02, 0xbc },
119 { 0x03, 0x02 },
120 { },
121};
122
123static struct cdce_reg cdce_y1_27000[] = {
124 { 0x13, 0x00 },
125 { 0x18, 0x00 },
126 { 0x19, 0x40 },
127 { 0x1a, 0x02 },
128 { 0x1b, 0x08 },
129 { 0x1c, 0x00 },
130 { 0x1d, 0x40 },
131 { 0x1e, 0x02 },
132 { 0x1f, 0x08 },
133 { 0x15, 0x02 },
134 { 0x14, 0xed },
135 { 0x16, 0x01 },
136 { 0x17, 0x01 },
137 { 0x01, 0x00 },
138 { 0x05, 0x50 },
139 { 0x02, 0xb4 },
140 { 0x03, 0x01 },
141 { },
142};
143
144static struct cdce_freq cdce_y1_freqs[] = {
145 CDCE_FREQ_TABLE_ENTRY(1, 148500),
146 CDCE_FREQ_TABLE_ENTRY(1, 74250),
147 CDCE_FREQ_TABLE_ENTRY(1, 27000),
148};
149
150static struct cdce_reg cdce_y5_13500[] = {
151 { 0x27, 0x08 },
152 { 0x28, 0x00 },
153 { 0x29, 0x40 },
154 { 0x2a, 0x02 },
155 { 0x2b, 0x08 },
156 { 0x24, 0x6f },
157 { },
158};
159
160static struct cdce_reg cdce_y5_16875[] = {
161 { 0x27, 0x08 },
162 { 0x28, 0x9f },
163 { 0x29, 0xb0 },
164 { 0x2a, 0x02 },
165 { 0x2b, 0x89 },
166 { 0x24, 0x6f },
167 { },
168};
169
170static struct cdce_reg cdce_y5_27000[] = {
171 { 0x27, 0x04 },
172 { 0x28, 0x00 },
173 { 0x29, 0x40 },
174 { 0x2a, 0x02 },
175 { 0x2b, 0x08 },
176 { 0x24, 0x6f },
177 { },
178};
179static struct cdce_reg cdce_y5_54000[] = {
180 { 0x27, 0x04 },
181 { 0x28, 0xff },
182 { 0x29, 0x80 },
183 { 0x2a, 0x02 },
184 { 0x2b, 0x07 },
185 { 0x24, 0x6f },
186 { },
187};
188
189static struct cdce_reg cdce_y5_81000[] = {
190 { 0x27, 0x02 },
191 { 0x28, 0xbf },
192 { 0x29, 0xa0 },
193 { 0x2a, 0x03 },
194 { 0x2b, 0x0a },
195 { 0x24, 0x6f },
196 { },
197};
198
199static struct cdce_freq cdce_y5_freqs[] = {
200 CDCE_FREQ_TABLE_ENTRY(5, 13500),
201 CDCE_FREQ_TABLE_ENTRY(5, 16875),
202 CDCE_FREQ_TABLE_ENTRY(5, 27000),
203 CDCE_FREQ_TABLE_ENTRY(5, 54000),
204 CDCE_FREQ_TABLE_ENTRY(5, 81000),
205};
206
207
208static struct cdce_output output_list[] = {
209 [1] = { cdce_y1_freqs, ARRAY_SIZE(cdce_y1_freqs) },
210 [5] = { cdce_y5_freqs, ARRAY_SIZE(cdce_y5_freqs) },
211};
212
213int cdce_set_rate(struct clk *clk, unsigned long rate)
214{
215 int i, ret = 0;
216 struct cdce_freq *freq_table = output_list[clk->lpsc].freq_table;
217 struct cdce_reg *regs = NULL;
218
219 if (!cdce_i2c_client)
220 return -ENODEV;
221
222 if (!freq_table)
223 return -EINVAL;
224
225 for (i = 0; i < output_list[clk->lpsc].size; i++) {
226 if (freq_table[i].frequency == rate / 1000) {
227 regs = freq_table[i].reglist;
228 break;
229 }
230 }
231
232 if (!regs)
233 return -EINVAL;
234
235 mutex_lock(&cdce_mutex);
236 for (i = 0; regs[i].addr; i++) {
237 ret = i2c_smbus_write_byte_data(cdce_i2c_client,
238 regs[i].addr | 0x80, regs[i].val);
239 if (ret)
240 break;
241 }
242 mutex_unlock(&cdce_mutex);
243
244 if (!ret)
245 clk->rate = rate;
246
247 return ret;
248}
249
250static int cdce_probe(struct i2c_client *client,
251 const struct i2c_device_id *id)
252{
253 cdce_i2c_client = client;
254 return 0;
255}
256
257static int __devexit cdce_remove(struct i2c_client *client)
258{
259 cdce_i2c_client = NULL;
260 return 0;
261}
262
263static const struct i2c_device_id cdce_id[] = {
264 {"cdce949", 0},
265 {},
266};
267MODULE_DEVICE_TABLE(i2c, cdce_id);
268
269static struct i2c_driver cdce_driver = {
270 .driver = {
271 .owner = THIS_MODULE,
272 .name = "cdce949",
273 },
274 .probe = cdce_probe,
275 .remove = __devexit_p(cdce_remove),
276 .id_table = cdce_id,
277};
278
279static int __init cdce_init(void)
280{
281 return i2c_add_driver(&cdce_driver);
282}
283subsys_initcall(cdce_init);
284
285static void __exit cdce_exit(void)
286{
287 i2c_del_driver(&cdce_driver);
288}
289module_exit(cdce_exit);
290
291MODULE_AUTHOR("Texas Instruments");
292MODULE_DESCRIPTION("CDCE949 clock synthesizer driver");
293MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 83d54d50b5ea..bf6218ee94e1 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -17,8 +17,8 @@
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/err.h> 18#include <linux/err.h>
19#include <linux/mutex.h> 19#include <linux/mutex.h>
20#include <linux/platform_device.h>
21#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/delay.h>
22 22
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24 24
@@ -42,17 +42,16 @@ static void __clk_enable(struct clk *clk)
42 if (clk->parent) 42 if (clk->parent)
43 __clk_enable(clk->parent); 43 __clk_enable(clk->parent);
44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC)) 44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
45 davinci_psc_config(psc_domain(clk), clk->psc_ctlr, 45 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 1);
46 clk->lpsc, 1);
47} 46}
48 47
49static void __clk_disable(struct clk *clk) 48static void __clk_disable(struct clk *clk)
50{ 49{
51 if (WARN_ON(clk->usecount == 0)) 50 if (WARN_ON(clk->usecount == 0))
52 return; 51 return;
53 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) 52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
54 davinci_psc_config(psc_domain(clk), clk->psc_ctlr, 53 (clk->flags & CLK_PSC))
55 clk->lpsc, 0); 54 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
56 if (clk->parent) 55 if (clk->parent)
57 __clk_disable(clk->parent); 56 __clk_disable(clk->parent);
58} 57}
@@ -99,20 +98,75 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
99 if (clk == NULL || IS_ERR(clk)) 98 if (clk == NULL || IS_ERR(clk))
100 return -EINVAL; 99 return -EINVAL;
101 100
101 if (clk->round_rate)
102 return clk->round_rate(clk, rate);
103
102 return clk->rate; 104 return clk->rate;
103} 105}
104EXPORT_SYMBOL(clk_round_rate); 106EXPORT_SYMBOL(clk_round_rate);
105 107
108/* Propagate rate to children */
109static void propagate_rate(struct clk *root)
110{
111 struct clk *clk;
112
113 list_for_each_entry(clk, &root->children, childnode) {
114 if (clk->recalc)
115 clk->rate = clk->recalc(clk);
116 propagate_rate(clk);
117 }
118}
119
106int clk_set_rate(struct clk *clk, unsigned long rate) 120int clk_set_rate(struct clk *clk, unsigned long rate)
107{ 121{
122 unsigned long flags;
123 int ret = -EINVAL;
124
108 if (clk == NULL || IS_ERR(clk)) 125 if (clk == NULL || IS_ERR(clk))
109 return -EINVAL; 126 return ret;
127
128 if (clk->set_rate)
129 ret = clk->set_rate(clk, rate);
130
131 spin_lock_irqsave(&clockfw_lock, flags);
132 if (ret == 0) {
133 if (clk->recalc)
134 clk->rate = clk->recalc(clk);
135 propagate_rate(clk);
136 }
137 spin_unlock_irqrestore(&clockfw_lock, flags);
110 138
111 /* changing the clk rate is not supported */ 139 return ret;
112 return -EINVAL;
113} 140}
114EXPORT_SYMBOL(clk_set_rate); 141EXPORT_SYMBOL(clk_set_rate);
115 142
143int clk_set_parent(struct clk *clk, struct clk *parent)
144{
145 unsigned long flags;
146
147 if (clk == NULL || IS_ERR(clk))
148 return -EINVAL;
149
150 /* Cannot change parent on enabled clock */
151 if (WARN_ON(clk->usecount))
152 return -EINVAL;
153
154 mutex_lock(&clocks_mutex);
155 clk->parent = parent;
156 list_del_init(&clk->childnode);
157 list_add(&clk->childnode, &clk->parent->children);
158 mutex_unlock(&clocks_mutex);
159
160 spin_lock_irqsave(&clockfw_lock, flags);
161 if (clk->recalc)
162 clk->rate = clk->recalc(clk);
163 propagate_rate(clk);
164 spin_unlock_irqrestore(&clockfw_lock, flags);
165
166 return 0;
167}
168EXPORT_SYMBOL(clk_set_parent);
169
116int clk_register(struct clk *clk) 170int clk_register(struct clk *clk)
117{ 171{
118 if (clk == NULL || IS_ERR(clk)) 172 if (clk == NULL || IS_ERR(clk))
@@ -123,16 +177,24 @@ int clk_register(struct clk *clk)
123 clk->name, clk->parent->name)) 177 clk->name, clk->parent->name))
124 return -EINVAL; 178 return -EINVAL;
125 179
180 INIT_LIST_HEAD(&clk->children);
181
126 mutex_lock(&clocks_mutex); 182 mutex_lock(&clocks_mutex);
127 list_add_tail(&clk->node, &clocks); 183 list_add_tail(&clk->node, &clocks);
184 if (clk->parent)
185 list_add_tail(&clk->childnode, &clk->parent->children);
128 mutex_unlock(&clocks_mutex); 186 mutex_unlock(&clocks_mutex);
129 187
130 /* If rate is already set, use it */ 188 /* If rate is already set, use it */
131 if (clk->rate) 189 if (clk->rate)
132 return 0; 190 return 0;
133 191
192 /* Else, see if there is a way to calculate it */
193 if (clk->recalc)
194 clk->rate = clk->recalc(clk);
195
134 /* Otherwise, default to parent rate */ 196 /* Otherwise, default to parent rate */
135 if (clk->parent) 197 else if (clk->parent)
136 clk->rate = clk->parent->rate; 198 clk->rate = clk->parent->rate;
137 199
138 return 0; 200 return 0;
@@ -146,6 +208,7 @@ void clk_unregister(struct clk *clk)
146 208
147 mutex_lock(&clocks_mutex); 209 mutex_lock(&clocks_mutex);
148 list_del(&clk->node); 210 list_del(&clk->node);
211 list_del(&clk->childnode);
149 mutex_unlock(&clocks_mutex); 212 mutex_unlock(&clocks_mutex);
150} 213}
151EXPORT_SYMBOL(clk_unregister); 214EXPORT_SYMBOL(clk_unregister);
@@ -166,11 +229,11 @@ static int __init clk_disable_unused(void)
166 continue; 229 continue;
167 230
168 /* ignore if in Disabled or SwRstDisable states */ 231 /* ignore if in Disabled or SwRstDisable states */
169 if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc)) 232 if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
170 continue; 233 continue;
171 234
172 pr_info("Clocks: disable unused %s\n", ck->name); 235 pr_info("Clocks: disable unused %s\n", ck->name);
173 davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0); 236 davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc, 0);
174 } 237 }
175 spin_unlock_irq(&clockfw_lock); 238 spin_unlock_irq(&clockfw_lock);
176 239
@@ -179,50 +242,62 @@ static int __init clk_disable_unused(void)
179late_initcall(clk_disable_unused); 242late_initcall(clk_disable_unused);
180#endif 243#endif
181 244
182static void clk_sysclk_recalc(struct clk *clk) 245static unsigned long clk_sysclk_recalc(struct clk *clk)
183{ 246{
184 u32 v, plldiv; 247 u32 v, plldiv;
185 struct pll_data *pll; 248 struct pll_data *pll;
249 unsigned long rate = clk->rate;
186 250
187 /* If this is the PLL base clock, no more calculations needed */ 251 /* If this is the PLL base clock, no more calculations needed */
188 if (clk->pll_data) 252 if (clk->pll_data)
189 return; 253 return rate;
190 254
191 if (WARN_ON(!clk->parent)) 255 if (WARN_ON(!clk->parent))
192 return; 256 return rate;
193 257
194 clk->rate = clk->parent->rate; 258 rate = clk->parent->rate;
195 259
196 /* Otherwise, the parent must be a PLL */ 260 /* Otherwise, the parent must be a PLL */
197 if (WARN_ON(!clk->parent->pll_data)) 261 if (WARN_ON(!clk->parent->pll_data))
198 return; 262 return rate;
199 263
200 pll = clk->parent->pll_data; 264 pll = clk->parent->pll_data;
201 265
202 /* If pre-PLL, source clock is before the multiplier and divider(s) */ 266 /* If pre-PLL, source clock is before the multiplier and divider(s) */
203 if (clk->flags & PRE_PLL) 267 if (clk->flags & PRE_PLL)
204 clk->rate = pll->input_rate; 268 rate = pll->input_rate;
205 269
206 if (!clk->div_reg) 270 if (!clk->div_reg)
207 return; 271 return rate;
208 272
209 v = __raw_readl(pll->base + clk->div_reg); 273 v = __raw_readl(pll->base + clk->div_reg);
210 if (v & PLLDIV_EN) { 274 if (v & PLLDIV_EN) {
211 plldiv = (v & PLLDIV_RATIO_MASK) + 1; 275 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
212 if (plldiv) 276 if (plldiv)
213 clk->rate /= plldiv; 277 rate /= plldiv;
214 } 278 }
279
280 return rate;
281}
282
283static unsigned long clk_leafclk_recalc(struct clk *clk)
284{
285 if (WARN_ON(!clk->parent))
286 return clk->rate;
287
288 return clk->parent->rate;
215} 289}
216 290
217static void __init clk_pll_init(struct clk *clk) 291static unsigned long clk_pllclk_recalc(struct clk *clk)
218{ 292{
219 u32 ctrl, mult = 1, prediv = 1, postdiv = 1; 293 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
220 u8 bypass; 294 u8 bypass;
221 struct pll_data *pll = clk->pll_data; 295 struct pll_data *pll = clk->pll_data;
296 unsigned long rate = clk->rate;
222 297
223 pll->base = IO_ADDRESS(pll->phys_base); 298 pll->base = IO_ADDRESS(pll->phys_base);
224 ctrl = __raw_readl(pll->base + PLLCTL); 299 ctrl = __raw_readl(pll->base + PLLCTL);
225 clk->rate = pll->input_rate = clk->parent->rate; 300 rate = pll->input_rate = clk->parent->rate;
226 301
227 if (ctrl & PLLCTL_PLLEN) { 302 if (ctrl & PLLCTL_PLLEN) {
228 bypass = 0; 303 bypass = 0;
@@ -255,9 +330,9 @@ static void __init clk_pll_init(struct clk *clk)
255 } 330 }
256 331
257 if (!bypass) { 332 if (!bypass) {
258 clk->rate /= prediv; 333 rate /= prediv;
259 clk->rate *= mult; 334 rate *= mult;
260 clk->rate /= postdiv; 335 rate /= postdiv;
261 } 336 }
262 337
263 pr_debug("PLL%d: input = %lu MHz [ ", 338 pr_debug("PLL%d: input = %lu MHz [ ",
@@ -270,56 +345,135 @@ static void __init clk_pll_init(struct clk *clk)
270 pr_debug("* %d ", mult); 345 pr_debug("* %d ", mult);
271 if (postdiv > 1) 346 if (postdiv > 1)
272 pr_debug("/ %d ", postdiv); 347 pr_debug("/ %d ", postdiv);
273 pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000); 348 pr_debug("] --> %lu MHz output.\n", rate / 1000000);
349
350 return rate;
274} 351}
275 352
276int __init davinci_clk_init(struct davinci_clk *clocks) 353/**
354 * davinci_set_pllrate - set the output rate of a given PLL.
355 *
356 * Note: Currently tested to work with OMAP-L138 only.
357 *
358 * @pll: pll whose rate needs to be changed.
359 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
360 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
361 * @postdiv: The post divider value. Passing 0 disables the post-divider.
362 */
363int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
364 unsigned int mult, unsigned int postdiv)
365{
366 u32 ctrl;
367 unsigned int locktime;
368 unsigned long flags;
369
370 if (pll->base == NULL)
371 return -EINVAL;
372
373 /*
374 * PLL lock time required per OMAP-L138 datasheet is
375 * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
376 * as 4 and OSCIN cycle as 25 MHz.
377 */
378 if (prediv) {
379 locktime = ((2000 * prediv) / 100);
380 prediv = (prediv - 1) | PLLDIV_EN;
381 } else {
382 locktime = PLL_LOCK_TIME;
383 }
384 if (postdiv)
385 postdiv = (postdiv - 1) | PLLDIV_EN;
386 if (mult)
387 mult = mult - 1;
388
389 /* Protect against simultaneous calls to PLL setting seqeunce */
390 spin_lock_irqsave(&clockfw_lock, flags);
391
392 ctrl = __raw_readl(pll->base + PLLCTL);
393
394 /* Switch the PLL to bypass mode */
395 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
396 __raw_writel(ctrl, pll->base + PLLCTL);
397
398 udelay(PLL_BYPASS_TIME);
399
400 /* Reset and enable PLL */
401 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
402 __raw_writel(ctrl, pll->base + PLLCTL);
403
404 if (pll->flags & PLL_HAS_PREDIV)
405 __raw_writel(prediv, pll->base + PREDIV);
406
407 __raw_writel(mult, pll->base + PLLM);
408
409 if (pll->flags & PLL_HAS_POSTDIV)
410 __raw_writel(postdiv, pll->base + POSTDIV);
411
412 udelay(PLL_RESET_TIME);
413
414 /* Bring PLL out of reset */
415 ctrl |= PLLCTL_PLLRST;
416 __raw_writel(ctrl, pll->base + PLLCTL);
417
418 udelay(locktime);
419
420 /* Remove PLL from bypass mode */
421 ctrl |= PLLCTL_PLLEN;
422 __raw_writel(ctrl, pll->base + PLLCTL);
423
424 spin_unlock_irqrestore(&clockfw_lock, flags);
425
426 return 0;
427}
428EXPORT_SYMBOL(davinci_set_pllrate);
429
430int __init davinci_clk_init(struct clk_lookup *clocks)
277 { 431 {
278 struct davinci_clk *c; 432 struct clk_lookup *c;
279 struct clk *clk; 433 struct clk *clk;
434 size_t num_clocks = 0;
435
436 for (c = clocks; c->clk; c++) {
437 clk = c->clk;
280 438
281 for (c = clocks; c->lk.clk; c++) { 439 if (!clk->recalc) {
282 clk = c->lk.clk;
283 440
284 if (clk->pll_data) 441 /* Check if clock is a PLL */
285 clk_pll_init(clk); 442 if (clk->pll_data)
443 clk->recalc = clk_pllclk_recalc;
286 444
287 /* Calculate rates for PLL-derived clocks */ 445 /* Else, if it is a PLL-derived clock */
288 else if (clk->flags & CLK_PLL) 446 else if (clk->flags & CLK_PLL)
289 clk_sysclk_recalc(clk); 447 clk->recalc = clk_sysclk_recalc;
448
449 /* Otherwise, it is a leaf clock (PSC clock) */
450 else if (clk->parent)
451 clk->recalc = clk_leafclk_recalc;
452 }
453
454 if (clk->recalc)
455 clk->rate = clk->recalc(clk);
290 456
291 if (clk->lpsc) 457 if (clk->lpsc)
292 clk->flags |= CLK_PSC; 458 clk->flags |= CLK_PSC;
293 459
294 clkdev_add(&c->lk);
295 clk_register(clk); 460 clk_register(clk);
461 num_clocks++;
296 462
297 /* Turn on clocks that Linux doesn't otherwise manage */ 463 /* Turn on clocks that Linux doesn't otherwise manage */
298 if (clk->flags & ALWAYS_ENABLED) 464 if (clk->flags & ALWAYS_ENABLED)
299 clk_enable(clk); 465 clk_enable(clk);
300 } 466 }
301 467
302 return 0; 468 clkdev_add_table(clocks, num_clocks);
303}
304
305#ifdef CONFIG_PROC_FS
306#include <linux/proc_fs.h>
307#include <linux/seq_file.h>
308 469
309static void *davinci_ck_start(struct seq_file *m, loff_t *pos) 470 return 0;
310{
311 return *pos < 1 ? (void *)1 : NULL;
312} 471}
313 472
314static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos) 473#ifdef CONFIG_DEBUG_FS
315{
316 ++*pos;
317 return NULL;
318}
319 474
320static void davinci_ck_stop(struct seq_file *m, void *v) 475#include <linux/debugfs.h>
321{ 476#include <linux/seq_file.h>
322}
323 477
324#define CLKNAME_MAX 10 /* longest clock name */ 478#define CLKNAME_MAX 10 /* longest clock name */
325#define NEST_DELTA 2 479#define NEST_DELTA 2
@@ -352,49 +506,45 @@ dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
352 /* REVISIT show device associations too */ 506 /* REVISIT show device associations too */
353 507
354 /* cost is now small, but not linear... */ 508 /* cost is now small, but not linear... */
355 list_for_each_entry(clk, &clocks, node) { 509 list_for_each_entry(clk, &parent->children, childnode) {
356 if (clk->parent == parent) 510 dump_clock(s, nest + NEST_DELTA, clk);
357 dump_clock(s, nest + NEST_DELTA, clk);
358 } 511 }
359} 512}
360 513
361static int davinci_ck_show(struct seq_file *m, void *v) 514static int davinci_ck_show(struct seq_file *m, void *v)
362{ 515{
363 /* Show clock tree; we know the main oscillator is first. 516 struct clk *clk;
364 * We trust nonzero usecounts equate to PSC enables... 517
518 /*
519 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
365 */ 520 */
366 mutex_lock(&clocks_mutex); 521 mutex_lock(&clocks_mutex);
367 if (!list_empty(&clocks)) 522 list_for_each_entry(clk, &clocks, node)
368 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node)); 523 if (!clk->parent)
524 dump_clock(m, 0, clk);
369 mutex_unlock(&clocks_mutex); 525 mutex_unlock(&clocks_mutex);
370 526
371 return 0; 527 return 0;
372} 528}
373 529
374static const struct seq_operations davinci_ck_op = {
375 .start = davinci_ck_start,
376 .next = davinci_ck_next,
377 .stop = davinci_ck_stop,
378 .show = davinci_ck_show
379};
380
381static int davinci_ck_open(struct inode *inode, struct file *file) 530static int davinci_ck_open(struct inode *inode, struct file *file)
382{ 531{
383 return seq_open(file, &davinci_ck_op); 532 return single_open(file, davinci_ck_show, NULL);
384} 533}
385 534
386static const struct file_operations proc_davinci_ck_operations = { 535static const struct file_operations davinci_ck_operations = {
387 .open = davinci_ck_open, 536 .open = davinci_ck_open,
388 .read = seq_read, 537 .read = seq_read,
389 .llseek = seq_lseek, 538 .llseek = seq_lseek,
390 .release = seq_release, 539 .release = single_release,
391}; 540};
392 541
393static int __init davinci_ck_proc_init(void) 542static int __init davinci_clk_debugfs_init(void)
394{ 543{
395 proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations); 544 debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
545 &davinci_ck_operations);
396 return 0; 546 return 0;
397 547
398} 548}
399__initcall(davinci_ck_proc_init); 549device_initcall(davinci_clk_debugfs_init);
400#endif /* CONFIG_DEBUG_PROC_FS */ 550#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 27233cb4a2fb..aa0a61150325 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -12,9 +12,6 @@
12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H 12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
13#define __ARCH_ARM_DAVINCI_CLOCK_H 13#define __ARCH_ARM_DAVINCI_CLOCK_H
14 14
15#include <linux/list.h>
16#include <asm/clkdev.h>
17
18#define DAVINCI_PLL1_BASE 0x01c40800 15#define DAVINCI_PLL1_BASE 0x01c40800
19#define DAVINCI_PLL2_BASE 0x01c40c00 16#define DAVINCI_PLL2_BASE 0x01c40c00
20#define MAX_PLL 2 17#define MAX_PLL 2
@@ -22,6 +19,10 @@
22/* PLL/Reset register offsets */ 19/* PLL/Reset register offsets */
23#define PLLCTL 0x100 20#define PLLCTL 0x100
24#define PLLCTL_PLLEN BIT(0) 21#define PLLCTL_PLLEN BIT(0)
22#define PLLCTL_PLLPWRDN BIT(1)
23#define PLLCTL_PLLRST BIT(3)
24#define PLLCTL_PLLDIS BIT(4)
25#define PLLCTL_PLLENSRC BIT(5)
25#define PLLCTL_CLKMODE BIT(8) 26#define PLLCTL_CLKMODE BIT(8)
26 27
27#define PLLM 0x110 28#define PLLM 0x110
@@ -49,6 +50,26 @@
49#define PLLDIV_EN BIT(15) 50#define PLLDIV_EN BIT(15)
50#define PLLDIV_RATIO_MASK 0x1f 51#define PLLDIV_RATIO_MASK 0x1f
51 52
53/*
54 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
55 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
56 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
57 * is ~25MHz. Units are micro seconds.
58 */
59#define PLL_BYPASS_TIME 1
60/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
61#define PLL_RESET_TIME 1
62/*
63 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
64 * Units are micro seconds.
65 */
66#define PLL_LOCK_TIME 20
67
68#ifndef __ASSEMBLER__
69
70#include <linux/list.h>
71#include <asm/clkdev.h>
72
52struct pll_data { 73struct pll_data {
53 u32 phys_base; 74 u32 phys_base;
54 void __iomem *base; 75 void __iomem *base;
@@ -65,36 +86,39 @@ struct clk {
65 const char *name; 86 const char *name;
66 unsigned long rate; 87 unsigned long rate;
67 u8 usecount; 88 u8 usecount;
68 u8 flags;
69 u8 lpsc; 89 u8 lpsc;
70 u8 psc_ctlr; 90 u8 gpsc;
91 u32 flags;
71 struct clk *parent; 92 struct clk *parent;
93 struct list_head children; /* list of children */
94 struct list_head childnode; /* parent's child list node */
72 struct pll_data *pll_data; 95 struct pll_data *pll_data;
73 u32 div_reg; 96 u32 div_reg;
97 unsigned long (*recalc) (struct clk *);
98 int (*set_rate) (struct clk *clk, unsigned long rate);
99 int (*round_rate) (struct clk *clk, unsigned long rate);
74}; 100};
75 101
76/* Clock flags */ 102/* Clock flags: SoC-specific flags start at BIT(16) */
77#define ALWAYS_ENABLED BIT(1) 103#define ALWAYS_ENABLED BIT(1)
78#define CLK_PSC BIT(2) 104#define CLK_PSC BIT(2)
79#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */ 105#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
80#define CLK_PLL BIT(4) /* PLL-derived clock */ 106#define CLK_PLL BIT(4) /* PLL-derived clock */
81#define PRE_PLL BIT(5) /* source is before PLL mult/div */ 107#define PRE_PLL BIT(5) /* source is before PLL mult/div */
82 108
83struct davinci_clk { 109#define CLK(dev, con, ck) \
84 struct clk_lookup lk; 110 { \
85}; 111 .dev_id = dev, \
86 112 .con_id = con, \
87#define CLK(dev, con, ck) \ 113 .clk = ck, \
88 { \ 114 } \
89 .lk = { \
90 .dev_id = dev, \
91 .con_id = con, \
92 .clk = ck, \
93 }, \
94 }
95 115
96int davinci_clk_init(struct davinci_clk *clocks); 116int davinci_clk_init(struct clk_lookup *clocks);
117int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
118 unsigned int mult, unsigned int postdiv);
97 119
98extern struct platform_device davinci_wdt_device; 120extern struct platform_device davinci_wdt_device;
99 121
100#endif 122#endif
123
124#endif
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 61ede19c6b54..94f27cbcd55a 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -11,13 +11,13 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/etherdevice.h> 13#include <linux/etherdevice.h>
14#include <linux/davinci_emac.h>
14 15
15#include <asm/tlb.h> 16#include <asm/tlb.h>
16#include <asm/mach/map.h> 17#include <asm/mach/map.h>
17 18
18#include <mach/common.h> 19#include <mach/common.h>
19#include <mach/cputype.h> 20#include <mach/cputype.h>
20#include <mach/emac.h>
21 21
22#include "clock.h" 22#include "clock.h"
23 23
@@ -86,6 +86,8 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
86 dip = davinci_get_id(davinci_soc_info.jtag_id); 86 dip = davinci_get_id(davinci_soc_info.jtag_id);
87 if (!dip) { 87 if (!dip) {
88 ret = -EINVAL; 88 ret = -EINVAL;
89 pr_err("Unknown DaVinci JTAG ID 0x%x\n",
90 davinci_soc_info.jtag_id);
89 goto err; 91 goto err;
90 } 92 }
91 93
@@ -104,5 +106,5 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
104 return; 106 return;
105 107
106err: 108err:
107 pr_err("davinci_common_init: SoC Initialization failed\n"); 109 panic("davinci_common_init: SoC Initialization failed\n");
108} 110}
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 96c8e97a7deb..37311d1830eb 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -10,9 +10,6 @@
10 */ 10 */
11 11
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/irq.h> 13#include <linux/irq.h>
17#include <linux/io.h> 14#include <linux/io.h>
18 15
@@ -84,12 +81,23 @@ static int cp_intc_set_irq_type(unsigned int irq, unsigned int flow_type)
84 return 0; 81 return 0;
85} 82}
86 83
84/*
85 * Faking this allows us to to work with suspend functions of
86 * generic drivers which call {enable|disable}_irq_wake for
87 * wake up interrupt sources (eg RTC on DA850).
88 */
89static int cp_intc_set_wake(unsigned int irq, unsigned int on)
90{
91 return 0;
92}
93
87static struct irq_chip cp_intc_irq_chip = { 94static struct irq_chip cp_intc_irq_chip = {
88 .name = "cp_intc", 95 .name = "cp_intc",
89 .ack = cp_intc_ack_irq, 96 .ack = cp_intc_ack_irq,
90 .mask = cp_intc_mask_irq, 97 .mask = cp_intc_mask_irq,
91 .unmask = cp_intc_unmask_irq, 98 .unmask = cp_intc_unmask_irq,
92 .set_type = cp_intc_set_irq_type, 99 .set_type = cp_intc_set_irq_type,
100 .set_wake = cp_intc_set_wake,
93}; 101};
94 102
95void __init cp_intc_init(void __iomem *base, unsigned short num_irq, 103void __init cp_intc_init(void __iomem *base, unsigned short num_irq,
diff --git a/arch/arm/mach-davinci/cpufreq.c b/arch/arm/mach-davinci/cpufreq.c
new file mode 100644
index 000000000000..d3fa6de1e20f
--- /dev/null
+++ b/arch/arm/mach-davinci/cpufreq.c
@@ -0,0 +1,226 @@
1/*
2 * CPU frequency scaling for DaVinci
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Based on linux/arch/arm/plat-omap/cpu-omap.c. Original Copyright follows:
7 *
8 * Copyright (C) 2005 Nokia Corporation
9 * Written by Tony Lindgren <tony@atomide.com>
10 *
11 * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
12 *
13 * Copyright (C) 2007-2008 Texas Instruments, Inc.
14 * Updated to support OMAP3
15 * Rajendra Nayak <rnayak@ti.com>
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21#include <linux/types.h>
22#include <linux/cpufreq.h>
23#include <linux/init.h>
24#include <linux/err.h>
25#include <linux/clk.h>
26#include <linux/platform_device.h>
27
28#include <mach/hardware.h>
29#include <mach/cpufreq.h>
30#include <mach/common.h>
31
32#include "clock.h"
33
34struct davinci_cpufreq {
35 struct device *dev;
36 struct clk *armclk;
37};
38static struct davinci_cpufreq cpufreq;
39
40static int davinci_verify_speed(struct cpufreq_policy *policy)
41{
42 struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
43 struct cpufreq_frequency_table *freq_table = pdata->freq_table;
44 struct clk *armclk = cpufreq.armclk;
45
46 if (freq_table)
47 return cpufreq_frequency_table_verify(policy, freq_table);
48
49 if (policy->cpu)
50 return -EINVAL;
51
52 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
53 policy->cpuinfo.max_freq);
54
55 policy->min = clk_round_rate(armclk, policy->min * 1000) / 1000;
56 policy->max = clk_round_rate(armclk, policy->max * 1000) / 1000;
57 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
58 policy->cpuinfo.max_freq);
59 return 0;
60}
61
62static unsigned int davinci_getspeed(unsigned int cpu)
63{
64 if (cpu)
65 return 0;
66
67 return clk_get_rate(cpufreq.armclk) / 1000;
68}
69
70static int davinci_target(struct cpufreq_policy *policy,
71 unsigned int target_freq, unsigned int relation)
72{
73 int ret = 0;
74 unsigned int idx;
75 struct cpufreq_freqs freqs;
76 struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
77 struct clk *armclk = cpufreq.armclk;
78
79 /*
80 * Ensure desired rate is within allowed range. Some govenors
81 * (ondemand) will just pass target_freq=0 to get the minimum.
82 */
83 if (target_freq < policy->cpuinfo.min_freq)
84 target_freq = policy->cpuinfo.min_freq;
85 if (target_freq > policy->cpuinfo.max_freq)
86 target_freq = policy->cpuinfo.max_freq;
87
88 freqs.old = davinci_getspeed(0);
89 freqs.new = clk_round_rate(armclk, target_freq * 1000) / 1000;
90 freqs.cpu = 0;
91
92 if (freqs.old == freqs.new)
93 return ret;
94
95 cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER,
96 dev_driver_string(cpufreq.dev),
97 "transition: %u --> %u\n", freqs.old, freqs.new);
98
99 ret = cpufreq_frequency_table_target(policy, pdata->freq_table,
100 freqs.new, relation, &idx);
101 if (ret)
102 return -EINVAL;
103
104 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
105
106 /* if moving to higher frequency, up the voltage beforehand */
107 if (pdata->set_voltage && freqs.new > freqs.old)
108 pdata->set_voltage(idx);
109
110 ret = clk_set_rate(armclk, idx);
111
112 /* if moving to lower freq, lower the voltage after lowering freq */
113 if (pdata->set_voltage && freqs.new < freqs.old)
114 pdata->set_voltage(idx);
115
116 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
117
118 return ret;
119}
120
121static int __init davinci_cpu_init(struct cpufreq_policy *policy)
122{
123 int result = 0;
124 struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;
125 struct cpufreq_frequency_table *freq_table = pdata->freq_table;
126
127 if (policy->cpu != 0)
128 return -EINVAL;
129
130 /* Finish platform specific initialization */
131 if (pdata->init) {
132 result = pdata->init();
133 if (result)
134 return result;
135 }
136
137 policy->cur = policy->min = policy->max = davinci_getspeed(0);
138
139 if (freq_table) {
140 result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
141 if (!result)
142 cpufreq_frequency_table_get_attr(freq_table,
143 policy->cpu);
144 } else {
145 policy->cpuinfo.min_freq = policy->min;
146 policy->cpuinfo.max_freq = policy->max;
147 }
148
149 policy->min = policy->cpuinfo.min_freq;
150 policy->max = policy->cpuinfo.max_freq;
151 policy->cur = davinci_getspeed(0);
152
153 /*
154 * Time measurement across the target() function yields ~1500-1800us
155 * time taken with no drivers on notification list.
156 * Setting the latency to 2000 us to accomodate addition of drivers
157 * to pre/post change notification list.
158 */
159 policy->cpuinfo.transition_latency = 2000 * 1000;
160 return 0;
161}
162
163static int davinci_cpu_exit(struct cpufreq_policy *policy)
164{
165 cpufreq_frequency_table_put_attr(policy->cpu);
166 return 0;
167}
168
169static struct freq_attr *davinci_cpufreq_attr[] = {
170 &cpufreq_freq_attr_scaling_available_freqs,
171 NULL,
172};
173
174static struct cpufreq_driver davinci_driver = {
175 .flags = CPUFREQ_STICKY,
176 .verify = davinci_verify_speed,
177 .target = davinci_target,
178 .get = davinci_getspeed,
179 .init = davinci_cpu_init,
180 .exit = davinci_cpu_exit,
181 .name = "davinci",
182 .attr = davinci_cpufreq_attr,
183};
184
185static int __init davinci_cpufreq_probe(struct platform_device *pdev)
186{
187 struct davinci_cpufreq_config *pdata = pdev->dev.platform_data;
188
189 if (!pdata)
190 return -EINVAL;
191 if (!pdata->freq_table)
192 return -EINVAL;
193
194 cpufreq.dev = &pdev->dev;
195
196 cpufreq.armclk = clk_get(NULL, "arm");
197 if (IS_ERR(cpufreq.armclk)) {
198 dev_err(cpufreq.dev, "Unable to get ARM clock\n");
199 return PTR_ERR(cpufreq.armclk);
200 }
201
202 return cpufreq_register_driver(&davinci_driver);
203}
204
205static int __exit davinci_cpufreq_remove(struct platform_device *pdev)
206{
207 clk_put(cpufreq.armclk);
208
209 return cpufreq_unregister_driver(&davinci_driver);
210}
211
212static struct platform_driver davinci_cpufreq_driver = {
213 .driver = {
214 .name = "cpufreq-davinci",
215 .owner = THIS_MODULE,
216 },
217 .remove = __exit_p(davinci_cpufreq_remove),
218};
219
220static int __init davinci_cpufreq_init(void)
221{
222 return platform_driver_probe(&davinci_cpufreq_driver,
223 davinci_cpufreq_probe);
224}
225late_initcall(davinci_cpufreq_init);
226
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
new file mode 100644
index 000000000000..bd59f31b8a95
--- /dev/null
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -0,0 +1,169 @@
1/*
2 * CPU idle for DaVinci SoCs
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
5 *
6 * Derived from Marvell Kirkwood CPU idle code
7 * (arch/arm/mach-kirkwood/cpuidle.c)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/cpuidle.h>
18#include <linux/io.h>
19#include <asm/proc-fns.h>
20
21#include <mach/cpuidle.h>
22#include <mach/memory.h>
23
24#define DAVINCI_CPUIDLE_MAX_STATES 2
25
26struct davinci_ops {
27 void (*enter) (u32 flags);
28 void (*exit) (u32 flags);
29 u32 flags;
30};
31
32/* fields in davinci_ops.flags */
33#define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
34
35static struct cpuidle_driver davinci_idle_driver = {
36 .name = "cpuidle-davinci",
37 .owner = THIS_MODULE,
38};
39
40static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
41static void __iomem *ddr2_reg_base;
42
43static void davinci_save_ddr_power(int enter, bool pdown)
44{
45 u32 val;
46
47 val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
48
49 if (enter) {
50 if (pdown)
51 val |= DDR2_SRPD_BIT;
52 else
53 val &= ~DDR2_SRPD_BIT;
54 val |= DDR2_LPMODEN_BIT;
55 } else {
56 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
57 }
58
59 __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
60}
61
62static void davinci_c2state_enter(u32 flags)
63{
64 davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
65}
66
67static void davinci_c2state_exit(u32 flags)
68{
69 davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
70}
71
72static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
73 [1] = {
74 .enter = davinci_c2state_enter,
75 .exit = davinci_c2state_exit,
76 },
77};
78
79/* Actual code that puts the SoC in different idle states */
80static int davinci_enter_idle(struct cpuidle_device *dev,
81 struct cpuidle_state *state)
82{
83 struct davinci_ops *ops = cpuidle_get_statedata(state);
84 struct timeval before, after;
85 int idle_time;
86
87 local_irq_disable();
88 do_gettimeofday(&before);
89
90 if (ops && ops->enter)
91 ops->enter(ops->flags);
92 /* Wait for interrupt state */
93 cpu_do_idle();
94 if (ops && ops->exit)
95 ops->exit(ops->flags);
96
97 do_gettimeofday(&after);
98 local_irq_enable();
99 idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
100 (after.tv_usec - before.tv_usec);
101 return idle_time;
102}
103
104static int __init davinci_cpuidle_probe(struct platform_device *pdev)
105{
106 int ret;
107 struct cpuidle_device *device;
108 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
109
110 device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
111
112 if (!pdata) {
113 dev_err(&pdev->dev, "cannot get platform data\n");
114 return -ENOENT;
115 }
116
117 ddr2_reg_base = pdata->ddr2_ctlr_base;
118
119 ret = cpuidle_register_driver(&davinci_idle_driver);
120 if (ret) {
121 dev_err(&pdev->dev, "failed to register driver\n");
122 return ret;
123 }
124
125 /* Wait for interrupt state */
126 device->states[0].enter = davinci_enter_idle;
127 device->states[0].exit_latency = 1;
128 device->states[0].target_residency = 10000;
129 device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
130 strcpy(device->states[0].name, "WFI");
131 strcpy(device->states[0].desc, "Wait for interrupt");
132
133 /* Wait for interrupt and DDR self refresh state */
134 device->states[1].enter = davinci_enter_idle;
135 device->states[1].exit_latency = 10;
136 device->states[1].target_residency = 10000;
137 device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
138 strcpy(device->states[1].name, "DDR SR");
139 strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
140 if (pdata->ddr2_pdown)
141 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
142 cpuidle_set_statedata(&device->states[1], &davinci_states[1]);
143
144 device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
145
146 ret = cpuidle_register_device(device);
147 if (ret) {
148 dev_err(&pdev->dev, "failed to register device\n");
149 cpuidle_unregister_driver(&davinci_idle_driver);
150 return ret;
151 }
152
153 return 0;
154}
155
156static struct platform_driver davinci_cpuidle_driver = {
157 .driver = {
158 .name = "cpuidle-davinci",
159 .owner = THIS_MODULE,
160 },
161};
162
163static int __init davinci_cpuidle_init(void)
164{
165 return platform_driver_probe(&davinci_cpuidle_driver,
166 davinci_cpuidle_probe);
167}
168device_initcall(davinci_cpuidle_init);
169
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 19b2748357fc..e8cb982f5e8e 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -8,22 +8,17 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/platform_device.h>
15 13
16#include <asm/mach/map.h> 14#include <asm/mach/map.h>
17 15
18#include <mach/clock.h>
19#include <mach/psc.h> 16#include <mach/psc.h>
20#include <mach/mux.h>
21#include <mach/irqs.h> 17#include <mach/irqs.h>
22#include <mach/cputype.h> 18#include <mach/cputype.h>
23#include <mach/common.h> 19#include <mach/common.h>
24#include <mach/time.h> 20#include <mach/time.h>
25#include <mach/da8xx.h> 21#include <mach/da8xx.h>
26#include <mach/asp.h>
27 22
28#include "clock.h" 23#include "clock.h"
29#include "mux.h" 24#include "mux.h"
@@ -193,14 +188,14 @@ static struct clk uart1_clk = {
193 .name = "uart1", 188 .name = "uart1",
194 .parent = &pll0_sysclk2, 189 .parent = &pll0_sysclk2,
195 .lpsc = DA8XX_LPSC1_UART1, 190 .lpsc = DA8XX_LPSC1_UART1,
196 .psc_ctlr = 1, 191 .gpsc = 1,
197}; 192};
198 193
199static struct clk uart2_clk = { 194static struct clk uart2_clk = {
200 .name = "uart2", 195 .name = "uart2",
201 .parent = &pll0_sysclk2, 196 .parent = &pll0_sysclk2,
202 .lpsc = DA8XX_LPSC1_UART2, 197 .lpsc = DA8XX_LPSC1_UART2,
203 .psc_ctlr = 1, 198 .gpsc = 1,
204}; 199};
205 200
206static struct clk spi0_clk = { 201static struct clk spi0_clk = {
@@ -213,98 +208,98 @@ static struct clk spi1_clk = {
213 .name = "spi1", 208 .name = "spi1",
214 .parent = &pll0_sysclk2, 209 .parent = &pll0_sysclk2,
215 .lpsc = DA8XX_LPSC1_SPI1, 210 .lpsc = DA8XX_LPSC1_SPI1,
216 .psc_ctlr = 1, 211 .gpsc = 1,
217}; 212};
218 213
219static struct clk ecap0_clk = { 214static struct clk ecap0_clk = {
220 .name = "ecap0", 215 .name = "ecap0",
221 .parent = &pll0_sysclk2, 216 .parent = &pll0_sysclk2,
222 .lpsc = DA8XX_LPSC1_ECAP, 217 .lpsc = DA8XX_LPSC1_ECAP,
223 .psc_ctlr = 1, 218 .gpsc = 1,
224}; 219};
225 220
226static struct clk ecap1_clk = { 221static struct clk ecap1_clk = {
227 .name = "ecap1", 222 .name = "ecap1",
228 .parent = &pll0_sysclk2, 223 .parent = &pll0_sysclk2,
229 .lpsc = DA8XX_LPSC1_ECAP, 224 .lpsc = DA8XX_LPSC1_ECAP,
230 .psc_ctlr = 1, 225 .gpsc = 1,
231}; 226};
232 227
233static struct clk ecap2_clk = { 228static struct clk ecap2_clk = {
234 .name = "ecap2", 229 .name = "ecap2",
235 .parent = &pll0_sysclk2, 230 .parent = &pll0_sysclk2,
236 .lpsc = DA8XX_LPSC1_ECAP, 231 .lpsc = DA8XX_LPSC1_ECAP,
237 .psc_ctlr = 1, 232 .gpsc = 1,
238}; 233};
239 234
240static struct clk pwm0_clk = { 235static struct clk pwm0_clk = {
241 .name = "pwm0", 236 .name = "pwm0",
242 .parent = &pll0_sysclk2, 237 .parent = &pll0_sysclk2,
243 .lpsc = DA8XX_LPSC1_PWM, 238 .lpsc = DA8XX_LPSC1_PWM,
244 .psc_ctlr = 1, 239 .gpsc = 1,
245}; 240};
246 241
247static struct clk pwm1_clk = { 242static struct clk pwm1_clk = {
248 .name = "pwm1", 243 .name = "pwm1",
249 .parent = &pll0_sysclk2, 244 .parent = &pll0_sysclk2,
250 .lpsc = DA8XX_LPSC1_PWM, 245 .lpsc = DA8XX_LPSC1_PWM,
251 .psc_ctlr = 1, 246 .gpsc = 1,
252}; 247};
253 248
254static struct clk pwm2_clk = { 249static struct clk pwm2_clk = {
255 .name = "pwm2", 250 .name = "pwm2",
256 .parent = &pll0_sysclk2, 251 .parent = &pll0_sysclk2,
257 .lpsc = DA8XX_LPSC1_PWM, 252 .lpsc = DA8XX_LPSC1_PWM,
258 .psc_ctlr = 1, 253 .gpsc = 1,
259}; 254};
260 255
261static struct clk eqep0_clk = { 256static struct clk eqep0_clk = {
262 .name = "eqep0", 257 .name = "eqep0",
263 .parent = &pll0_sysclk2, 258 .parent = &pll0_sysclk2,
264 .lpsc = DA830_LPSC1_EQEP, 259 .lpsc = DA830_LPSC1_EQEP,
265 .psc_ctlr = 1, 260 .gpsc = 1,
266}; 261};
267 262
268static struct clk eqep1_clk = { 263static struct clk eqep1_clk = {
269 .name = "eqep1", 264 .name = "eqep1",
270 .parent = &pll0_sysclk2, 265 .parent = &pll0_sysclk2,
271 .lpsc = DA830_LPSC1_EQEP, 266 .lpsc = DA830_LPSC1_EQEP,
272 .psc_ctlr = 1, 267 .gpsc = 1,
273}; 268};
274 269
275static struct clk lcdc_clk = { 270static struct clk lcdc_clk = {
276 .name = "lcdc", 271 .name = "lcdc",
277 .parent = &pll0_sysclk2, 272 .parent = &pll0_sysclk2,
278 .lpsc = DA8XX_LPSC1_LCDC, 273 .lpsc = DA8XX_LPSC1_LCDC,
279 .psc_ctlr = 1, 274 .gpsc = 1,
280}; 275};
281 276
282static struct clk mcasp0_clk = { 277static struct clk mcasp0_clk = {
283 .name = "mcasp0", 278 .name = "mcasp0",
284 .parent = &pll0_sysclk2, 279 .parent = &pll0_sysclk2,
285 .lpsc = DA8XX_LPSC1_McASP0, 280 .lpsc = DA8XX_LPSC1_McASP0,
286 .psc_ctlr = 1, 281 .gpsc = 1,
287}; 282};
288 283
289static struct clk mcasp1_clk = { 284static struct clk mcasp1_clk = {
290 .name = "mcasp1", 285 .name = "mcasp1",
291 .parent = &pll0_sysclk2, 286 .parent = &pll0_sysclk2,
292 .lpsc = DA830_LPSC1_McASP1, 287 .lpsc = DA830_LPSC1_McASP1,
293 .psc_ctlr = 1, 288 .gpsc = 1,
294}; 289};
295 290
296static struct clk mcasp2_clk = { 291static struct clk mcasp2_clk = {
297 .name = "mcasp2", 292 .name = "mcasp2",
298 .parent = &pll0_sysclk2, 293 .parent = &pll0_sysclk2,
299 .lpsc = DA830_LPSC1_McASP2, 294 .lpsc = DA830_LPSC1_McASP2,
300 .psc_ctlr = 1, 295 .gpsc = 1,
301}; 296};
302 297
303static struct clk usb20_clk = { 298static struct clk usb20_clk = {
304 .name = "usb20", 299 .name = "usb20",
305 .parent = &pll0_sysclk2, 300 .parent = &pll0_sysclk2,
306 .lpsc = DA8XX_LPSC1_USB20, 301 .lpsc = DA8XX_LPSC1_USB20,
307 .psc_ctlr = 1, 302 .gpsc = 1,
308}; 303};
309 304
310static struct clk aemif_clk = { 305static struct clk aemif_clk = {
@@ -332,36 +327,36 @@ static struct clk emac_clk = {
332 .name = "emac", 327 .name = "emac",
333 .parent = &pll0_sysclk4, 328 .parent = &pll0_sysclk4,
334 .lpsc = DA8XX_LPSC1_CPGMAC, 329 .lpsc = DA8XX_LPSC1_CPGMAC,
335 .psc_ctlr = 1, 330 .gpsc = 1,
336}; 331};
337 332
338static struct clk gpio_clk = { 333static struct clk gpio_clk = {
339 .name = "gpio", 334 .name = "gpio",
340 .parent = &pll0_sysclk4, 335 .parent = &pll0_sysclk4,
341 .lpsc = DA8XX_LPSC1_GPIO, 336 .lpsc = DA8XX_LPSC1_GPIO,
342 .psc_ctlr = 1, 337 .gpsc = 1,
343}; 338};
344 339
345static struct clk i2c1_clk = { 340static struct clk i2c1_clk = {
346 .name = "i2c1", 341 .name = "i2c1",
347 .parent = &pll0_sysclk4, 342 .parent = &pll0_sysclk4,
348 .lpsc = DA8XX_LPSC1_I2C, 343 .lpsc = DA8XX_LPSC1_I2C,
349 .psc_ctlr = 1, 344 .gpsc = 1,
350}; 345};
351 346
352static struct clk usb11_clk = { 347static struct clk usb11_clk = {
353 .name = "usb11", 348 .name = "usb11",
354 .parent = &pll0_sysclk4, 349 .parent = &pll0_sysclk4,
355 .lpsc = DA8XX_LPSC1_USB11, 350 .lpsc = DA8XX_LPSC1_USB11,
356 .psc_ctlr = 1, 351 .gpsc = 1,
357}; 352};
358 353
359static struct clk emif3_clk = { 354static struct clk emif3_clk = {
360 .name = "emif3", 355 .name = "emif3",
361 .parent = &pll0_sysclk5, 356 .parent = &pll0_sysclk5,
362 .lpsc = DA8XX_LPSC1_EMIF3C, 357 .lpsc = DA8XX_LPSC1_EMIF3C,
358 .gpsc = 1,
363 .flags = ALWAYS_ENABLED, 359 .flags = ALWAYS_ENABLED,
364 .psc_ctlr = 1,
365}; 360};
366 361
367static struct clk arm_clk = { 362static struct clk arm_clk = {
@@ -376,7 +371,7 @@ static struct clk rmii_clk = {
376 .parent = &pll0_sysclk7, 371 .parent = &pll0_sysclk7,
377}; 372};
378 373
379static struct davinci_clk da830_clks[] = { 374static struct clk_lookup da830_clks[] = {
380 CLK(NULL, "ref", &ref_clk), 375 CLK(NULL, "ref", &ref_clk),
381 CLK(NULL, "pll0", &pll0_clk), 376 CLK(NULL, "pll0", &pll0_clk),
382 CLK(NULL, "pll0_aux", &pll0_aux_clk), 377 CLK(NULL, "pll0_aux", &pll0_aux_clk),
@@ -411,11 +406,11 @@ static struct davinci_clk da830_clks[] = {
411 CLK(NULL, "pwm2", &pwm2_clk), 406 CLK(NULL, "pwm2", &pwm2_clk),
412 CLK("eqep.0", NULL, &eqep0_clk), 407 CLK("eqep.0", NULL, &eqep0_clk),
413 CLK("eqep.1", NULL, &eqep1_clk), 408 CLK("eqep.1", NULL, &eqep1_clk),
414 CLK("da830_lcdc", NULL, &lcdc_clk), 409 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
415 CLK("davinci-mcasp.0", NULL, &mcasp0_clk), 410 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
416 CLK("davinci-mcasp.1", NULL, &mcasp1_clk), 411 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
417 CLK("davinci-mcasp.2", NULL, &mcasp2_clk), 412 CLK("davinci-mcasp.2", NULL, &mcasp2_clk),
418 CLK("musb_hdrc", NULL, &usb20_clk), 413 CLK(NULL, "usb20", &usb20_clk),
419 CLK(NULL, "aemif", &aemif_clk), 414 CLK(NULL, "aemif", &aemif_clk),
420 CLK(NULL, "aintc", &aintc_clk), 415 CLK(NULL, "aintc", &aintc_clk),
421 CLK(NULL, "secu_mgr", &secu_mgr_clk), 416 CLK(NULL, "secu_mgr", &secu_mgr_clk),
@@ -1143,7 +1138,21 @@ static struct davinci_id da830_ids[] = {
1143 .part_no = 0xb7df, 1138 .part_no = 0xb7df,
1144 .manufacturer = 0x017, /* 0x02f >> 1 */ 1139 .manufacturer = 0x017, /* 0x02f >> 1 */
1145 .cpu_id = DAVINCI_CPU_ID_DA830, 1140 .cpu_id = DAVINCI_CPU_ID_DA830,
1146 .name = "da830/omap l137", 1141 .name = "da830/omap-l137 rev1.0",
1142 },
1143 {
1144 .variant = 0x8,
1145 .part_no = 0xb7df,
1146 .manufacturer = 0x017,
1147 .cpu_id = DAVINCI_CPU_ID_DA830,
1148 .name = "da830/omap-l137 rev1.1",
1149 },
1150 {
1151 .variant = 0x9,
1152 .part_no = 0xb7df,
1153 .manufacturer = 0x017,
1154 .cpu_id = DAVINCI_CPU_ID_DA830,
1155 .name = "da830/omap-l137 rev2.0",
1147 }, 1156 },
1148}; 1157};
1149 1158
@@ -1178,13 +1187,11 @@ static struct davinci_timer_info da830_timer_info = {
1178static struct davinci_soc_info davinci_soc_info_da830 = { 1187static struct davinci_soc_info davinci_soc_info_da830 = {
1179 .io_desc = da830_io_desc, 1188 .io_desc = da830_io_desc,
1180 .io_desc_num = ARRAY_SIZE(da830_io_desc), 1189 .io_desc_num = ARRAY_SIZE(da830_io_desc),
1181 .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG),
1182 .ids = da830_ids, 1190 .ids = da830_ids,
1183 .ids_num = ARRAY_SIZE(da830_ids), 1191 .ids_num = ARRAY_SIZE(da830_ids),
1184 .cpu_clks = da830_clks, 1192 .cpu_clks = da830_clks,
1185 .psc_bases = da830_psc_bases, 1193 .psc_bases = da830_psc_bases,
1186 .psc_bases_num = ARRAY_SIZE(da830_psc_bases), 1194 .psc_bases_num = ARRAY_SIZE(da830_psc_bases),
1187 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
1188 .pinmux_pins = da830_pins, 1195 .pinmux_pins = da830_pins,
1189 .pinmux_pins_num = ARRAY_SIZE(da830_pins), 1196 .pinmux_pins_num = ARRAY_SIZE(da830_pins),
1190 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, 1197 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
@@ -1201,5 +1208,13 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
1201 1208
1202void __init da830_init(void) 1209void __init da830_init(void)
1203{ 1210{
1211 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1212 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1213 return;
1214
1215 davinci_soc_info_da830.jtag_id_base =
1216 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1217 davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
1218
1204 davinci_common_init(&davinci_soc_info_da830); 1219 davinci_common_init(&davinci_soc_info_da830);
1205} 1220}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 192d719a47df..d0fd7566712a 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -11,31 +11,43 @@
11 * is licensed "as is" without any warranty of any kind, whether express 11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied. 12 * or implied.
13 */ 13 */
14#include <linux/kernel.h>
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/clk.h> 15#include <linux/clk.h>
17#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/cpufreq.h>
18#include <linux/regulator/consumer.h>
18 19
19#include <asm/mach/map.h> 20#include <asm/mach/map.h>
20 21
21#include <mach/clock.h>
22#include <mach/psc.h> 22#include <mach/psc.h>
23#include <mach/mux.h>
24#include <mach/irqs.h> 23#include <mach/irqs.h>
25#include <mach/cputype.h> 24#include <mach/cputype.h>
26#include <mach/common.h> 25#include <mach/common.h>
27#include <mach/time.h> 26#include <mach/time.h>
28#include <mach/da8xx.h> 27#include <mach/da8xx.h>
28#include <mach/cpufreq.h>
29#include <mach/pm.h>
29 30
30#include "clock.h" 31#include "clock.h"
31#include "mux.h" 32#include "mux.h"
32 33
34/* SoC specific clock flags */
35#define DA850_CLK_ASYNC3 BIT(16)
36
33#define DA850_PLL1_BASE 0x01e1a000 37#define DA850_PLL1_BASE 0x01e1a000
34#define DA850_TIMER64P2_BASE 0x01f0c000 38#define DA850_TIMER64P2_BASE 0x01f0c000
35#define DA850_TIMER64P3_BASE 0x01f0d000 39#define DA850_TIMER64P3_BASE 0x01f0d000
36 40
37#define DA850_REF_FREQ 24000000 41#define DA850_REF_FREQ 24000000
38 42
43#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
44#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
45#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
46
47static int da850_set_armrate(struct clk *clk, unsigned long rate);
48static int da850_round_armrate(struct clk *clk, unsigned long rate);
49static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
50
39static struct pll_data pll0_data = { 51static struct pll_data pll0_data = {
40 .num = 1, 52 .num = 1,
41 .phys_base = DA8XX_PLL0_BASE, 53 .phys_base = DA8XX_PLL0_BASE,
@@ -52,6 +64,7 @@ static struct clk pll0_clk = {
52 .parent = &ref_clk, 64 .parent = &ref_clk,
53 .pll_data = &pll0_data, 65 .pll_data = &pll0_data,
54 .flags = CLK_PLL, 66 .flags = CLK_PLL,
67 .set_rate = da850_set_pll0rate,
55}; 68};
56 69
57static struct clk pll0_aux_clk = { 70static struct clk pll0_aux_clk = {
@@ -210,16 +223,16 @@ static struct clk tpcc1_clk = {
210 .name = "tpcc1", 223 .name = "tpcc1",
211 .parent = &pll0_sysclk2, 224 .parent = &pll0_sysclk2,
212 .lpsc = DA850_LPSC1_TPCC1, 225 .lpsc = DA850_LPSC1_TPCC1,
226 .gpsc = 1,
213 .flags = CLK_PSC | ALWAYS_ENABLED, 227 .flags = CLK_PSC | ALWAYS_ENABLED,
214 .psc_ctlr = 1,
215}; 228};
216 229
217static struct clk tptc2_clk = { 230static struct clk tptc2_clk = {
218 .name = "tptc2", 231 .name = "tptc2",
219 .parent = &pll0_sysclk2, 232 .parent = &pll0_sysclk2,
220 .lpsc = DA850_LPSC1_TPTC2, 233 .lpsc = DA850_LPSC1_TPTC2,
234 .gpsc = 1,
221 .flags = ALWAYS_ENABLED, 235 .flags = ALWAYS_ENABLED,
222 .psc_ctlr = 1,
223}; 236};
224 237
225static struct clk uart0_clk = { 238static struct clk uart0_clk = {
@@ -232,14 +245,16 @@ static struct clk uart1_clk = {
232 .name = "uart1", 245 .name = "uart1",
233 .parent = &pll0_sysclk2, 246 .parent = &pll0_sysclk2,
234 .lpsc = DA8XX_LPSC1_UART1, 247 .lpsc = DA8XX_LPSC1_UART1,
235 .psc_ctlr = 1, 248 .gpsc = 1,
249 .flags = DA850_CLK_ASYNC3,
236}; 250};
237 251
238static struct clk uart2_clk = { 252static struct clk uart2_clk = {
239 .name = "uart2", 253 .name = "uart2",
240 .parent = &pll0_sysclk2, 254 .parent = &pll0_sysclk2,
241 .lpsc = DA8XX_LPSC1_UART2, 255 .lpsc = DA8XX_LPSC1_UART2,
242 .psc_ctlr = 1, 256 .gpsc = 1,
257 .flags = DA850_CLK_ASYNC3,
243}; 258};
244 259
245static struct clk aintc_clk = { 260static struct clk aintc_clk = {
@@ -253,22 +268,22 @@ static struct clk gpio_clk = {
253 .name = "gpio", 268 .name = "gpio",
254 .parent = &pll0_sysclk4, 269 .parent = &pll0_sysclk4,
255 .lpsc = DA8XX_LPSC1_GPIO, 270 .lpsc = DA8XX_LPSC1_GPIO,
256 .psc_ctlr = 1, 271 .gpsc = 1,
257}; 272};
258 273
259static struct clk i2c1_clk = { 274static struct clk i2c1_clk = {
260 .name = "i2c1", 275 .name = "i2c1",
261 .parent = &pll0_sysclk4, 276 .parent = &pll0_sysclk4,
262 .lpsc = DA8XX_LPSC1_I2C, 277 .lpsc = DA8XX_LPSC1_I2C,
263 .psc_ctlr = 1, 278 .gpsc = 1,
264}; 279};
265 280
266static struct clk emif3_clk = { 281static struct clk emif3_clk = {
267 .name = "emif3", 282 .name = "emif3",
268 .parent = &pll0_sysclk5, 283 .parent = &pll0_sysclk5,
269 .lpsc = DA8XX_LPSC1_EMIF3C, 284 .lpsc = DA8XX_LPSC1_EMIF3C,
285 .gpsc = 1,
270 .flags = ALWAYS_ENABLED, 286 .flags = ALWAYS_ENABLED,
271 .psc_ctlr = 1,
272}; 287};
273 288
274static struct clk arm_clk = { 289static struct clk arm_clk = {
@@ -276,6 +291,8 @@ static struct clk arm_clk = {
276 .parent = &pll0_sysclk6, 291 .parent = &pll0_sysclk6,
277 .lpsc = DA8XX_LPSC0_ARM, 292 .lpsc = DA8XX_LPSC0_ARM,
278 .flags = ALWAYS_ENABLED, 293 .flags = ALWAYS_ENABLED,
294 .set_rate = da850_set_armrate,
295 .round_rate = da850_round_armrate,
279}; 296};
280 297
281static struct clk rmii_clk = { 298static struct clk rmii_clk = {
@@ -287,21 +304,22 @@ static struct clk emac_clk = {
287 .name = "emac", 304 .name = "emac",
288 .parent = &pll0_sysclk4, 305 .parent = &pll0_sysclk4,
289 .lpsc = DA8XX_LPSC1_CPGMAC, 306 .lpsc = DA8XX_LPSC1_CPGMAC,
290 .psc_ctlr = 1, 307 .gpsc = 1,
291}; 308};
292 309
293static struct clk mcasp_clk = { 310static struct clk mcasp_clk = {
294 .name = "mcasp", 311 .name = "mcasp",
295 .parent = &pll0_sysclk2, 312 .parent = &pll0_sysclk2,
296 .lpsc = DA8XX_LPSC1_McASP0, 313 .lpsc = DA8XX_LPSC1_McASP0,
297 .psc_ctlr = 1, 314 .gpsc = 1,
315 .flags = DA850_CLK_ASYNC3,
298}; 316};
299 317
300static struct clk lcdc_clk = { 318static struct clk lcdc_clk = {
301 .name = "lcdc", 319 .name = "lcdc",
302 .parent = &pll0_sysclk2, 320 .parent = &pll0_sysclk2,
303 .lpsc = DA8XX_LPSC1_LCDC, 321 .lpsc = DA8XX_LPSC1_LCDC,
304 .psc_ctlr = 1, 322 .gpsc = 1,
305}; 323};
306 324
307static struct clk mmcsd_clk = { 325static struct clk mmcsd_clk = {
@@ -317,7 +335,7 @@ static struct clk aemif_clk = {
317 .flags = ALWAYS_ENABLED, 335 .flags = ALWAYS_ENABLED,
318}; 336};
319 337
320static struct davinci_clk da850_clks[] = { 338static struct clk_lookup da850_clks[] = {
321 CLK(NULL, "ref", &ref_clk), 339 CLK(NULL, "ref", &ref_clk),
322 CLK(NULL, "pll0", &pll0_clk), 340 CLK(NULL, "pll0", &pll0_clk),
323 CLK(NULL, "pll0_aux", &pll0_aux_clk), 341 CLK(NULL, "pll0_aux", &pll0_aux_clk),
@@ -404,6 +422,14 @@ static const struct mux_config da850_pins[] = {
404 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false) 422 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
405 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false) 423 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
406 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false) 424 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
425 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
426 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
427 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
428 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
429 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
430 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
431 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
432 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
407 /* McASP function */ 433 /* McASP function */
408 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false) 434 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
409 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false) 435 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
@@ -506,10 +532,12 @@ static const struct mux_config da850_pins[] = {
506 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false) 532 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
507 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false) 533 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
508 /* GPIO function */ 534 /* GPIO function */
535 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
536 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
509 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 537 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
510 MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false)
511 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 538 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
512 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 539 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
540 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
513#endif 541#endif
514}; 542};
515 543
@@ -547,6 +575,14 @@ const short da850_cpgmac_pins[] __initdata = {
547 -1 575 -1
548}; 576};
549 577
578const short da850_rmii_pins[] __initdata = {
579 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
580 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
581 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
582 DA850_MDIO_D,
583 -1
584};
585
550const short da850_mcasp_pins[] __initdata = { 586const short da850_mcasp_pins[] __initdata = {
551 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, 587 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
552 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, 588 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
@@ -555,12 +591,11 @@ const short da850_mcasp_pins[] __initdata = {
555}; 591};
556 592
557const short da850_lcdcntl_pins[] __initdata = { 593const short da850_lcdcntl_pins[] __initdata = {
558 DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4, 594 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
559 DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8, 595 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
560 DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12, 596 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
561 DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK, 597 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
562 DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15, 598 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
563 DA850_GPIO8_10,
564 -1 599 -1
565}; 600};
566 601
@@ -738,6 +773,12 @@ static struct map_desc da850_io_desc[] = {
738 .length = DA8XX_CP_INTC_SIZE, 773 .length = DA8XX_CP_INTC_SIZE,
739 .type = MT_DEVICE 774 .type = MT_DEVICE
740 }, 775 },
776 {
777 .virtual = SRAM_VIRT,
778 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
779 .length = SZ_8K,
780 .type = MT_DEVICE
781 },
741}; 782};
742 783
743static void __iomem *da850_psc_bases[] = { 784static void __iomem *da850_psc_bases[] = {
@@ -790,16 +831,252 @@ static struct davinci_timer_info da850_timer_info = {
790 .clocksource_id = T0_TOP, 831 .clocksource_id = T0_TOP,
791}; 832};
792 833
834static void da850_set_async3_src(int pllnum)
835{
836 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
837 struct clk_lookup *c;
838 unsigned int v;
839 int ret;
840
841 for (c = da850_clks; c->clk; c++) {
842 clk = c->clk;
843 if (clk->flags & DA850_CLK_ASYNC3) {
844 ret = clk_set_parent(clk, newparent);
845 WARN(ret, "DA850: unable to re-parent clock %s",
846 clk->name);
847 }
848 }
849
850 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
851 if (pllnum)
852 v |= CFGCHIP3_ASYNC3_CLKSRC;
853 else
854 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
855 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
856}
857
858#ifdef CONFIG_CPU_FREQ
859/*
860 * Notes:
861 * According to the TRM, minimum PLLM results in maximum power savings.
862 * The OPP definitions below should keep the PLLM as low as possible.
863 *
864 * The output of the PLLM must be between 400 to 600 MHz.
865 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
866 */
867struct da850_opp {
868 unsigned int freq; /* in KHz */
869 unsigned int prediv;
870 unsigned int mult;
871 unsigned int postdiv;
872 unsigned int cvdd_min; /* in uV */
873 unsigned int cvdd_max; /* in uV */
874};
875
876static const struct da850_opp da850_opp_300 = {
877 .freq = 300000,
878 .prediv = 1,
879 .mult = 25,
880 .postdiv = 2,
881 .cvdd_min = 1140000,
882 .cvdd_max = 1320000,
883};
884
885static const struct da850_opp da850_opp_200 = {
886 .freq = 200000,
887 .prediv = 1,
888 .mult = 25,
889 .postdiv = 3,
890 .cvdd_min = 1050000,
891 .cvdd_max = 1160000,
892};
893
894static const struct da850_opp da850_opp_96 = {
895 .freq = 96000,
896 .prediv = 1,
897 .mult = 20,
898 .postdiv = 5,
899 .cvdd_min = 950000,
900 .cvdd_max = 1050000,
901};
902
903#define OPP(freq) \
904 { \
905 .index = (unsigned int) &da850_opp_##freq, \
906 .frequency = freq * 1000, \
907 }
908
909static struct cpufreq_frequency_table da850_freq_table[] = {
910 OPP(300),
911 OPP(200),
912 OPP(96),
913 {
914 .index = 0,
915 .frequency = CPUFREQ_TABLE_END,
916 },
917};
918
919#ifdef CONFIG_REGULATOR
920static struct regulator *cvdd;
921
922static int da850_set_voltage(unsigned int index)
923{
924 struct da850_opp *opp;
925
926 if (!cvdd)
927 return -ENODEV;
928
929 opp = (struct da850_opp *) da850_freq_table[index].index;
930
931 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
932}
933
934static int da850_regulator_init(void)
935{
936 cvdd = regulator_get(NULL, "cvdd");
937 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
938 " voltage scaling unsupported\n")) {
939 return PTR_ERR(cvdd);
940 }
941
942 return 0;
943}
944#endif
945
946static struct davinci_cpufreq_config cpufreq_info = {
947 .freq_table = &da850_freq_table[0],
948#ifdef CONFIG_REGULATOR
949 .init = da850_regulator_init,
950 .set_voltage = da850_set_voltage,
951#endif
952};
953
954static struct platform_device da850_cpufreq_device = {
955 .name = "cpufreq-davinci",
956 .dev = {
957 .platform_data = &cpufreq_info,
958 },
959};
960
961int __init da850_register_cpufreq(void)
962{
963 return platform_device_register(&da850_cpufreq_device);
964}
965
966static int da850_round_armrate(struct clk *clk, unsigned long rate)
967{
968 int i, ret = 0, diff;
969 unsigned int best = (unsigned int) -1;
970
971 rate /= 1000; /* convert to kHz */
972
973 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
974 diff = da850_freq_table[i].frequency - rate;
975 if (diff < 0)
976 diff = -diff;
977
978 if (diff < best) {
979 best = diff;
980 ret = da850_freq_table[i].frequency;
981 }
982 }
983
984 return ret * 1000;
985}
986
987static int da850_set_armrate(struct clk *clk, unsigned long index)
988{
989 struct clk *pllclk = &pll0_clk;
990
991 return clk_set_rate(pllclk, index);
992}
993
994static int da850_set_pll0rate(struct clk *clk, unsigned long index)
995{
996 unsigned int prediv, mult, postdiv;
997 struct da850_opp *opp;
998 struct pll_data *pll = clk->pll_data;
999 int ret;
1000
1001 opp = (struct da850_opp *) da850_freq_table[index].index;
1002 prediv = opp->prediv;
1003 mult = opp->mult;
1004 postdiv = opp->postdiv;
1005
1006 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1007 if (WARN_ON(ret))
1008 return ret;
1009
1010 return 0;
1011}
1012#else
1013int __init da850_register_cpufreq(void)
1014{
1015 return 0;
1016}
1017
1018static int da850_set_armrate(struct clk *clk, unsigned long rate)
1019{
1020 return -EINVAL;
1021}
1022
1023static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1024{
1025 return -EINVAL;
1026}
1027
1028static int da850_round_armrate(struct clk *clk, unsigned long rate)
1029{
1030 return clk->rate;
1031}
1032#endif
1033
1034int da850_register_pm(struct platform_device *pdev)
1035{
1036 int ret;
1037 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1038
1039 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1040 if (ret)
1041 return ret;
1042
1043 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1044 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1045 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1046
1047 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1048 if (!pdata->cpupll_reg_base)
1049 return -ENOMEM;
1050
1051 pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
1052 if (!pdata->ddrpll_reg_base) {
1053 ret = -ENOMEM;
1054 goto no_ddrpll_mem;
1055 }
1056
1057 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1058 if (!pdata->ddrpsc_reg_base) {
1059 ret = -ENOMEM;
1060 goto no_ddrpsc_mem;
1061 }
1062
1063 return platform_device_register(pdev);
1064
1065no_ddrpsc_mem:
1066 iounmap(pdata->ddrpll_reg_base);
1067no_ddrpll_mem:
1068 iounmap(pdata->cpupll_reg_base);
1069 return ret;
1070}
1071
793static struct davinci_soc_info davinci_soc_info_da850 = { 1072static struct davinci_soc_info davinci_soc_info_da850 = {
794 .io_desc = da850_io_desc, 1073 .io_desc = da850_io_desc,
795 .io_desc_num = ARRAY_SIZE(da850_io_desc), 1074 .io_desc_num = ARRAY_SIZE(da850_io_desc),
796 .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG),
797 .ids = da850_ids, 1075 .ids = da850_ids,
798 .ids_num = ARRAY_SIZE(da850_ids), 1076 .ids_num = ARRAY_SIZE(da850_ids),
799 .cpu_clks = da850_clks, 1077 .cpu_clks = da850_clks,
800 .psc_bases = da850_psc_bases, 1078 .psc_bases = da850_psc_bases,
801 .psc_bases_num = ARRAY_SIZE(da850_psc_bases), 1079 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
802 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
803 .pinmux_pins = da850_pins, 1080 .pinmux_pins = da850_pins,
804 .pinmux_pins_num = ARRAY_SIZE(da850_pins), 1081 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
805 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT, 1082 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
@@ -812,9 +1089,44 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
812 .gpio_irq = IRQ_DA8XX_GPIO0, 1089 .gpio_irq = IRQ_DA8XX_GPIO0,
813 .serial_dev = &da8xx_serial_device, 1090 .serial_dev = &da8xx_serial_device,
814 .emac_pdata = &da8xx_emac_pdata, 1091 .emac_pdata = &da8xx_emac_pdata,
1092 .sram_dma = DA8XX_ARM_RAM_BASE,
1093 .sram_len = SZ_8K,
815}; 1094};
816 1095
817void __init da850_init(void) 1096void __init da850_init(void)
818{ 1097{
1098 unsigned int v;
1099
1100 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1101 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1102 return;
1103
1104 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1105 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1106 return;
1107
1108 davinci_soc_info_da850.jtag_id_base =
1109 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1110 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
1111
819 davinci_common_init(&davinci_soc_info_da850); 1112 davinci_common_init(&davinci_soc_info_da850);
1113
1114 /*
1115 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1116 * This helps keeping the peripherals on this domain insulated
1117 * from CPU frequency changes caused by DVFS. The firmware sets
1118 * both PLL0 and PLL1 to the same frequency so, there should not
1119 * be any noticible change even in non-DVFS use cases.
1120 */
1121 da850_set_async3_src(1);
1122
1123 /* Unlock writing to PLL0 registers */
1124 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1125 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1126 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1127
1128 /* Unlock writing to PLL1 registers */
1129 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1130 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1131 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
820} 1132}
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 58ad5b66fd60..0a96791d3b0f 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -10,8 +10,6 @@
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 */ 12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h> 13#include <linux/init.h>
16#include <linux/platform_device.h> 14#include <linux/platform_device.h>
17#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
@@ -21,15 +19,18 @@
21#include <mach/common.h> 19#include <mach/common.h>
22#include <mach/time.h> 20#include <mach/time.h>
23#include <mach/da8xx.h> 21#include <mach/da8xx.h>
24#include <video/da8xx-fb.h> 22#include <mach/cpuidle.h>
25 23
26#include "clock.h" 24#include "clock.h"
27 25
28#define DA8XX_TPCC_BASE 0x01c00000 26#define DA8XX_TPCC_BASE 0x01c00000
27#define DA850_TPCC1_BASE 0x01e30000
29#define DA8XX_TPTC0_BASE 0x01c08000 28#define DA8XX_TPTC0_BASE 0x01c08000
30#define DA8XX_TPTC1_BASE 0x01c08400 29#define DA8XX_TPTC1_BASE 0x01c08400
30#define DA850_TPTC2_BASE 0x01e38000
31#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 31#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
32#define DA8XX_I2C0_BASE 0x01c22000 32#define DA8XX_I2C0_BASE 0x01c22000
33#define DA8XX_RTC_BASE 0x01C23000
33#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000 34#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
34#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000 35#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
35#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000 36#define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
@@ -43,6 +44,9 @@
43#define DA8XX_MDIO_REG_OFFSET 0x4000 44#define DA8XX_MDIO_REG_OFFSET 0x4000
44#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 45#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
45 46
47void __iomem *da8xx_syscfg0_base;
48void __iomem *da8xx_syscfg1_base;
49
46static struct plat_serial8250_port da8xx_serial_pdata[] = { 50static struct plat_serial8250_port da8xx_serial_pdata[] = {
47 { 51 {
48 .mapbase = DA8XX_UART0_BASE, 52 .mapbase = DA8XX_UART0_BASE,
@@ -81,11 +85,6 @@ struct platform_device da8xx_serial_device = {
81 }, 85 },
82}; 86};
83 87
84static const s8 da8xx_dma_chan_no_event[] = {
85 20, 21,
86 -1
87};
88
89static const s8 da8xx_queue_tc_mapping[][2] = { 88static const s8 da8xx_queue_tc_mapping[][2] = {
90 /* {event queue no, TC no} */ 89 /* {event queue no, TC no} */
91 {0, 0}, 90 {0, 0},
@@ -100,20 +99,52 @@ static const s8 da8xx_queue_priority_mapping[][2] = {
100 {-1, -1} 99 {-1, -1}
101}; 100};
102 101
103static struct edma_soc_info da8xx_edma_info[] = { 102static const s8 da850_queue_tc_mapping[][2] = {
103 /* {event queue no, TC no} */
104 {0, 0},
105 {-1, -1}
106};
107
108static const s8 da850_queue_priority_mapping[][2] = {
109 /* {event queue no, Priority} */
110 {0, 3},
111 {-1, -1}
112};
113
114static struct edma_soc_info da830_edma_info[] = {
104 { 115 {
105 .n_channel = 32, 116 .n_channel = 32,
106 .n_region = 4, 117 .n_region = 4,
107 .n_slot = 128, 118 .n_slot = 128,
108 .n_tc = 2, 119 .n_tc = 2,
109 .n_cc = 1, 120 .n_cc = 1,
110 .noevent = da8xx_dma_chan_no_event,
111 .queue_tc_mapping = da8xx_queue_tc_mapping, 121 .queue_tc_mapping = da8xx_queue_tc_mapping,
112 .queue_priority_mapping = da8xx_queue_priority_mapping, 122 .queue_priority_mapping = da8xx_queue_priority_mapping,
113 }, 123 },
114}; 124};
115 125
116static struct resource da8xx_edma_resources[] = { 126static struct edma_soc_info da850_edma_info[] = {
127 {
128 .n_channel = 32,
129 .n_region = 4,
130 .n_slot = 128,
131 .n_tc = 2,
132 .n_cc = 1,
133 .queue_tc_mapping = da8xx_queue_tc_mapping,
134 .queue_priority_mapping = da8xx_queue_priority_mapping,
135 },
136 {
137 .n_channel = 32,
138 .n_region = 4,
139 .n_slot = 128,
140 .n_tc = 1,
141 .n_cc = 1,
142 .queue_tc_mapping = da850_queue_tc_mapping,
143 .queue_priority_mapping = da850_queue_priority_mapping,
144 },
145};
146
147static struct resource da830_edma_resources[] = {
117 { 148 {
118 .name = "edma_cc0", 149 .name = "edma_cc0",
119 .start = DA8XX_TPCC_BASE, 150 .start = DA8XX_TPCC_BASE,
@@ -144,19 +175,91 @@ static struct resource da8xx_edma_resources[] = {
144 }, 175 },
145}; 176};
146 177
147static struct platform_device da8xx_edma_device = { 178static struct resource da850_edma_resources[] = {
179 {
180 .name = "edma_cc0",
181 .start = DA8XX_TPCC_BASE,
182 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
183 .flags = IORESOURCE_MEM,
184 },
185 {
186 .name = "edma_tc0",
187 .start = DA8XX_TPTC0_BASE,
188 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .name = "edma_tc1",
193 .start = DA8XX_TPTC1_BASE,
194 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 {
198 .name = "edma_cc1",
199 .start = DA850_TPCC1_BASE,
200 .end = DA850_TPCC1_BASE + SZ_32K - 1,
201 .flags = IORESOURCE_MEM,
202 },
203 {
204 .name = "edma_tc2",
205 .start = DA850_TPTC2_BASE,
206 .end = DA850_TPTC2_BASE + SZ_1K - 1,
207 .flags = IORESOURCE_MEM,
208 },
209 {
210 .name = "edma0",
211 .start = IRQ_DA8XX_CCINT0,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "edma0_err",
216 .start = IRQ_DA8XX_CCERRINT,
217 .flags = IORESOURCE_IRQ,
218 },
219 {
220 .name = "edma1",
221 .start = IRQ_DA850_CCINT1,
222 .flags = IORESOURCE_IRQ,
223 },
224 {
225 .name = "edma1_err",
226 .start = IRQ_DA850_CCERRINT1,
227 .flags = IORESOURCE_IRQ,
228 },
229};
230
231static struct platform_device da830_edma_device = {
148 .name = "edma", 232 .name = "edma",
149 .id = -1, 233 .id = -1,
150 .dev = { 234 .dev = {
151 .platform_data = da8xx_edma_info, 235 .platform_data = da830_edma_info,
152 }, 236 },
153 .num_resources = ARRAY_SIZE(da8xx_edma_resources), 237 .num_resources = ARRAY_SIZE(da830_edma_resources),
154 .resource = da8xx_edma_resources, 238 .resource = da830_edma_resources,
239};
240
241static struct platform_device da850_edma_device = {
242 .name = "edma",
243 .id = -1,
244 .dev = {
245 .platform_data = da850_edma_info,
246 },
247 .num_resources = ARRAY_SIZE(da850_edma_resources),
248 .resource = da850_edma_resources,
155}; 249};
156 250
157int __init da8xx_register_edma(void) 251int __init da8xx_register_edma(void)
158{ 252{
159 return platform_device_register(&da8xx_edma_device); 253 struct platform_device *pdev;
254
255 if (cpu_is_davinci_da830())
256 pdev = &da830_edma_device;
257 else if (cpu_is_davinci_da850())
258 pdev = &da850_edma_device;
259 else
260 return -ENODEV;
261
262 return platform_device_register(pdev);
160} 263}
161 264
162static struct resource da8xx_i2c_resources0[] = { 265static struct resource da8xx_i2c_resources0[] = {
@@ -282,6 +385,11 @@ static struct platform_device da8xx_emac_device = {
282 .resource = da8xx_emac_resources, 385 .resource = da8xx_emac_resources,
283}; 386};
284 387
388int __init da8xx_register_emac(void)
389{
390 return platform_device_register(&da8xx_emac_device);
391}
392
285static struct resource da830_mcasp1_resources[] = { 393static struct resource da830_mcasp1_resources[] = {
286 { 394 {
287 .name = "mcasp1", 395 .name = "mcasp1",
@@ -338,12 +446,7 @@ static struct platform_device da850_mcasp_device = {
338 .resource = da850_mcasp_resources, 446 .resource = da850_mcasp_resources,
339}; 447};
340 448
341int __init da8xx_register_emac(void) 449void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
342{
343 return platform_device_register(&da8xx_emac_device);
344}
345
346void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata)
347{ 450{
348 /* DA830/OMAP-L137 has 3 instances of McASP */ 451 /* DA830/OMAP-L137 has 3 instances of McASP */
349 if (cpu_is_davinci_da830() && id == 1) { 452 if (cpu_is_davinci_da830() && id == 1) {
@@ -379,10 +482,16 @@ static struct lcd_ctrl_config lcd_cfg = {
379 .raster_order = 0, 482 .raster_order = 0,
380}; 483};
381 484
382static struct da8xx_lcdc_platform_data da850_evm_lcdc_pdata = { 485struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
383 .manu_name = "sharp", 486 .manu_name = "sharp",
384 .controller_data = &lcd_cfg, 487 .controller_data = &lcd_cfg,
385 .type = "Sharp_LK043T1DG01", 488 .type = "Sharp_LCD035Q3DG01",
489};
490
491struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
492 .manu_name = "sharp",
493 .controller_data = &lcd_cfg,
494 .type = "Sharp_LK043T1DG01",
386}; 495};
387 496
388static struct resource da8xx_lcdc_resources[] = { 497static struct resource da8xx_lcdc_resources[] = {
@@ -398,19 +507,17 @@ static struct resource da8xx_lcdc_resources[] = {
398 }, 507 },
399}; 508};
400 509
401static struct platform_device da850_lcdc_device = { 510static struct platform_device da8xx_lcdc_device = {
402 .name = "da8xx_lcdc", 511 .name = "da8xx_lcdc",
403 .id = 0, 512 .id = 0,
404 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources), 513 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
405 .resource = da8xx_lcdc_resources, 514 .resource = da8xx_lcdc_resources,
406 .dev = {
407 .platform_data = &da850_evm_lcdc_pdata,
408 }
409}; 515};
410 516
411int __init da8xx_register_lcdc(void) 517int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
412{ 518{
413 return platform_device_register(&da850_lcdc_device); 519 da8xx_lcdc_device.dev.platform_data = pdata;
520 return platform_device_register(&da8xx_lcdc_device);
414} 521}
415 522
416static struct resource da8xx_mmcsd0_resources[] = { 523static struct resource da8xx_mmcsd0_resources[] = {
@@ -448,3 +555,87 @@ int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
448 da8xx_mmcsd0_device.dev.platform_data = config; 555 da8xx_mmcsd0_device.dev.platform_data = config;
449 return platform_device_register(&da8xx_mmcsd0_device); 556 return platform_device_register(&da8xx_mmcsd0_device);
450} 557}
558
559static struct resource da8xx_rtc_resources[] = {
560 {
561 .start = DA8XX_RTC_BASE,
562 .end = DA8XX_RTC_BASE + SZ_4K - 1,
563 .flags = IORESOURCE_MEM,
564 },
565 { /* timer irq */
566 .start = IRQ_DA8XX_RTC,
567 .end = IRQ_DA8XX_RTC,
568 .flags = IORESOURCE_IRQ,
569 },
570 { /* alarm irq */
571 .start = IRQ_DA8XX_RTC,
572 .end = IRQ_DA8XX_RTC,
573 .flags = IORESOURCE_IRQ,
574 },
575};
576
577static struct platform_device da8xx_rtc_device = {
578 .name = "omap_rtc",
579 .id = -1,
580 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
581 .resource = da8xx_rtc_resources,
582};
583
584int da8xx_register_rtc(void)
585{
586 int ret;
587
588 /* Unlock the rtc's registers */
589 __raw_writel(0x83e70b13, IO_ADDRESS(DA8XX_RTC_BASE + 0x6c));
590 __raw_writel(0x95a4f1e0, IO_ADDRESS(DA8XX_RTC_BASE + 0x70));
591
592 ret = platform_device_register(&da8xx_rtc_device);
593 if (!ret)
594 /* Atleast on DA850, RTC is a wakeup source */
595 device_init_wakeup(&da8xx_rtc_device.dev, true);
596
597 return ret;
598}
599
600static void __iomem *da8xx_ddr2_ctlr_base;
601void __iomem * __init da8xx_get_mem_ctlr(void)
602{
603 if (da8xx_ddr2_ctlr_base)
604 return da8xx_ddr2_ctlr_base;
605
606 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
607 if (!da8xx_ddr2_ctlr_base)
608 pr_warning("%s: Unable to map DDR2 controller", __func__);
609
610 return da8xx_ddr2_ctlr_base;
611}
612
613static struct resource da8xx_cpuidle_resources[] = {
614 {
615 .start = DA8XX_DDR2_CTL_BASE,
616 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
617 .flags = IORESOURCE_MEM,
618 },
619};
620
621/* DA8XX devices support DDR2 power down */
622static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
623 .ddr2_pdown = 1,
624};
625
626
627static struct platform_device da8xx_cpuidle_device = {
628 .name = "cpuidle-davinci",
629 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
630 .resource = da8xx_cpuidle_resources,
631 .dev = {
632 .platform_data = &da8xx_cpuidle_pdata,
633 },
634};
635
636int __init da8xx_register_cpuidle(void)
637{
638 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
639
640 return platform_device_register(&da8xx_cpuidle_device);
641}
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a55b650db71e..147949650c25 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -9,15 +9,11 @@
9 * (at your option) any later version. 9 * (at your option) any later version.
10 */ 10 */
11 11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h> 12#include <linux/init.h>
15#include <linux/platform_device.h> 13#include <linux/platform_device.h>
16#include <linux/dma-mapping.h> 14#include <linux/dma-mapping.h>
17#include <linux/io.h> 15#include <linux/io.h>
18 16
19#include <asm/mach/map.h>
20
21#include <mach/hardware.h> 17#include <mach/hardware.h>
22#include <mach/i2c.h> 18#include <mach/i2c.h>
23#include <mach/irqs.h> 19#include <mach/irqs.h>
@@ -177,7 +173,7 @@ void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
177 mmcsd1_resources[0].start = DM365_MMCSD1_BASE; 173 mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
178 mmcsd1_resources[0].end = DM365_MMCSD1_BASE + 174 mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
179 SZ_4K - 1; 175 SZ_4K - 1;
180 mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1; 176 mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
181 } else 177 } else
182 break; 178 break;
183 179
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 059670018aff..3dc0a88712eb 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -8,7 +8,6 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/serial_8250.h> 13#include <linux/serial_8250.h>
@@ -21,7 +20,6 @@
21#include <asm/mach/map.h> 20#include <asm/mach/map.h>
22 21
23#include <mach/dm355.h> 22#include <mach/dm355.h>
24#include <mach/clock.h>
25#include <mach/cputype.h> 23#include <mach/cputype.h>
26#include <mach/edma.h> 24#include <mach/edma.h>
27#include <mach/psc.h> 25#include <mach/psc.h>
@@ -31,6 +29,7 @@
31#include <mach/serial.h> 29#include <mach/serial.h>
32#include <mach/common.h> 30#include <mach/common.h>
33#include <mach/asp.h> 31#include <mach/asp.h>
32#include <mach/spi.h>
34 33
35#include "clock.h" 34#include "clock.h"
36#include "mux.h" 35#include "mux.h"
@@ -127,7 +126,6 @@ static struct clk vpss_slave_clk = {
127 .lpsc = DAVINCI_LPSC_VPSSSLV, 126 .lpsc = DAVINCI_LPSC_VPSSSLV,
128}; 127};
129 128
130
131static struct clk clkout1_clk = { 129static struct clk clkout1_clk = {
132 .name = "clkout1", 130 .name = "clkout1",
133 .parent = &pll1_aux_clk, 131 .parent = &pll1_aux_clk,
@@ -337,7 +335,7 @@ static struct clk usb_clk = {
337 .lpsc = DAVINCI_LPSC_USB, 335 .lpsc = DAVINCI_LPSC_USB,
338}; 336};
339 337
340static struct davinci_clk dm355_clks[] = { 338static struct clk_lookup dm355_clks[] = {
341 CLK(NULL, "ref", &ref_clk), 339 CLK(NULL, "ref", &ref_clk),
342 CLK(NULL, "pll1", &pll1_clk), 340 CLK(NULL, "pll1", &pll1_clk),
343 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), 341 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -365,9 +363,9 @@ static struct davinci_clk dm355_clks[] = {
365 CLK("davinci-asp.1", NULL, &asp1_clk), 363 CLK("davinci-asp.1", NULL, &asp1_clk),
366 CLK("davinci_mmc.0", NULL, &mmcsd0_clk), 364 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
367 CLK("davinci_mmc.1", NULL, &mmcsd1_clk), 365 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
368 CLK(NULL, "spi0", &spi0_clk), 366 CLK("spi_davinci.0", NULL, &spi0_clk),
369 CLK(NULL, "spi1", &spi1_clk), 367 CLK("spi_davinci.1", NULL, &spi1_clk),
370 CLK(NULL, "spi2", &spi2_clk), 368 CLK("spi_davinci.2", NULL, &spi2_clk),
371 CLK(NULL, "gpio", &gpio_clk), 369 CLK(NULL, "gpio", &gpio_clk),
372 CLK(NULL, "aemif", &aemif_clk), 370 CLK(NULL, "aemif", &aemif_clk),
373 CLK(NULL, "pwm0", &pwm0_clk), 371 CLK(NULL, "pwm0", &pwm0_clk),
@@ -394,24 +392,40 @@ static struct resource dm355_spi0_resources[] = {
394 .flags = IORESOURCE_MEM, 392 .flags = IORESOURCE_MEM,
395 }, 393 },
396 { 394 {
397 .start = IRQ_DM355_SPINT0_1, 395 .start = IRQ_DM355_SPINT0_0,
398 .flags = IORESOURCE_IRQ, 396 .flags = IORESOURCE_IRQ,
399 }, 397 },
400 /* Not yet used, so not included: 398 {
401 * IORESOURCE_IRQ: 399 .start = 17,
402 * - IRQ_DM355_SPINT0_0 400 .flags = IORESOURCE_DMA,
403 * IORESOURCE_DMA: 401 },
404 * - DAVINCI_DMA_SPI_SPIX 402 {
405 * - DAVINCI_DMA_SPI_SPIR 403 .start = 16,
406 */ 404 .flags = IORESOURCE_DMA,
405 },
406 {
407 .start = EVENTQ_1,
408 .flags = IORESOURCE_DMA,
409 },
407}; 410};
408 411
412static struct davinci_spi_platform_data dm355_spi0_pdata = {
413 .version = SPI_VERSION_1,
414 .num_chipselect = 2,
415 .clk_internal = 1,
416 .cs_hold = 1,
417 .intr_level = 0,
418 .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
419 .c2tdelay = 0,
420 .t2cdelay = 0,
421};
409static struct platform_device dm355_spi0_device = { 422static struct platform_device dm355_spi0_device = {
410 .name = "spi_davinci", 423 .name = "spi_davinci",
411 .id = 0, 424 .id = 0,
412 .dev = { 425 .dev = {
413 .dma_mask = &dm355_spi0_dma_mask, 426 .dma_mask = &dm355_spi0_dma_mask,
414 .coherent_dma_mask = DMA_BIT_MASK(32), 427 .coherent_dma_mask = DMA_BIT_MASK(32),
428 .platform_data = &dm355_spi0_pdata,
415 }, 429 },
416 .num_resources = ARRAY_SIZE(dm355_spi0_resources), 430 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
417 .resource = dm355_spi0_resources, 431 .resource = dm355_spi0_resources,
@@ -566,13 +580,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
566 580
567/*----------------------------------------------------------------------*/ 581/*----------------------------------------------------------------------*/
568 582
569static const s8 dma_chan_dm355_no_event[] = {
570 12, 13, 24, 56, 57,
571 58, 59, 60, 61, 62,
572 63,
573 -1
574};
575
576static const s8 583static const s8
577queue_tc_mapping[][2] = { 584queue_tc_mapping[][2] = {
578 /* {event queue no, TC no} */ 585 /* {event queue no, TC no} */
@@ -596,7 +603,6 @@ static struct edma_soc_info dm355_edma_info[] = {
596 .n_slot = 128, 603 .n_slot = 128,
597 .n_tc = 2, 604 .n_tc = 2,
598 .n_cc = 1, 605 .n_cc = 1,
599 .noevent = dma_chan_dm355_no_event,
600 .queue_tc_mapping = queue_tc_mapping, 606 .queue_tc_mapping = queue_tc_mapping,
601 .queue_priority_mapping = queue_priority_mapping, 607 .queue_priority_mapping = queue_priority_mapping,
602 }, 608 },
@@ -667,6 +673,17 @@ static struct platform_device dm355_asp1_device = {
667 .resource = dm355_asp1_resources, 673 .resource = dm355_asp1_resources,
668}; 674};
669 675
676static void dm355_ccdc_setup_pinmux(void)
677{
678 davinci_cfg_reg(DM355_VIN_PCLK);
679 davinci_cfg_reg(DM355_VIN_CAM_WEN);
680 davinci_cfg_reg(DM355_VIN_CAM_VD);
681 davinci_cfg_reg(DM355_VIN_CAM_HD);
682 davinci_cfg_reg(DM355_VIN_YIN_EN);
683 davinci_cfg_reg(DM355_VIN_CINL_EN);
684 davinci_cfg_reg(DM355_VIN_CINH_EN);
685}
686
670static struct resource dm355_vpss_resources[] = { 687static struct resource dm355_vpss_resources[] = {
671 { 688 {
672 /* VPSS BL Base address */ 689 /* VPSS BL Base address */
@@ -703,6 +720,10 @@ static struct resource vpfe_resources[] = {
703 .end = IRQ_VDINT1, 720 .end = IRQ_VDINT1,
704 .flags = IORESOURCE_IRQ, 721 .flags = IORESOURCE_IRQ,
705 }, 722 },
723};
724
725static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
726static struct resource dm355_ccdc_resource[] = {
706 /* CCDC Base address */ 727 /* CCDC Base address */
707 { 728 {
708 .flags = IORESOURCE_MEM, 729 .flags = IORESOURCE_MEM,
@@ -710,8 +731,18 @@ static struct resource vpfe_resources[] = {
710 .end = 0x01c70600 + 0x1ff, 731 .end = 0x01c70600 + 0x1ff,
711 }, 732 },
712}; 733};
734static struct platform_device dm355_ccdc_dev = {
735 .name = "dm355_ccdc",
736 .id = -1,
737 .num_resources = ARRAY_SIZE(dm355_ccdc_resource),
738 .resource = dm355_ccdc_resource,
739 .dev = {
740 .dma_mask = &vpfe_capture_dma_mask,
741 .coherent_dma_mask = DMA_BIT_MASK(32),
742 .platform_data = dm355_ccdc_setup_pinmux,
743 },
744};
713 745
714static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
715static struct platform_device vpfe_capture_dev = { 746static struct platform_device vpfe_capture_dev = {
716 .name = CAPTURE_DRV_NAME, 747 .name = CAPTURE_DRV_NAME,
717 .id = -1, 748 .id = -1,
@@ -859,20 +890,13 @@ static int __init dm355_init_devices(void)
859 if (!cpu_is_davinci_dm355()) 890 if (!cpu_is_davinci_dm355())
860 return 0; 891 return 0;
861 892
893 /* Add ccdc clock aliases */
894 clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
895 clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
862 davinci_cfg_reg(DM355_INT_EDMA_CC); 896 davinci_cfg_reg(DM355_INT_EDMA_CC);
863 platform_device_register(&dm355_edma_device); 897 platform_device_register(&dm355_edma_device);
864 platform_device_register(&dm355_vpss_device); 898 platform_device_register(&dm355_vpss_device);
865 /* 899 platform_device_register(&dm355_ccdc_dev);
866 * setup Mux configuration for vpfe input and register
867 * vpfe capture platform device
868 */
869 davinci_cfg_reg(DM355_VIN_PCLK);
870 davinci_cfg_reg(DM355_VIN_CAM_WEN);
871 davinci_cfg_reg(DM355_VIN_CAM_VD);
872 davinci_cfg_reg(DM355_VIN_CAM_HD);
873 davinci_cfg_reg(DM355_VIN_YIN_EN);
874 davinci_cfg_reg(DM355_VIN_CINL_EN);
875 davinci_cfg_reg(DM355_VIN_CINH_EN);
876 platform_device_register(&vpfe_capture_dev); 900 platform_device_register(&vpfe_capture_dev);
877 901
878 return 0; 902 return 0;
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index e81517434703..0d6ee583f65c 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -12,18 +12,17 @@
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15#include <linux/kernel.h>
16#include <linux/init.h> 15#include <linux/init.h>
17#include <linux/clk.h> 16#include <linux/clk.h>
18#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
19#include <linux/platform_device.h> 18#include <linux/platform_device.h>
20#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
21#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/spi/spi.h>
22 22
23#include <asm/mach/map.h> 23#include <asm/mach/map.h>
24 24
25#include <mach/dm365.h> 25#include <mach/dm365.h>
26#include <mach/clock.h>
27#include <mach/cputype.h> 26#include <mach/cputype.h>
28#include <mach/edma.h> 27#include <mach/edma.h>
29#include <mach/psc.h> 28#include <mach/psc.h>
@@ -32,6 +31,10 @@
32#include <mach/time.h> 31#include <mach/time.h>
33#include <mach/serial.h> 32#include <mach/serial.h>
34#include <mach/common.h> 33#include <mach/common.h>
34#include <mach/asp.h>
35#include <mach/keyscan.h>
36#include <mach/spi.h>
37
35 38
36#include "clock.h" 39#include "clock.h"
37#include "mux.h" 40#include "mux.h"
@@ -369,7 +372,7 @@ static struct clk timer3_clk = {
369 372
370static struct clk usb_clk = { 373static struct clk usb_clk = {
371 .name = "usb", 374 .name = "usb",
372 .parent = &pll2_sysclk1, 375 .parent = &pll1_aux_clk,
373 .lpsc = DAVINCI_LPSC_USB, 376 .lpsc = DAVINCI_LPSC_USB,
374}; 377};
375 378
@@ -403,7 +406,7 @@ static struct clk mjcp_clk = {
403 .lpsc = DM365_LPSC_MJCP, 406 .lpsc = DM365_LPSC_MJCP,
404}; 407};
405 408
406static struct davinci_clk dm365_clks[] = { 409static struct clk_lookup dm365_clks[] = {
407 CLK(NULL, "ref", &ref_clk), 410 CLK(NULL, "ref", &ref_clk),
408 CLK(NULL, "pll1", &pll1_clk), 411 CLK(NULL, "pll1", &pll1_clk),
409 CLK(NULL, "pll1_aux", &pll1_aux_clk), 412 CLK(NULL, "pll1_aux", &pll1_aux_clk),
@@ -455,8 +458,8 @@ static struct davinci_clk dm365_clks[] = {
455 CLK(NULL, "timer3", &timer3_clk), 458 CLK(NULL, "timer3", &timer3_clk),
456 CLK(NULL, "usb", &usb_clk), 459 CLK(NULL, "usb", &usb_clk),
457 CLK("davinci_emac.1", NULL, &emac_clk), 460 CLK("davinci_emac.1", NULL, &emac_clk),
458 CLK("voice_codec", NULL, &voicecodec_clk), 461 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
459 CLK("soc-audio.0", NULL, &asp0_clk), 462 CLK("davinci-asp.0", NULL, &asp0_clk),
460 CLK(NULL, "rto", &rto_clk), 463 CLK(NULL, "rto", &rto_clk),
461 CLK(NULL, "mjcp", &mjcp_clk), 464 CLK(NULL, "mjcp", &mjcp_clk),
462 CLK(NULL, NULL, NULL), 465 CLK(NULL, NULL, NULL),
@@ -531,7 +534,7 @@ MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
531MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false) 534MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
532MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false) 535MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
533 536
534MUX_CFG(DM365, KEYPAD, 2, 0, 0x3f, 0x3f, false) 537MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
535 538
536MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false) 539MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
537MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false) 540MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
@@ -603,9 +606,81 @@ INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
603INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false) 606INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
604INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false) 607INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
605INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false) 608INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
609
610EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
611EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
612EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
613EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
606#endif 614#endif
607}; 615};
608 616
617static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
618
619static struct davinci_spi_platform_data dm365_spi0_pdata = {
620 .version = SPI_VERSION_1,
621 .num_chipselect = 2,
622 .clk_internal = 1,
623 .cs_hold = 1,
624 .intr_level = 0,
625 .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
626 .c2tdelay = 0,
627 .t2cdelay = 0,
628};
629
630static struct resource dm365_spi0_resources[] = {
631 {
632 .start = 0x01c66000,
633 .end = 0x01c667ff,
634 .flags = IORESOURCE_MEM,
635 },
636 {
637 .start = IRQ_DM365_SPIINT0_0,
638 .flags = IORESOURCE_IRQ,
639 },
640 {
641 .start = 17,
642 .flags = IORESOURCE_DMA,
643 },
644 {
645 .start = 16,
646 .flags = IORESOURCE_DMA,
647 },
648 {
649 .start = EVENTQ_3,
650 .flags = IORESOURCE_DMA,
651 },
652};
653
654static struct platform_device dm365_spi0_device = {
655 .name = "spi_davinci",
656 .id = 0,
657 .dev = {
658 .dma_mask = &dm365_spi0_dma_mask,
659 .coherent_dma_mask = DMA_BIT_MASK(32),
660 .platform_data = &dm365_spi0_pdata,
661 },
662 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
663 .resource = dm365_spi0_resources,
664};
665
666void __init dm365_init_spi0(unsigned chipselect_mask,
667 struct spi_board_info *info, unsigned len)
668{
669 davinci_cfg_reg(DM365_SPI0_SCLK);
670 davinci_cfg_reg(DM365_SPI0_SDI);
671 davinci_cfg_reg(DM365_SPI0_SDO);
672
673 /* not all slaves will be wired up */
674 if (chipselect_mask & BIT(0))
675 davinci_cfg_reg(DM365_SPI0_SDENA0);
676 if (chipselect_mask & BIT(1))
677 davinci_cfg_reg(DM365_SPI0_SDENA1);
678
679 spi_register_board_info(info, len);
680
681 platform_device_register(&dm365_spi0_device);
682}
683
609static struct emac_platform_data dm365_emac_pdata = { 684static struct emac_platform_data dm365_emac_pdata = {
610 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, 685 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
611 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, 686 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
@@ -683,7 +758,6 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
683 [IRQ_MMCINT] = 7, 758 [IRQ_MMCINT] = 7,
684 [IRQ_DM365_MMCINT1] = 7, 759 [IRQ_DM365_MMCINT1] = 7,
685 [IRQ_DM365_PWMINT3] = 7, 760 [IRQ_DM365_PWMINT3] = 7,
686 [IRQ_DDRINT] = 4,
687 [IRQ_AEMIFINT] = 2, 761 [IRQ_AEMIFINT] = 2,
688 [IRQ_DM365_SDIOINT1] = 2, 762 [IRQ_DM365_SDIOINT1] = 2,
689 [IRQ_TINT0_TINT12] = 7, 763 [IRQ_TINT0_TINT12] = 7,
@@ -696,6 +770,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
696 [IRQ_I2C] = 3, 770 [IRQ_I2C] = 3,
697 [IRQ_UARTINT0] = 3, 771 [IRQ_UARTINT0] = 3,
698 [IRQ_UARTINT1] = 3, 772 [IRQ_UARTINT1] = 3,
773 [IRQ_DM365_RTCINT] = 3,
699 [IRQ_DM365_SPIINT0_0] = 3, 774 [IRQ_DM365_SPIINT0_0] = 3,
700 [IRQ_DM365_SPIINT3_0] = 3, 775 [IRQ_DM365_SPIINT3_0] = 3,
701 [IRQ_DM365_GPIO0] = 3, 776 [IRQ_DM365_GPIO0] = 3,
@@ -750,7 +825,7 @@ static struct edma_soc_info dm365_edma_info[] = {
750 .n_cc = 1, 825 .n_cc = 1,
751 .queue_tc_mapping = dm365_queue_tc_mapping, 826 .queue_tc_mapping = dm365_queue_tc_mapping,
752 .queue_priority_mapping = dm365_queue_priority_mapping, 827 .queue_priority_mapping = dm365_queue_priority_mapping,
753 .default_queue = EVENTQ_2, 828 .default_queue = EVENTQ_3,
754 }, 829 },
755}; 830};
756 831
@@ -806,6 +881,75 @@ static struct platform_device dm365_edma_device = {
806 .resource = edma_resources, 881 .resource = edma_resources,
807}; 882};
808 883
884static struct resource dm365_asp_resources[] = {
885 {
886 .start = DAVINCI_DM365_ASP0_BASE,
887 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
888 .flags = IORESOURCE_MEM,
889 },
890 {
891 .start = DAVINCI_DMA_ASP0_TX,
892 .end = DAVINCI_DMA_ASP0_TX,
893 .flags = IORESOURCE_DMA,
894 },
895 {
896 .start = DAVINCI_DMA_ASP0_RX,
897 .end = DAVINCI_DMA_ASP0_RX,
898 .flags = IORESOURCE_DMA,
899 },
900};
901
902static struct platform_device dm365_asp_device = {
903 .name = "davinci-asp",
904 .id = 0,
905 .num_resources = ARRAY_SIZE(dm365_asp_resources),
906 .resource = dm365_asp_resources,
907};
908
909static struct resource dm365_vc_resources[] = {
910 {
911 .start = DAVINCI_DM365_VC_BASE,
912 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
913 .flags = IORESOURCE_MEM,
914 },
915 {
916 .start = DAVINCI_DMA_VC_TX,
917 .end = DAVINCI_DMA_VC_TX,
918 .flags = IORESOURCE_DMA,
919 },
920 {
921 .start = DAVINCI_DMA_VC_RX,
922 .end = DAVINCI_DMA_VC_RX,
923 .flags = IORESOURCE_DMA,
924 },
925};
926
927static struct platform_device dm365_vc_device = {
928 .name = "davinci_voicecodec",
929 .id = -1,
930 .num_resources = ARRAY_SIZE(dm365_vc_resources),
931 .resource = dm365_vc_resources,
932};
933
934static struct resource dm365_rtc_resources[] = {
935 {
936 .start = DM365_RTC_BASE,
937 .end = DM365_RTC_BASE + SZ_1K - 1,
938 .flags = IORESOURCE_MEM,
939 },
940 {
941 .start = IRQ_DM365_RTCINT,
942 .flags = IORESOURCE_IRQ,
943 },
944};
945
946static struct platform_device dm365_rtc_device = {
947 .name = "rtc_davinci",
948 .id = 0,
949 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
950 .resource = dm365_rtc_resources,
951};
952
809static struct map_desc dm365_io_desc[] = { 953static struct map_desc dm365_io_desc[] = {
810 { 954 {
811 .virtual = IO_VIRT, 955 .virtual = IO_VIRT,
@@ -822,6 +966,28 @@ static struct map_desc dm365_io_desc[] = {
822 }, 966 },
823}; 967};
824 968
969static struct resource dm365_ks_resources[] = {
970 {
971 /* registers */
972 .start = DM365_KEYSCAN_BASE,
973 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
974 .flags = IORESOURCE_MEM,
975 },
976 {
977 /* interrupt */
978 .start = IRQ_DM365_KEYINT,
979 .end = IRQ_DM365_KEYINT,
980 .flags = IORESOURCE_IRQ,
981 },
982};
983
984static struct platform_device dm365_ks_device = {
985 .name = "davinci_keyscan",
986 .id = 0,
987 .num_resources = ARRAY_SIZE(dm365_ks_resources),
988 .resource = dm365_ks_resources,
989};
990
825/* Contents of JTAG ID register used to identify exact cpu type */ 991/* Contents of JTAG ID register used to identify exact cpu type */
826static struct davinci_id dm365_ids[] = { 992static struct davinci_id dm365_ids[] = {
827 { 993 {
@@ -907,11 +1073,136 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
907 .sram_len = SZ_32K, 1073 .sram_len = SZ_32K,
908}; 1074};
909 1075
1076void __init dm365_init_asp(struct snd_platform_data *pdata)
1077{
1078 davinci_cfg_reg(DM365_MCBSP0_BDX);
1079 davinci_cfg_reg(DM365_MCBSP0_X);
1080 davinci_cfg_reg(DM365_MCBSP0_BFSX);
1081 davinci_cfg_reg(DM365_MCBSP0_BDR);
1082 davinci_cfg_reg(DM365_MCBSP0_R);
1083 davinci_cfg_reg(DM365_MCBSP0_BFSR);
1084 davinci_cfg_reg(DM365_EVT2_ASP_TX);
1085 davinci_cfg_reg(DM365_EVT3_ASP_RX);
1086 dm365_asp_device.dev.platform_data = pdata;
1087 platform_device_register(&dm365_asp_device);
1088}
1089
1090void __init dm365_init_vc(struct snd_platform_data *pdata)
1091{
1092 davinci_cfg_reg(DM365_EVT2_VC_TX);
1093 davinci_cfg_reg(DM365_EVT3_VC_RX);
1094 dm365_vc_device.dev.platform_data = pdata;
1095 platform_device_register(&dm365_vc_device);
1096}
1097
1098void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1099{
1100 dm365_ks_device.dev.platform_data = pdata;
1101 platform_device_register(&dm365_ks_device);
1102}
1103
1104void __init dm365_init_rtc(void)
1105{
1106 davinci_cfg_reg(DM365_INT_PRTCSS);
1107 platform_device_register(&dm365_rtc_device);
1108}
1109
910void __init dm365_init(void) 1110void __init dm365_init(void)
911{ 1111{
912 davinci_common_init(&davinci_soc_info_dm365); 1112 davinci_common_init(&davinci_soc_info_dm365);
913} 1113}
914 1114
1115static struct resource dm365_vpss_resources[] = {
1116 {
1117 /* VPSS ISP5 Base address */
1118 .name = "isp5",
1119 .start = 0x01c70000,
1120 .end = 0x01c70000 + 0xff,
1121 .flags = IORESOURCE_MEM,
1122 },
1123 {
1124 /* VPSS CLK Base address */
1125 .name = "vpss",
1126 .start = 0x01c70200,
1127 .end = 0x01c70200 + 0xff,
1128 .flags = IORESOURCE_MEM,
1129 },
1130};
1131
1132static struct platform_device dm365_vpss_device = {
1133 .name = "vpss",
1134 .id = -1,
1135 .dev.platform_data = "dm365_vpss",
1136 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
1137 .resource = dm365_vpss_resources,
1138};
1139
1140static struct resource vpfe_resources[] = {
1141 {
1142 .start = IRQ_VDINT0,
1143 .end = IRQ_VDINT0,
1144 .flags = IORESOURCE_IRQ,
1145 },
1146 {
1147 .start = IRQ_VDINT1,
1148 .end = IRQ_VDINT1,
1149 .flags = IORESOURCE_IRQ,
1150 },
1151};
1152
1153static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1154static struct platform_device vpfe_capture_dev = {
1155 .name = CAPTURE_DRV_NAME,
1156 .id = -1,
1157 .num_resources = ARRAY_SIZE(vpfe_resources),
1158 .resource = vpfe_resources,
1159 .dev = {
1160 .dma_mask = &vpfe_capture_dma_mask,
1161 .coherent_dma_mask = DMA_BIT_MASK(32),
1162 },
1163};
1164
1165static void dm365_isif_setup_pinmux(void)
1166{
1167 davinci_cfg_reg(DM365_VIN_CAM_WEN);
1168 davinci_cfg_reg(DM365_VIN_CAM_VD);
1169 davinci_cfg_reg(DM365_VIN_CAM_HD);
1170 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1171 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1172}
1173
1174static struct resource isif_resource[] = {
1175 /* ISIF Base address */
1176 {
1177 .start = 0x01c71000,
1178 .end = 0x01c71000 + 0x1ff,
1179 .flags = IORESOURCE_MEM,
1180 },
1181 /* ISIF Linearization table 0 */
1182 {
1183 .start = 0x1C7C000,
1184 .end = 0x1C7C000 + 0x2ff,
1185 .flags = IORESOURCE_MEM,
1186 },
1187 /* ISIF Linearization table 1 */
1188 {
1189 .start = 0x1C7C400,
1190 .end = 0x1C7C400 + 0x2ff,
1191 .flags = IORESOURCE_MEM,
1192 },
1193};
1194static struct platform_device dm365_isif_dev = {
1195 .name = "isif",
1196 .id = -1,
1197 .num_resources = ARRAY_SIZE(isif_resource),
1198 .resource = isif_resource,
1199 .dev = {
1200 .dma_mask = &vpfe_capture_dma_mask,
1201 .coherent_dma_mask = DMA_BIT_MASK(32),
1202 .platform_data = dm365_isif_setup_pinmux,
1203 },
1204};
1205
915static int __init dm365_init_devices(void) 1206static int __init dm365_init_devices(void)
916{ 1207{
917 if (!cpu_is_davinci_dm365()) 1208 if (!cpu_is_davinci_dm365())
@@ -920,7 +1211,16 @@ static int __init dm365_init_devices(void)
920 davinci_cfg_reg(DM365_INT_EDMA_CC); 1211 davinci_cfg_reg(DM365_INT_EDMA_CC);
921 platform_device_register(&dm365_edma_device); 1212 platform_device_register(&dm365_edma_device);
922 platform_device_register(&dm365_emac_device); 1213 platform_device_register(&dm365_emac_device);
923 1214 /* Add isif clock alias */
1215 clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
1216 platform_device_register(&dm365_vpss_device);
1217 platform_device_register(&dm365_isif_dev);
1218 platform_device_register(&vpfe_capture_dev);
924 return 0; 1219 return 0;
925} 1220}
926postcore_initcall(dm365_init_devices); 1221postcore_initcall(dm365_init_devices);
1222
1223void dm365_set_vpfe_config(struct vpfe_config *cfg)
1224{
1225 vpfe_capture_dev.dev.platform_data = cfg;
1226}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index d6e0fa5a8d8a..2f2ae8bc77bb 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -8,7 +8,6 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/serial_8250.h> 13#include <linux/serial_8250.h>
@@ -18,7 +17,6 @@
18#include <asm/mach/map.h> 17#include <asm/mach/map.h>
19 18
20#include <mach/dm644x.h> 19#include <mach/dm644x.h>
21#include <mach/clock.h>
22#include <mach/cputype.h> 20#include <mach/cputype.h>
23#include <mach/edma.h> 21#include <mach/edma.h>
24#include <mach/irqs.h> 22#include <mach/irqs.h>
@@ -279,7 +277,7 @@ static struct clk timer2_clk = {
279 .usecount = 1, /* REVISIT: why cant' this be disabled? */ 277 .usecount = 1, /* REVISIT: why cant' this be disabled? */
280}; 278};
281 279
282struct davinci_clk dm644x_clks[] = { 280struct clk_lookup dm644x_clks[] = {
283 CLK(NULL, "ref", &ref_clk), 281 CLK(NULL, "ref", &ref_clk),
284 CLK(NULL, "pll1", &pll1_clk), 282 CLK(NULL, "pll1", &pll1_clk),
285 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), 283 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -370,6 +368,11 @@ MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
370MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true) 368MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
371 369
372MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true) 370MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
371MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
372MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
373MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
374MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
375MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
373 376
374MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false) 377MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
375 378
@@ -476,15 +479,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
476 479
477/*----------------------------------------------------------------------*/ 480/*----------------------------------------------------------------------*/
478 481
479static const s8 dma_chan_dm644x_no_event[] = {
480 0, 1, 12, 13, 14,
481 15, 25, 30, 31, 45,
482 46, 47, 55, 56, 57,
483 58, 59, 60, 61, 62,
484 63,
485 -1
486};
487
488static const s8 482static const s8
489queue_tc_mapping[][2] = { 483queue_tc_mapping[][2] = {
490 /* {event queue no, TC no} */ 484 /* {event queue no, TC no} */
@@ -508,7 +502,6 @@ static struct edma_soc_info dm644x_edma_info[] = {
508 .n_slot = 128, 502 .n_slot = 128,
509 .n_tc = 2, 503 .n_tc = 2,
510 .n_cc = 1, 504 .n_cc = 1,
511 .noevent = dma_chan_dm644x_no_event,
512 .queue_tc_mapping = queue_tc_mapping, 505 .queue_tc_mapping = queue_tc_mapping,
513 .queue_priority_mapping = queue_priority_mapping, 506 .queue_priority_mapping = queue_priority_mapping,
514 }, 507 },
@@ -609,6 +602,11 @@ static struct resource vpfe_resources[] = {
609 .end = IRQ_VDINT1, 602 .end = IRQ_VDINT1,
610 .flags = IORESOURCE_IRQ, 603 .flags = IORESOURCE_IRQ,
611 }, 604 },
605};
606
607static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
608static struct resource dm644x_ccdc_resource[] = {
609 /* CCDC Base address */
612 { 610 {
613 .start = 0x01c70400, 611 .start = 0x01c70400,
614 .end = 0x01c70400 + 0xff, 612 .end = 0x01c70400 + 0xff,
@@ -616,7 +614,17 @@ static struct resource vpfe_resources[] = {
616 }, 614 },
617}; 615};
618 616
619static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); 617static struct platform_device dm644x_ccdc_dev = {
618 .name = "dm644x_ccdc",
619 .id = -1,
620 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
621 .resource = dm644x_ccdc_resource,
622 .dev = {
623 .dma_mask = &vpfe_capture_dma_mask,
624 .coherent_dma_mask = DMA_BIT_MASK(32),
625 },
626};
627
620static struct platform_device vpfe_capture_dev = { 628static struct platform_device vpfe_capture_dev = {
621 .name = CAPTURE_DRV_NAME, 629 .name = CAPTURE_DRV_NAME,
622 .id = -1, 630 .id = -1,
@@ -766,9 +774,13 @@ static int __init dm644x_init_devices(void)
766 if (!cpu_is_davinci_dm644x()) 774 if (!cpu_is_davinci_dm644x())
767 return 0; 775 return 0;
768 776
777 /* Add ccdc clock aliases */
778 clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
779 clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
769 platform_device_register(&dm644x_edma_device); 780 platform_device_register(&dm644x_edma_device);
770 platform_device_register(&dm644x_emac_device); 781 platform_device_register(&dm644x_emac_device);
771 platform_device_register(&dm644x_vpss_device); 782 platform_device_register(&dm644x_vpss_device);
783 platform_device_register(&dm644x_ccdc_dev);
772 platform_device_register(&vpfe_capture_dev); 784 platform_device_register(&vpfe_capture_dev);
773 785
774 return 0; 786 return 0;
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 0976049c7b3b..893baf4ad37d 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -8,7 +8,6 @@
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
10 */ 10 */
11#include <linux/kernel.h>
12#include <linux/init.h> 11#include <linux/init.h>
13#include <linux/clk.h> 12#include <linux/clk.h>
14#include <linux/serial_8250.h> 13#include <linux/serial_8250.h>
@@ -18,7 +17,6 @@
18#include <asm/mach/map.h> 17#include <asm/mach/map.h>
19 18
20#include <mach/dm646x.h> 19#include <mach/dm646x.h>
21#include <mach/clock.h>
22#include <mach/cputype.h> 20#include <mach/cputype.h>
23#include <mach/edma.h> 21#include <mach/edma.h>
24#include <mach/irqs.h> 22#include <mach/irqs.h>
@@ -44,7 +42,6 @@
44/* 42/*
45 * Device specific clocks 43 * Device specific clocks
46 */ 44 */
47#define DM646X_REF_FREQ 27000000
48#define DM646X_AUX_FREQ 24000000 45#define DM646X_AUX_FREQ 24000000
49 46
50static struct pll_data pll1_data = { 47static struct pll_data pll1_data = {
@@ -59,7 +56,6 @@ static struct pll_data pll2_data = {
59 56
60static struct clk ref_clk = { 57static struct clk ref_clk = {
61 .name = "ref_clk", 58 .name = "ref_clk",
62 .rate = DM646X_REF_FREQ,
63}; 59};
64 60
65static struct clk aux_clkin = { 61static struct clk aux_clkin = {
@@ -315,7 +311,7 @@ static struct clk vpif1_clk = {
315 .flags = ALWAYS_ENABLED, 311 .flags = ALWAYS_ENABLED,
316}; 312};
317 313
318struct davinci_clk dm646x_clks[] = { 314struct clk_lookup dm646x_clks[] = {
319 CLK(NULL, "ref", &ref_clk), 315 CLK(NULL, "ref", &ref_clk),
320 CLK(NULL, "aux", &aux_clkin), 316 CLK(NULL, "aux", &aux_clkin),
321 CLK(NULL, "pll1", &pll1_clk), 317 CLK(NULL, "pll1", &pll1_clk),
@@ -515,14 +511,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
515 511
516/*----------------------------------------------------------------------*/ 512/*----------------------------------------------------------------------*/
517 513
518static const s8 dma_chan_dm646x_no_event[] = {
519 0, 1, 2, 3, 13,
520 14, 15, 24, 25, 26,
521 27, 30, 31, 54, 55,
522 56,
523 -1
524};
525
526/* Four Transfer Controllers on DM646x */ 514/* Four Transfer Controllers on DM646x */
527static const s8 515static const s8
528dm646x_queue_tc_mapping[][2] = { 516dm646x_queue_tc_mapping[][2] = {
@@ -551,7 +539,6 @@ static struct edma_soc_info dm646x_edma_info[] = {
551 .n_slot = 512, 539 .n_slot = 512,
552 .n_tc = 4, 540 .n_tc = 4,
553 .n_cc = 1, 541 .n_cc = 1,
554 .noevent = dma_chan_dm646x_no_event,
555 .queue_tc_mapping = dm646x_queue_tc_mapping, 542 .queue_tc_mapping = dm646x_queue_tc_mapping,
556 .queue_priority_mapping = dm646x_queue_priority_mapping, 543 .queue_priority_mapping = dm646x_queue_priority_mapping,
557 }, 544 },
@@ -789,7 +776,14 @@ static struct davinci_id dm646x_ids[] = {
789 .part_no = 0xb770, 776 .part_no = 0xb770,
790 .manufacturer = 0x017, 777 .manufacturer = 0x017,
791 .cpu_id = DAVINCI_CPU_ID_DM6467, 778 .cpu_id = DAVINCI_CPU_ID_DM6467,
792 .name = "dm6467", 779 .name = "dm6467_rev1.x",
780 },
781 {
782 .variant = 0x1,
783 .part_no = 0xb770,
784 .manufacturer = 0x017,
785 .cpu_id = DAVINCI_CPU_ID_DM6467,
786 .name = "dm6467_rev3.x",
793 }, 787 },
794}; 788};
795 789
@@ -920,6 +914,7 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
920 914
921void __init dm646x_init(void) 915void __init dm646x_init(void)
922{ 916{
917 dm646x_board_setup_refclk(&ref_clk);
923 davinci_common_init(&davinci_soc_info_dm646x); 918 davinci_common_init(&davinci_soc_info_dm646x);
924} 919}
925 920
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index f2e57d272958..53137387aee1 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -18,22 +18,14 @@
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/module.h> 22#include <linux/module.h>
24#include <linux/interrupt.h> 23#include <linux/interrupt.h>
25#include <linux/platform_device.h> 24#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27#include <linux/compiler.h>
28#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/slab.h>
29 27
30#include <mach/cputype.h>
31#include <mach/memory.h>
32#include <mach/hardware.h>
33#include <mach/irqs.h>
34#include <mach/edma.h> 28#include <mach/edma.h>
35#include <mach/mux.h>
36
37 29
38/* Offsets matching "struct edmacc_param" */ 30/* Offsets matching "struct edmacc_param" */
39#define PARM_OPT 0x00 31#define PARM_OPT 0x00
@@ -235,11 +227,11 @@ struct edma {
235 */ 227 */
236 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); 228 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
237 229
238 /* The edma_noevent bit for each channel is clear unless 230 /* The edma_unused bit for each channel is clear unless
239 * it doesn't trigger DMA events on this platform. It uses a 231 * it is not being used on this platform. It uses a bit
240 * bit of SOC-specific initialization code. 232 * of SOC-specific initialization code.
241 */ 233 */
242 DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); 234 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
243 235
244 unsigned irq_res_start; 236 unsigned irq_res_start;
245 unsigned irq_res_end; 237 unsigned irq_res_end;
@@ -252,6 +244,7 @@ struct edma {
252}; 244};
253 245
254static struct edma *edma_info[EDMA_MAX_CC]; 246static struct edma *edma_info[EDMA_MAX_CC];
247static int arch_num_cc;
255 248
256/* dummy param set used to (re)initialize parameter RAM slots */ 249/* dummy param set used to (re)initialize parameter RAM slots */
257static const struct edmacc_param dummy_paramset = { 250static const struct edmacc_param dummy_paramset = {
@@ -509,47 +502,82 @@ static irqreturn_t dma_tc1err_handler(int irq, void *data)
509 return IRQ_HANDLED; 502 return IRQ_HANDLED;
510} 503}
511 504
512static int reserve_contiguous_params(int ctlr, unsigned int id, 505static int reserve_contiguous_slots(int ctlr, unsigned int id,
513 unsigned int num_params, 506 unsigned int num_slots,
514 unsigned int start_param) 507 unsigned int start_slot)
515{ 508{
516 int i, j; 509 int i, j;
517 unsigned int count = num_params; 510 unsigned int count = num_slots;
511 int stop_slot = start_slot;
512 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
518 513
519 for (i = start_param; i < edma_info[ctlr]->num_slots; ++i) { 514 for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) {
520 j = EDMA_CHAN_SLOT(i); 515 j = EDMA_CHAN_SLOT(i);
521 if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) 516 if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) {
517 /* Record our current beginning slot */
518 if (count == num_slots)
519 stop_slot = i;
520
522 count--; 521 count--;
522 set_bit(j, tmp_inuse);
523
523 if (count == 0) 524 if (count == 0)
524 break; 525 break;
525 else if (id == EDMA_CONT_PARAMS_FIXED_EXACT) 526 } else {
526 break; 527 clear_bit(j, tmp_inuse);
527 else 528
528 count = num_params; 529 if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
530 stop_slot = i;
531 break;
532 } else
533 count = num_slots;
534 }
529 } 535 }
530 536
531 /* 537 /*
532 * We have to clear any bits that we set 538 * We have to clear any bits that we set
533 * if we run out parameter RAMs, i.e we do find a set 539 * if we run out parameter RAM slots, i.e we do find a set
534 * of contiguous parameter RAMs but do not find the exact number 540 * of contiguous parameter RAM slots but do not find the exact number
535 * requested as we may reach the total number of parameter RAMs 541 * requested as we may reach the total number of parameter RAM slots
536 */ 542 */
537 if (count) { 543 if (i == edma_info[ctlr]->num_slots)
538 for (j = i - num_params + count + 1; j <= i ; ++j) 544 stop_slot = i;
545
546 for (j = start_slot; j < stop_slot; j++)
547 if (test_bit(j, tmp_inuse))
539 clear_bit(j, edma_info[ctlr]->edma_inuse); 548 clear_bit(j, edma_info[ctlr]->edma_inuse);
540 549
550 if (count)
541 return -EBUSY; 551 return -EBUSY;
542 }
543 552
544 for (j = i - num_params + 1; j <= i; ++j) 553 for (j = i - num_slots + 1; j <= i; ++j)
545 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), 554 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
546 &dummy_paramset, PARM_SIZE); 555 &dummy_paramset, PARM_SIZE);
547 556
548 return EDMA_CTLR_CHAN(ctlr, i - num_params + 1); 557 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
558}
559
560static int prepare_unused_channel_list(struct device *dev, void *data)
561{
562 struct platform_device *pdev = to_platform_device(dev);
563 int i, ctlr;
564
565 for (i = 0; i < pdev->num_resources; i++) {
566 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
567 (int)pdev->resource[i].start >= 0) {
568 ctlr = EDMA_CTLR(pdev->resource[i].start);
569 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
570 edma_info[ctlr]->edma_unused);
571 }
572 }
573
574 return 0;
549} 575}
550 576
551/*-----------------------------------------------------------------------*/ 577/*-----------------------------------------------------------------------*/
552 578
579static bool unused_chan_list_done;
580
553/* Resource alloc/free: dma channels, parameter RAM slots */ 581/* Resource alloc/free: dma channels, parameter RAM slots */
554 582
555/** 583/**
@@ -587,7 +615,22 @@ int edma_alloc_channel(int channel,
587 void *data, 615 void *data,
588 enum dma_event_q eventq_no) 616 enum dma_event_q eventq_no)
589{ 617{
590 unsigned i, done, ctlr = 0; 618 unsigned i, done = 0, ctlr = 0;
619 int ret = 0;
620
621 if (!unused_chan_list_done) {
622 /*
623 * Scan all the platform devices to find out the EDMA channels
624 * used and clear them in the unused list, making the rest
625 * available for ARM usage.
626 */
627 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
628 prepare_unused_channel_list);
629 if (ret < 0)
630 return ret;
631
632 unused_chan_list_done = true;
633 }
591 634
592 if (channel >= 0) { 635 if (channel >= 0) {
593 ctlr = EDMA_CTLR(channel); 636 ctlr = EDMA_CTLR(channel);
@@ -595,15 +638,15 @@ int edma_alloc_channel(int channel,
595 } 638 }
596 639
597 if (channel < 0) { 640 if (channel < 0) {
598 for (i = 0; i < EDMA_MAX_CC; i++) { 641 for (i = 0; i < arch_num_cc; i++) {
599 channel = 0; 642 channel = 0;
600 for (;;) { 643 for (;;) {
601 channel = find_next_bit(edma_info[i]-> 644 channel = find_next_bit(edma_info[i]->
602 edma_noevent, 645 edma_unused,
603 edma_info[i]->num_channels, 646 edma_info[i]->num_channels,
604 channel); 647 channel);
605 if (channel == edma_info[i]->num_channels) 648 if (channel == edma_info[i]->num_channels)
606 return -ENOMEM; 649 break;
607 if (!test_and_set_bit(channel, 650 if (!test_and_set_bit(channel,
608 edma_info[i]->edma_inuse)) { 651 edma_info[i]->edma_inuse)) {
609 done = 1; 652 done = 1;
@@ -615,6 +658,8 @@ int edma_alloc_channel(int channel,
615 if (done) 658 if (done)
616 break; 659 break;
617 } 660 }
661 if (!done)
662 return -ENOMEM;
618 } else if (channel >= edma_info[ctlr]->num_channels) { 663 } else if (channel >= edma_info[ctlr]->num_channels) {
619 return -EINVAL; 664 return -EINVAL;
620 } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { 665 } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
@@ -635,7 +680,7 @@ int edma_alloc_channel(int channel,
635 680
636 map_dmach_queue(ctlr, channel, eventq_no); 681 map_dmach_queue(ctlr, channel, eventq_no);
637 682
638 return channel; 683 return EDMA_CTLR_CHAN(ctlr, channel);
639} 684}
640EXPORT_SYMBOL(edma_alloc_channel); 685EXPORT_SYMBOL(edma_alloc_channel);
641 686
@@ -743,26 +788,27 @@ EXPORT_SYMBOL(edma_free_slot);
743/** 788/**
744 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots 789 * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
745 * The API will return the starting point of a set of 790 * The API will return the starting point of a set of
746 * contiguous PARAM's that have been requested 791 * contiguous parameter RAM slots that have been requested
747 * 792 *
748 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT 793 * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
749 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT 794 * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
750 * @count: number of contiguous Paramter RAM's 795 * @count: number of contiguous Paramter RAM slots
751 * @param - the start value of Parameter RAM that should be passed if id 796 * @slot - the start value of Parameter RAM slot that should be passed if id
752 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT 797 * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
753 * 798 *
754 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of 799 * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
755 * contiguous Parameter RAMs from parameter RAM 64 in the case of DaVinci SOCs 800 * contiguous Parameter RAM slots from parameter RAM 64 in the case of
756 * and 32 in the case of Primus 801 * DaVinci SOCs and 32 in the case of DA8xx SOCs.
757 * 802 *
758 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a 803 * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
759 * set of contiguous parameter RAMs from the "param" that is passed as an 804 * set of contiguous parameter RAM slots from the "slot" that is passed as an
760 * argument to the API. 805 * argument to the API.
761 * 806 *
762 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries 807 * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
763 * starts looking for a set of contiguous parameter RAMs from the "param" 808 * starts looking for a set of contiguous parameter RAMs from the "slot"
764 * that is passed as an argument to the API. On failure the API will try to 809 * that is passed as an argument to the API. On failure the API will try to
765 * find a set of contiguous Parameter RAMs in the remaining Parameter RAMs 810 * find a set of contiguous Parameter RAM slots from the remaining Parameter
811 * RAM slots
766 */ 812 */
767int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) 813int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
768{ 814{
@@ -771,12 +817,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
771 * the number of channels and lesser than the total number 817 * the number of channels and lesser than the total number
772 * of slots 818 * of slots
773 */ 819 */
774 if (slot < edma_info[ctlr]->num_channels || 820 if ((id != EDMA_CONT_PARAMS_ANY) &&
775 slot >= edma_info[ctlr]->num_slots) 821 (slot < edma_info[ctlr]->num_channels ||
822 slot >= edma_info[ctlr]->num_slots))
776 return -EINVAL; 823 return -EINVAL;
777 824
778 /* 825 /*
779 * The number of parameter RAMs requested cannot be less than 1 826 * The number of parameter RAM slots requested cannot be less than 1
780 * and cannot be more than the number of slots minus the number of 827 * and cannot be more than the number of slots minus the number of
781 * channels 828 * channels
782 */ 829 */
@@ -786,11 +833,11 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
786 833
787 switch (id) { 834 switch (id) {
788 case EDMA_CONT_PARAMS_ANY: 835 case EDMA_CONT_PARAMS_ANY:
789 return reserve_contiguous_params(ctlr, id, count, 836 return reserve_contiguous_slots(ctlr, id, count,
790 edma_info[ctlr]->num_channels); 837 edma_info[ctlr]->num_channels);
791 case EDMA_CONT_PARAMS_FIXED_EXACT: 838 case EDMA_CONT_PARAMS_FIXED_EXACT:
792 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: 839 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
793 return reserve_contiguous_params(ctlr, id, count, slot); 840 return reserve_contiguous_slots(ctlr, id, count, slot);
794 default: 841 default:
795 return -EINVAL; 842 return -EINVAL;
796 } 843 }
@@ -799,21 +846,21 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
799EXPORT_SYMBOL(edma_alloc_cont_slots); 846EXPORT_SYMBOL(edma_alloc_cont_slots);
800 847
801/** 848/**
802 * edma_free_cont_slots - deallocate DMA parameter RAMs 849 * edma_free_cont_slots - deallocate DMA parameter RAM slots
803 * @slot: first parameter RAM of a set of parameter RAMs to be freed 850 * @slot: first parameter RAM of a set of parameter RAM slots to be freed
804 * @count: the number of contiguous parameter RAMs to be freed 851 * @count: the number of contiguous parameter RAM slots to be freed
805 * 852 *
806 * This deallocates the parameter RAM slots allocated by 853 * This deallocates the parameter RAM slots allocated by
807 * edma_alloc_cont_slots. 854 * edma_alloc_cont_slots.
808 * Callers/applications need to keep track of sets of contiguous 855 * Callers/applications need to keep track of sets of contiguous
809 * parameter RAMs that have been allocated using the edma_alloc_cont_slots 856 * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
810 * API. 857 * API.
811 * Callers are responsible for ensuring the slots are inactive, and will 858 * Callers are responsible for ensuring the slots are inactive, and will
812 * not be activated. 859 * not be activated.
813 */ 860 */
814int edma_free_cont_slots(unsigned slot, int count) 861int edma_free_cont_slots(unsigned slot, int count)
815{ 862{
816 unsigned ctlr; 863 unsigned ctlr, slot_to_free;
817 int i; 864 int i;
818 865
819 ctlr = EDMA_CTLR(slot); 866 ctlr = EDMA_CTLR(slot);
@@ -826,11 +873,11 @@ int edma_free_cont_slots(unsigned slot, int count)
826 873
827 for (i = slot; i < slot + count; ++i) { 874 for (i = slot; i < slot + count; ++i) {
828 ctlr = EDMA_CTLR(i); 875 ctlr = EDMA_CTLR(i);
829 slot = EDMA_CHAN_SLOT(i); 876 slot_to_free = EDMA_CHAN_SLOT(i);
830 877
831 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), 878 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
832 &dummy_paramset, PARM_SIZE); 879 &dummy_paramset, PARM_SIZE);
833 clear_bit(slot, edma_info[ctlr]->edma_inuse); 880 clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse);
834 } 881 }
835 882
836 return 0; 883 return 0;
@@ -1210,7 +1257,7 @@ int edma_start(unsigned channel)
1210 unsigned int mask = (1 << (channel & 0x1f)); 1257 unsigned int mask = (1 << (channel & 0x1f));
1211 1258
1212 /* EDMA channels without event association */ 1259 /* EDMA channels without event association */
1213 if (test_bit(channel, edma_info[ctlr]->edma_noevent)) { 1260 if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
1214 pr_debug("EDMA: ESR%d %08x\n", j, 1261 pr_debug("EDMA: ESR%d %08x\n", j,
1215 edma_shadow0_read_array(ctlr, SH_ESR, j)); 1262 edma_shadow0_read_array(ctlr, SH_ESR, j));
1216 edma_shadow0_write_array(ctlr, SH_ESR, j, mask); 1263 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@@ -1220,7 +1267,8 @@ int edma_start(unsigned channel)
1220 /* EDMA channel with event association */ 1267 /* EDMA channel with event association */
1221 pr_debug("EDMA: ER%d %08x\n", j, 1268 pr_debug("EDMA: ER%d %08x\n", j,
1222 edma_shadow0_read_array(ctlr, SH_ER, j)); 1269 edma_shadow0_read_array(ctlr, SH_ER, j));
1223 /* Clear any pending error */ 1270 /* Clear any pending event or error */
1271 edma_write_array(ctlr, EDMA_ECR, j, mask);
1224 edma_write_array(ctlr, EDMA_EMCR, j, mask); 1272 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1225 /* Clear any SER */ 1273 /* Clear any SER */
1226 edma_shadow0_write_array(ctlr, SH_SECR, j, mask); 1274 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
@@ -1335,7 +1383,6 @@ static int __init edma_probe(struct platform_device *pdev)
1335 const s8 (*queue_tc_mapping)[2]; 1383 const s8 (*queue_tc_mapping)[2];
1336 int i, j, found = 0; 1384 int i, j, found = 0;
1337 int status = -1; 1385 int status = -1;
1338 const s8 *noevent;
1339 int irq[EDMA_MAX_CC] = {0, 0}; 1386 int irq[EDMA_MAX_CC] = {0, 0};
1340 int err_irq[EDMA_MAX_CC] = {0, 0}; 1387 int err_irq[EDMA_MAX_CC] = {0, 0};
1341 struct resource *r[EDMA_MAX_CC] = {NULL}; 1388 struct resource *r[EDMA_MAX_CC] = {NULL};
@@ -1398,11 +1445,9 @@ static int __init edma_probe(struct platform_device *pdev)
1398 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), 1445 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1399 &dummy_paramset, PARM_SIZE); 1446 &dummy_paramset, PARM_SIZE);
1400 1447
1401 noevent = info[j].noevent; 1448 /* Mark all channels as unused */
1402 if (noevent) { 1449 memset(edma_info[j]->edma_unused, 0xff,
1403 while (*noevent != -1) 1450 sizeof(edma_info[j]->edma_unused));
1404 set_bit(*noevent++, edma_info[j]->edma_noevent);
1405 }
1406 1451
1407 sprintf(irq_name, "edma%d", j); 1452 sprintf(irq_name, "edma%d", j);
1408 irq[j] = platform_get_irq_byname(pdev, irq_name); 1453 irq[j] = platform_get_irq_byname(pdev, irq_name);
@@ -1458,6 +1503,7 @@ static int __init edma_probe(struct platform_device *pdev)
1458 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); 1503 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1459 edma_write_array(j, EDMA_QRAE, i, 0x0); 1504 edma_write_array(j, EDMA_QRAE, i, 0x0);
1460 } 1505 }
1506 arch_num_cc++;
1461 } 1507 }
1462 1508
1463 if (tc_errs_handled) { 1509 if (tc_errs_handled) {
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index f6ea9db11f41..744755b53236 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -12,23 +12,14 @@
12 12
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/module.h>
17#include <linux/clk.h> 15#include <linux/clk.h>
18#include <linux/err.h> 16#include <linux/err.h>
19#include <linux/io.h> 17#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/bitops.h>
22 18
23#include <mach/cputype.h>
24#include <mach/irqs.h>
25#include <mach/hardware.h>
26#include <mach/common.h>
27#include <mach/gpio.h> 19#include <mach/gpio.h>
28 20
29#include <asm/mach/irq.h> 21#include <asm/mach/irq.h>
30 22
31
32static DEFINE_SPINLOCK(gpio_lock); 23static DEFINE_SPINLOCK(gpio_lock);
33 24
34struct davinci_gpio { 25struct davinci_gpio {
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index 18e4ce34ece6..834725f1e81d 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -11,6 +11,9 @@
11#define DAVINCI_ASP0_BASE 0x01E02000 11#define DAVINCI_ASP0_BASE 0x01E02000
12#define DAVINCI_ASP1_BASE 0x01E04000 12#define DAVINCI_ASP1_BASE 0x01E04000
13 13
14/* Bases of dm365 register banks */
15#define DAVINCI_DM365_ASP0_BASE 0x01D02000
16
14/* Bases of dm646x register banks */ 17/* Bases of dm646x register banks */
15#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 18#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
16#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 19#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
@@ -51,6 +54,14 @@ struct snd_platform_data {
51 u32 rx_dma_offset; 54 u32 rx_dma_offset;
52 enum dma_event_q eventq_no; /* event queue number */ 55 enum dma_event_q eventq_no; /* event queue number */
53 unsigned int codec_fmt; 56 unsigned int codec_fmt;
57 /*
58 * Allowing this is more efficient and eliminates left and right swaps
59 * caused by underruns, but will swap the left and right channels
60 * when compared to previous behavior.
61 */
62 unsigned enable_channel_combine:1;
63 unsigned sram_size_playback;
64 unsigned sram_size_capture;
54 65
55 /* McASP specific fields */ 66 /* McASP specific fields */
56 int tdm_slots; 67 int tdm_slots;
diff --git a/arch/arm/mach-davinci/include/mach/cdce949.h b/arch/arm/mach-davinci/include/mach/cdce949.h
new file mode 100644
index 000000000000..c73331fae341
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cdce949.h
@@ -0,0 +1,19 @@
1/*
2 * TI CDCE949 off-chip clock synthesizer support
3 *
4 * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10#ifndef _MACH_DAVINCI_CDCE949_H
11#define _MACH_DAVINCI_CDCE949_H
12
13#include <linux/clk.h>
14
15#include <mach/clock.h>
16
17int cdce_set_rate(struct clk *clk, unsigned long rate);
18
19#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 1fd3917cae4e..50a955f05ef9 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -20,12 +20,6 @@ extern void davinci_irq_init(void);
20extern void __iomem *davinci_intc_base; 20extern void __iomem *davinci_intc_base;
21extern int davinci_intc_type; 21extern int davinci_intc_type;
22 22
23/* parameters describe VBUS sourcing for host mode */
24extern void setup_usb(unsigned mA, unsigned potpgt_msec);
25
26/* parameters describe VBUS sourcing for host mode */
27extern void setup_usb(unsigned mA, unsigned potpgt_msec);
28
29struct davinci_timer_instance { 23struct davinci_timer_instance {
30 void __iomem *base; 24 void __iomem *base;
31 u32 bottom_irq; 25 u32 bottom_irq;
@@ -49,7 +43,7 @@ struct davinci_soc_info {
49 void __iomem *jtag_id_base; 43 void __iomem *jtag_id_base;
50 struct davinci_id *ids; 44 struct davinci_id *ids;
51 unsigned long ids_num; 45 unsigned long ids_num;
52 struct davinci_clk *cpu_clks; 46 struct clk_lookup *cpu_clks;
53 void __iomem **psc_bases; 47 void __iomem **psc_bases;
54 unsigned long psc_bases_num; 48 unsigned long psc_bases_num;
55 void __iomem *pinmux_base; 49 void __iomem *pinmux_base;
diff --git a/arch/arm/mach-davinci/include/mach/cpufreq.h b/arch/arm/mach-davinci/include/mach/cpufreq.h
new file mode 100644
index 000000000000..3c089cfb6cd6
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cpufreq.h
@@ -0,0 +1,26 @@
1/*
2 * TI DaVinci CPUFreq platform support.
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MACH_DAVINCI_CPUFREQ_H
16#define _MACH_DAVINCI_CPUFREQ_H
17
18#include <linux/cpufreq.h>
19
20struct davinci_cpufreq_config {
21 struct cpufreq_frequency_table *freq_table;
22 int (*set_voltage) (unsigned int index);
23 int (*init) (void);
24};
25
26#endif
diff --git a/arch/arm/mach-davinci/include/mach/cpuidle.h b/arch/arm/mach-davinci/include/mach/cpuidle.h
new file mode 100644
index 000000000000..74f088b0edfb
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cpuidle.h
@@ -0,0 +1,18 @@
1/*
2 * TI DaVinci cpuidle platform support
3 *
4 * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10#ifndef _MACH_DAVINCI_CPUIDLE_H
11#define _MACH_DAVINCI_CPUIDLE_H
12
13struct davinci_cpuidle_config {
14 u32 ddr2_pdown;
15 void __iomem *ddr2_ctlr_base;
16};
17
18#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index d4095d0572c6..03acfd39042b 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Author: Mark A. Greer <mgreer@mvista.com> 4 * Author: Mark A. Greer <mgreer@mvista.com>
5 * 5 *
6 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under 6 * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program 7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express 8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied. 9 * or implied.
@@ -11,12 +11,21 @@
11#ifndef __ASM_ARCH_DAVINCI_DA8XX_H 11#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
12#define __ASM_ARCH_DAVINCI_DA8XX_H 12#define __ASM_ARCH_DAVINCI_DA8XX_H
13 13
14#include <video/da8xx-fb.h>
15
16#include <linux/platform_device.h>
17#include <linux/davinci_emac.h>
18
14#include <mach/serial.h> 19#include <mach/serial.h>
15#include <mach/edma.h> 20#include <mach/edma.h>
16#include <mach/i2c.h> 21#include <mach/i2c.h>
17#include <mach/emac.h>
18#include <mach/asp.h> 22#include <mach/asp.h>
19#include <mach/mmc.h> 23#include <mach/mmc.h>
24#include <mach/usb.h>
25#include <mach/pm.h>
26
27extern void __iomem *da8xx_syscfg0_base;
28extern void __iomem *da8xx_syscfg1_base;
20 29
21/* 30/*
22 * The cp_intc interrupt controller for the da8xx isn't in the same 31 * The cp_intc interrupt controller for the da8xx isn't in the same
@@ -29,20 +38,31 @@
29#define DA8XX_CP_INTC_SIZE SZ_8K 38#define DA8XX_CP_INTC_SIZE SZ_8K
30#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) 39#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
31 40
32#define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000) 41#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
42#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
43#define DA8XX_JTAG_ID_REG 0x18
44#define DA8XX_CFGCHIP0_REG 0x17c
45#define DA8XX_CFGCHIP2_REG 0x184
46#define DA8XX_CFGCHIP3_REG 0x188
47
48#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
49#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
50#define DA8XX_DEEPSLEEP_REG 0x8
33 51
34#define DA8XX_PSC0_BASE 0x01c10000 52#define DA8XX_PSC0_BASE 0x01c10000
35#define DA8XX_PLL0_BASE 0x01c11000 53#define DA8XX_PLL0_BASE 0x01c11000
36#define DA8XX_JTAG_ID_REG 0x01c14018
37#define DA8XX_TIMER64P0_BASE 0x01c20000 54#define DA8XX_TIMER64P0_BASE 0x01c20000
38#define DA8XX_TIMER64P1_BASE 0x01c21000 55#define DA8XX_TIMER64P1_BASE 0x01c21000
39#define DA8XX_GPIO_BASE 0x01e26000 56#define DA8XX_GPIO_BASE 0x01e26000
40#define DA8XX_PSC1_BASE 0x01e27000 57#define DA8XX_PSC1_BASE 0x01e27000
41#define DA8XX_LCD_CNTRL_BASE 0x01e13000 58#define DA8XX_LCD_CNTRL_BASE 0x01e13000
59#define DA8XX_PLL1_BASE 0x01e1a000
42#define DA8XX_MMCSD0_BASE 0x01c40000 60#define DA8XX_MMCSD0_BASE 0x01c40000
43#define DA8XX_AEMIF_CS2_BASE 0x60000000 61#define DA8XX_AEMIF_CS2_BASE 0x60000000
44#define DA8XX_AEMIF_CS3_BASE 0x62000000 62#define DA8XX_AEMIF_CS3_BASE 0x62000000
45#define DA8XX_AEMIF_CTL_BASE 0x68000000 63#define DA8XX_AEMIF_CTL_BASE 0x68000000
64#define DA8XX_DDR2_CTL_BASE 0xb0000000
65#define DA8XX_ARM_RAM_BASE 0xffff0000
46 66
47#define PINMUX0 0x00 67#define PINMUX0 0x00
48#define PINMUX1 0x04 68#define PINMUX1 0x04
@@ -71,13 +91,22 @@ void __init da850_init(void);
71int da8xx_register_edma(void); 91int da8xx_register_edma(void);
72int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata); 92int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
73int da8xx_register_watchdog(void); 93int da8xx_register_watchdog(void);
94int da8xx_register_usb20(unsigned mA, unsigned potpgt);
95int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
74int da8xx_register_emac(void); 96int da8xx_register_emac(void);
75int da8xx_register_lcdc(void); 97int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
76int da8xx_register_mmcsd0(struct davinci_mmc_config *config); 98int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
77void __init da8xx_init_mcasp(int id, struct snd_platform_data *pdata); 99void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
100int da8xx_register_rtc(void);
101int da850_register_cpufreq(void);
102int da8xx_register_cpuidle(void);
103void __iomem * __init da8xx_get_mem_ctlr(void);
104int da850_register_pm(struct platform_device *pdev);
78 105
79extern struct platform_device da8xx_serial_device; 106extern struct platform_device da8xx_serial_device;
80extern struct emac_platform_data da8xx_emac_pdata; 107extern struct emac_platform_data da8xx_emac_pdata;
108extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
109extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
81 110
82extern const short da830_emif25_pins[]; 111extern const short da830_emif25_pins[];
83extern const short da830_spi0_pins[]; 112extern const short da830_spi0_pins[];
@@ -110,12 +139,17 @@ extern const short da850_uart2_pins[];
110extern const short da850_i2c0_pins[]; 139extern const short da850_i2c0_pins[];
111extern const short da850_i2c1_pins[]; 140extern const short da850_i2c1_pins[];
112extern const short da850_cpgmac_pins[]; 141extern const short da850_cpgmac_pins[];
142extern const short da850_rmii_pins[];
113extern const short da850_mcasp_pins[]; 143extern const short da850_mcasp_pins[];
114extern const short da850_lcdcntl_pins[]; 144extern const short da850_lcdcntl_pins[];
115extern const short da850_mmcsd0_pins[]; 145extern const short da850_mmcsd0_pins[];
116extern const short da850_nand_pins[]; 146extern const short da850_nand_pins[];
117extern const short da850_nor_pins[]; 147extern const short da850_nor_pins[];
118 148
149#ifdef CONFIG_DAVINCI_MUX
119int da8xx_pinmux_setup(const short pins[]); 150int da8xx_pinmux_setup(const short pins[]);
151#else
152static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
153#endif
120 154
121#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */ 155#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 17ab5236da66..3cd93a801d9b 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -19,7 +19,7 @@
19#include <linux/serial_reg.h> 19#include <linux/serial_reg.h>
20#define UART_SHIFT 2 20#define UART_SHIFT 2
21 21
22 .macro addruart, rx 22 .macro addruart, rx, tmp
23 mrc p15, 0, \rx, c1, c0 23 mrc p15, 0, \rx, c1, c0
24 tst \rx, #1 @ MMU enabled? 24 tst \rx, #1 @ MMU enabled?
25 moveq \rx, #0x01000000 @ physical base address 25 moveq \rx, #0x01000000 @ physical base address
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 09db4343bb4c..3a37b5a6983c 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -14,8 +14,11 @@
14#define __ASM_ARCH_DM665_H 14#define __ASM_ARCH_DM665_H
15 15
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/davinci_emac.h>
17#include <mach/hardware.h> 18#include <mach/hardware.h>
18#include <mach/emac.h> 19#include <mach/asp.h>
20#include <mach/keyscan.h>
21#include <media/davinci/vpfe_capture.h>
19 22
20#define DM365_EMAC_BASE (0x01D07000) 23#define DM365_EMAC_BASE (0x01D07000)
21#define DM365_EMAC_CNTRL_OFFSET (0x0000) 24#define DM365_EMAC_CNTRL_OFFSET (0x0000)
@@ -24,6 +27,22 @@
24#define DM365_EMAC_MDIO_OFFSET (0x4000) 27#define DM365_EMAC_MDIO_OFFSET (0x4000)
25#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000) 28#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
26 29
30/* Base of key scan register bank */
31#define DM365_KEYSCAN_BASE (0x01C69400)
32
33#define DM365_RTC_BASE (0x01C69000)
34
35#define DAVINCI_DM365_VC_BASE (0x01D0C000)
36#define DAVINCI_DMA_VC_TX 2
37#define DAVINCI_DMA_VC_RX 3
38
27void __init dm365_init(void); 39void __init dm365_init(void);
40void __init dm365_init_asp(struct snd_platform_data *pdata);
41void __init dm365_init_vc(struct snd_platform_data *pdata);
42void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
43void __init dm365_init_rtc(void);
44void dm365_init_spi0(unsigned chipselect_mask,
45 struct spi_board_info *info, unsigned len);
28 46
47void dm365_set_vpfe_config(struct vpfe_config *cfg);
29#endif /* __ASM_ARCH_DM365_H */ 48#endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 0efb73852c2c..1a8b09ccc3c8 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -22,9 +22,8 @@
22#ifndef __ASM_ARCH_DM644X_H 22#ifndef __ASM_ARCH_DM644X_H
23#define __ASM_ARCH_DM644X_H 23#define __ASM_ARCH_DM644X_H
24 24
25#include <linux/platform_device.h> 25#include <linux/davinci_emac.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/emac.h>
28#include <mach/asp.h> 27#include <mach/asp.h>
29#include <media/davinci/vpfe_capture.h> 28#include <media/davinci/vpfe_capture.h>
30 29
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 8cec746ae9d2..846da98b619a 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -12,10 +12,11 @@
12#define __ASM_ARCH_DM646X_H 12#define __ASM_ARCH_DM646X_H
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/emac.h>
16#include <mach/asp.h> 15#include <mach/asp.h>
17#include <linux/i2c.h> 16#include <linux/i2c.h>
18#include <linux/videodev2.h> 17#include <linux/videodev2.h>
18#include <linux/clk.h>
19#include <linux/davinci_emac.h>
19 20
20#define DM646X_EMAC_BASE (0x01C80000) 21#define DM646X_EMAC_BASE (0x01C80000)
21#define DM646X_EMAC_CNTRL_OFFSET (0x0000) 22#define DM646X_EMAC_CNTRL_OFFSET (0x0000)
@@ -30,6 +31,7 @@ void __init dm646x_init(void);
30void __init dm646x_init_ide(void); 31void __init dm646x_init_ide(void);
31void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); 32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
32void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); 33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
34void __init dm646x_board_setup_refclk(struct clk *clk);
33 35
34void dm646x_video_init(void); 36void dm646x_video_init(void);
35 37
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index eb8bfd7925e7..ced3092af5ba 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -280,8 +280,6 @@ struct edma_soc_info {
280 unsigned n_cc; 280 unsigned n_cc;
281 enum dma_event_q default_queue; 281 enum dma_event_q default_queue;
282 282
283 /* list of channels with no even trigger; terminated by "-1" */
284 const s8 *noevent;
285 const s8 (*queue_tc_mapping)[2]; 283 const s8 (*queue_tc_mapping)[2];
286 const s8 (*queue_priority_mapping)[2]; 284 const s8 (*queue_priority_mapping)[2];
287}; 285};
diff --git a/arch/arm/mach-davinci/include/mach/emac.h b/arch/arm/mach-davinci/include/mach/emac.h
deleted file mode 100644
index beff4fb7c845..000000000000
--- a/arch/arm/mach-davinci/include/mach/emac.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * TI DaVinci EMAC platform support
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef _MACH_DAVINCI_EMAC_H
12#define _MACH_DAVINCI_EMAC_H
13
14#include <linux/if_ether.h>
15#include <linux/memory.h>
16
17struct emac_platform_data {
18 char mac_addr[ETH_ALEN];
19 u32 ctrl_reg_offset;
20 u32 ctrl_mod_reg_offset;
21 u32 ctrl_ram_offset;
22 u32 mdio_reg_offset;
23 u32 ctrl_ram_size;
24 u32 phy_mask;
25 u32 mdio_max_freq;
26 u8 rmii_en;
27 u8 version;
28};
29
30enum {
31 EMAC_VERSION_1, /* DM644x */
32 EMAC_VERSION_2, /* DM646x */
33};
34
35void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context);
36#endif
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 41c89386e39b..c45ba1f62a11 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -27,7 +27,7 @@
27/* 27/*
28 * I/O mapping 28 * I/O mapping
29 */ 29 */
30#define IO_PHYS 0x01c00000 30#define IO_PHYS 0x01c00000UL
31#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ 31#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */
32#define IO_SIZE 0x00400000 32#define IO_SIZE 0x00400000
33#define IO_VIRT (IO_PHYS + IO_OFFSET) 33#define IO_VIRT (IO_PHYS + IO_OFFSET)
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h
index c248e9b7e825..2312d197dfb7 100644
--- a/arch/arm/mach-davinci/include/mach/i2c.h
+++ b/arch/arm/mach-davinci/include/mach/i2c.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * DaVinci I2C controller platfrom_device info 2 * DaVinci I2C controller platform_device info
3 * 3 *
4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 4 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
5 * 5 *
@@ -16,6 +16,8 @@
16struct davinci_i2c_platform_data { 16struct davinci_i2c_platform_data {
17 unsigned int bus_freq; /* standard bus frequency (kHz) */ 17 unsigned int bus_freq; /* standard bus frequency (kHz) */
18 unsigned int bus_delay; /* post-transaction delay (usec) */ 18 unsigned int bus_delay; /* post-transaction delay (usec) */
19 unsigned int sda_pin; /* GPIO pin ID to use for SDA */
20 unsigned int scl_pin; /* GPIO pin ID to use for SCL */
19}; 21};
20 22
21/* for board setup code */ 23/* for board setup code */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 3c918a772619..354af71798dc 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -217,6 +217,7 @@
217#define IRQ_DM365_SDIOINT0 23 217#define IRQ_DM365_SDIOINT0 23
218#define IRQ_DM365_MMCINT1 27 218#define IRQ_DM365_MMCINT1 27
219#define IRQ_DM365_PWMINT3 28 219#define IRQ_DM365_PWMINT3 28
220#define IRQ_DM365_RTCINT 29
220#define IRQ_DM365_SDIOINT1 31 221#define IRQ_DM365_SDIOINT1 31
221#define IRQ_DM365_SPIINT0_0 42 222#define IRQ_DM365_SPIINT0_0 42
222#define IRQ_DM365_SPIINT3_0 43 223#define IRQ_DM365_SPIINT3_0 43
diff --git a/arch/arm/mach-davinci/include/mach/keyscan.h b/arch/arm/mach-davinci/include/mach/keyscan.h
new file mode 100644
index 000000000000..7a560e05bda8
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/keyscan.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2009 Texas Instruments, Inc
3 *
4 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef DAVINCI_KEYSCAN_H
22#define DAVINCI_KEYSCAN_H
23
24#include <linux/io.h>
25
26enum davinci_matrix_types {
27 DAVINCI_KEYSCAN_MATRIX_4X4,
28 DAVINCI_KEYSCAN_MATRIX_5X3,
29};
30
31struct davinci_ks_platform_data {
32 int (*device_enable)(struct device *dev);
33 unsigned short *keymap;
34 u32 keymapsize;
35 u8 rep:1;
36 u8 strobe;
37 u8 interval;
38 u8 matrix_type;
39};
40
41#endif
42
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 80309aed534a..a91edfb8beea 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -31,6 +31,11 @@
31#define PHYS_OFFSET DAVINCI_DDR_BASE 31#define PHYS_OFFSET DAVINCI_DDR_BASE
32#endif 32#endif
33 33
34#define DDR2_SDRCR_OFFSET 0xc
35#define DDR2_SRPD_BIT BIT(23)
36#define DDR2_MCLKSTOPEN_BIT BIT(30)
37#define DDR2_LPMODEN_BIT BIT(31)
38
34/* 39/*
35 * Increase size of DMA-consistent memory region 40 * Increase size of DMA-consistent memory region
36 */ 41 */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index bb84893a4e83..2a68c1d8a24b 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -40,6 +40,11 @@ enum davinci_dm644x_index {
40 40
41 /* AEAW functions */ 41 /* AEAW functions */
42 DM644X_AEAW, 42 DM644X_AEAW,
43 DM644X_AEAW0,
44 DM644X_AEAW1,
45 DM644X_AEAW2,
46 DM644X_AEAW3,
47 DM644X_AEAW4,
43 48
44 /* Memory Stick */ 49 /* Memory Stick */
45 DM644X_MSTK, 50 DM644X_MSTK,
@@ -237,8 +242,8 @@ enum davinci_dm365_index {
237 DM365_EMAC_MDIO, 242 DM365_EMAC_MDIO,
238 DM365_EMAC_MDCLK, 243 DM365_EMAC_MDCLK,
239 244
240 /* Keypad */ 245 /* Key Scan */
241 DM365_KEYPAD, 246 DM365_KEYSCAN,
242 247
243 /* PWM */ 248 /* PWM */
244 DM365_PWM0, 249 DM365_PWM0,
@@ -322,6 +327,8 @@ enum davinci_dm365_index {
322 /* EDMA event muxing */ 327 /* EDMA event muxing */
323 DM365_EVT2_ASP_TX, 328 DM365_EVT2_ASP_TX,
324 DM365_EVT3_ASP_RX, 329 DM365_EVT3_ASP_RX,
330 DM365_EVT2_VC_TX,
331 DM365_EVT3_VC_RX,
325 DM365_EVT26_MMC0_RX, 332 DM365_EVT26_MMC0_RX,
326}; 333};
327 334
@@ -774,6 +781,14 @@ enum davinci_da850_index {
774 DA850_MII_RXD_0, 781 DA850_MII_RXD_0,
775 DA850_MDIO_CLK, 782 DA850_MDIO_CLK,
776 DA850_MDIO_D, 783 DA850_MDIO_D,
784 DA850_RMII_TXD_0,
785 DA850_RMII_TXD_1,
786 DA850_RMII_TXEN,
787 DA850_RMII_CRS_DV,
788 DA850_RMII_RXD_0,
789 DA850_RMII_RXD_1,
790 DA850_RMII_RXER,
791 DA850_RMII_MHZ_50_CLK,
777 792
778 /* McASP function */ 793 /* McASP function */
779 DA850_ACLKR, 794 DA850_ACLKR,
@@ -881,10 +896,12 @@ enum davinci_da850_index {
881 DA850_NEMA_CS_2, 896 DA850_NEMA_CS_2,
882 897
883 /* GPIO function */ 898 /* GPIO function */
899 DA850_GPIO2_6,
900 DA850_GPIO2_8,
884 DA850_GPIO2_15, 901 DA850_GPIO2_15,
885 DA850_GPIO8_10,
886 DA850_GPIO4_0, 902 DA850_GPIO4_0,
887 DA850_GPIO4_1, 903 DA850_GPIO4_1,
904 DA850_RTC_ALARM,
888}; 905};
889 906
890#ifdef CONFIG_DAVINCI_MUX 907#ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h
index b520c4b5678a..b2ad8090bd10 100644
--- a/arch/arm/mach-davinci/include/mach/nand.h
+++ b/arch/arm/mach-davinci/include/mach/nand.h
@@ -79,6 +79,10 @@ struct davinci_nand_pdata { /* platform_data */
79 79
80 /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ 80 /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */
81 unsigned options; 81 unsigned options;
82
83 /* Main and mirror bbt descriptor overrides */
84 struct nand_bbt_descr *bbt_td;
85 struct nand_bbt_descr *bbt_md;
82}; 86};
83 87
84#endif /* __ARCH_ARM_DAVINCI_NAND_H */ 88#endif /* __ARCH_ARM_DAVINCI_NAND_H */
diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/include/mach/pm.h
new file mode 100644
index 000000000000..37b19bf35a85
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pm.h
@@ -0,0 +1,54 @@
1/*
2 * TI DaVinci platform support for power management.
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MACH_DAVINCI_PM_H
16#define _MACH_DAVINCI_PM_H
17
18/*
19 * Caution: Assembly code in sleep.S makes assumtion on the order
20 * of the members of this structure.
21 */
22struct davinci_pm_config {
23 void __iomem *ddr2_ctlr_base;
24 void __iomem *ddrpsc_reg_base;
25 int ddrpsc_num;
26 void __iomem *ddrpll_reg_base;
27 void __iomem *deepsleep_reg;
28 void __iomem *cpupll_reg_base;
29 /*
30 * Note on SLEEPCOUNT:
31 * The SLEEPCOUNT feature is mainly intended for cases in which
32 * the internal oscillator is used. The internal oscillator is
33 * fully disabled in deep sleep mode. When you exist deep sleep
34 * mode, the oscillator will be turned on and will generate very
35 * small oscillations which will not be detected by the deep sleep
36 * counter. Eventually those oscillations will grow to an amplitude
37 * large enough to start incrementing the deep sleep counter.
38 * In this case recommendation from hardware engineers is that the
39 * SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles
40 * must be detected before the clock is passed to the rest of the
41 * system.
42 * In the case that the internal oscillator is not used and the
43 * clock is generated externally, the SLEEPCOUNT value can be very
44 * small since the clock input is assumed to be stable before SoC
45 * is taken out of deepsleep mode. A value of 128 would be more than
46 * adequate.
47 */
48 int sleepcount;
49};
50
51extern unsigned int davinci_cpu_suspend_sz;
52extern void davinci_cpu_suspend(struct davinci_pm_config *);
53
54#endif
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 171173c1dbad..651f6d8158fa 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -180,8 +180,23 @@
180#define DA8XX_LPSC1_CR_P3_SS 26 180#define DA8XX_LPSC1_CR_P3_SS 26
181#define DA8XX_LPSC1_L3_CBA_RAM 31 181#define DA8XX_LPSC1_L3_CBA_RAM 31
182 182
183/* PSC register offsets */
184#define EPCPR 0x070
185#define PTCMD 0x120
186#define PTSTAT 0x128
187#define PDSTAT 0x200
188#define PDCTL1 0x304
189#define MDSTAT 0x800
190#define MDCTL 0xA00
191
192#define MDSTAT_STATE_MASK 0x1f
193
194#ifndef __ASSEMBLER__
195
183extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); 196extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
184extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, 197extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
185 unsigned int id, char enable); 198 unsigned int id, char enable);
186 199
200#endif
201
187#endif /* __ASM_ARCH_PSC_H */ 202#endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
new file mode 100644
index 000000000000..910efbf099c0
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __ARCH_ARM_DAVINCI_SPI_H
20#define __ARCH_ARM_DAVINCI_SPI_H
21
22enum {
23 SPI_VERSION_1, /* For DM355/DM365/DM6467 */
24 SPI_VERSION_2, /* For DA8xx */
25};
26
27struct davinci_spi_platform_data {
28 u8 version;
29 u8 num_chipselect;
30 u8 wdelay;
31 u8 odd_parity;
32 u8 parity_enable;
33 u8 wait_enable;
34 u8 timer_disable;
35 u8 clk_internal;
36 u8 cs_hold;
37 u8 intr_level;
38 u8 poll_mode;
39 u8 use_dma;
40 u8 c2tdelay;
41 u8 t2cdelay;
42};
43
44#endif /* __ARCH_ARM_DAVINCI_SPI_H */
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index 8e4f10fe1263..5a7d7581b8ce 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -11,9 +11,6 @@
11#ifndef __ASM_ARCH_SYSTEM_H 11#ifndef __ASM_ARCH_SYSTEM_H
12#define __ASM_ARCH_SYSTEM_H 12#define __ASM_ARCH_SYSTEM_H
13 13
14#include <linux/io.h>
15#include <mach/hardware.h>
16
17extern void davinci_watchdog_reset(void); 14extern void davinci_watchdog_reset(void);
18 15
19static inline void arch_idle(void) 16static inline void arch_idle(void)
diff --git a/arch/arm/mach-davinci/include/mach/timex.h b/arch/arm/mach-davinci/include/mach/timex.h
index 52827567841d..9b885298f106 100644
--- a/arch/arm/mach-davinci/include/mach/timex.h
+++ b/arch/arm/mach-davinci/include/mach/timex.h
@@ -11,7 +11,12 @@
11#ifndef __ASM_ARCH_TIMEX_H 11#ifndef __ASM_ARCH_TIMEX_H
12#define __ASM_ARCH_TIMEX_H 12#define __ASM_ARCH_TIMEX_H
13 13
14/* The source frequency for the timers is the 27MHz clock */ 14/*
15 * Alert: Not all timers of the DaVinci family run at a frequency of 27MHz,
16 * but we should be fine as long as CLOCK_TICK_RATE or LATCH (see include/
17 * linux/jiffies.h) are not used directly in code. Currently none of the
18 * code relevant to DaVinci platform depends on these values directly.
19 */
15#define CLOCK_TICK_RATE 27000000 20#define CLOCK_TICK_RATE 27000000
16 21
17#endif /* __ASM_ARCH_TIMEX_H__ */ 22#endif /* __ASM_ARCH_TIMEX_H__ */
diff --git a/arch/arm/mach-davinci/include/mach/usb.h b/arch/arm/mach-davinci/include/mach/usb.h
new file mode 100644
index 000000000000..e0bc4abe69c2
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/usb.h
@@ -0,0 +1,59 @@
1/*
2 * USB related definitions
3 *
4 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_USB_H
12#define __ASM_ARCH_USB_H
13
14/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
15#define CFGCHIP2_PHYCLKGD (1 << 17)
16#define CFGCHIP2_VBUSSENSE (1 << 16)
17#define CFGCHIP2_RESET (1 << 15)
18#define CFGCHIP2_OTGMODE (3 << 13)
19#define CFGCHIP2_NO_OVERRIDE (0 << 13)
20#define CFGCHIP2_FORCE_HOST (1 << 13)
21#define CFGCHIP2_FORCE_DEVICE (2 << 13)
22#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
23#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
24#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
25#define CFGCHIP2_PHYPWRDN (1 << 10)
26#define CFGCHIP2_OTGPWRDN (1 << 9)
27#define CFGCHIP2_DATPOL (1 << 8)
28#define CFGCHIP2_USB1SUSPENDM (1 << 7)
29#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
30#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
31#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
32#define CFGCHIP2_REFFREQ (0xf << 0)
33#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
34#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
35#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
36
37struct da8xx_ohci_root_hub;
38
39typedef void (*da8xx_ocic_handler_t)(struct da8xx_ohci_root_hub *hub,
40 unsigned port);
41
42/* Passed as the platform data to the OHCI driver */
43struct da8xx_ohci_root_hub {
44 /* Switch the port power on/off */
45 int (*set_power)(unsigned port, int on);
46 /* Read the port power status */
47 int (*get_power)(unsigned port);
48 /* Read the port over-current indicator */
49 int (*get_oci)(unsigned port);
50 /* Over-current indicator change notification (pass NULL to disable) */
51 int (*ocic_notify)(da8xx_ocic_handler_t handler);
52
53 /* Time from power on to power good (in 2 ms units) */
54 u8 potpgt;
55};
56
57void davinci_setup_usb(unsigned mA, unsigned potpgt_ms);
58
59#endif /* ifndef __ASM_ARCH_USB_H */
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 49912b48b1b0..a1c0b6b99edf 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -24,7 +24,7 @@ void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
24 if (BETWEEN(p, IO_PHYS, IO_SIZE)) 24 if (BETWEEN(p, IO_PHYS, IO_SIZE))
25 return XLATE(p, IO_PHYS, IO_VIRT); 25 return XLATE(p, IO_PHYS, IO_VIRT);
26 26
27 return __arm_ioremap(p, size, type); 27 return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
28} 28}
29EXPORT_SYMBOL(davinci_ioremap); 29EXPORT_SYMBOL(davinci_ioremap);
30 30
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index 898905e48946..f757e83415f3 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -19,7 +19,6 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21 21
22#include <mach/hardware.h>
23#include <mach/mux.h> 22#include <mach/mux.h>
24#include <mach/common.h> 23#include <mach/common.h>
25 24
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
new file mode 100644
index 000000000000..fab953b43dea
--- /dev/null
+++ b/arch/arm/mach-davinci/pm.c
@@ -0,0 +1,158 @@
1/*
2 * DaVinci Power Management Routines
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/spinlock.h>
17
18#include <asm/cacheflush.h>
19#include <asm/delay.h>
20
21#include <mach/da8xx.h>
22#include <mach/sram.h>
23#include <mach/pm.h>
24
25#include "clock.h"
26
27#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
28
29static void (*davinci_sram_suspend) (struct davinci_pm_config *);
30static struct davinci_pm_config *pdata;
31
32static void davinci_sram_push(void *dest, void *src, unsigned int size)
33{
34 memcpy(dest, src, size);
35 flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
36}
37
38static void davinci_pm_suspend(void)
39{
40 unsigned val;
41
42 if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
43
44 /* Switch CPU PLL to bypass mode */
45 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
46 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
47 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
48
49 udelay(PLL_BYPASS_TIME);
50
51 /* Powerdown CPU PLL */
52 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
53 val |= PLLCTL_PLLPWRDN;
54 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
55 }
56
57 /* Configure sleep count in deep sleep register */
58 val = __raw_readl(pdata->deepsleep_reg);
59 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
60 val |= pdata->sleepcount;
61 __raw_writel(val, pdata->deepsleep_reg);
62
63 /* System goes to sleep in this call */
64 davinci_sram_suspend(pdata);
65
66 if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
67
68 /* put CPU PLL in reset */
69 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
70 val &= ~PLLCTL_PLLRST;
71 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
72
73 /* put CPU PLL in power down */
74 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
75 val &= ~PLLCTL_PLLPWRDN;
76 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
77
78 /* wait for CPU PLL reset */
79 udelay(PLL_RESET_TIME);
80
81 /* bring CPU PLL out of reset */
82 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
83 val |= PLLCTL_PLLRST;
84 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
85
86 /* Wait for CPU PLL to lock */
87 udelay(PLL_LOCK_TIME);
88
89 /* Remove CPU PLL from bypass mode */
90 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
91 val &= ~PLLCTL_PLLENSRC;
92 val |= PLLCTL_PLLEN;
93 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
94 }
95}
96
97static int davinci_pm_enter(suspend_state_t state)
98{
99 int ret = 0;
100
101 switch (state) {
102 case PM_SUSPEND_STANDBY:
103 case PM_SUSPEND_MEM:
104 davinci_pm_suspend();
105 break;
106 default:
107 ret = -EINVAL;
108 }
109
110 return ret;
111}
112
113static struct platform_suspend_ops davinci_pm_ops = {
114 .enter = davinci_pm_enter,
115 .valid = suspend_valid_only_mem,
116};
117
118static int __init davinci_pm_probe(struct platform_device *pdev)
119{
120 pdata = pdev->dev.platform_data;
121 if (!pdata) {
122 dev_err(&pdev->dev, "cannot get platform data\n");
123 return -ENOENT;
124 }
125
126 davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
127 if (!davinci_sram_suspend) {
128 dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
129 return -ENOMEM;
130 }
131
132 davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
133 davinci_cpu_suspend_sz);
134
135 suspend_set_ops(&davinci_pm_ops);
136
137 return 0;
138}
139
140static int __exit davinci_pm_remove(struct platform_device *pdev)
141{
142 sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
143 return 0;
144}
145
146static struct platform_driver davinci_pm_driver = {
147 .driver = {
148 .name = "pm-davinci",
149 .owner = THIS_MODULE,
150 },
151 .remove = __exit_p(davinci_pm_remove),
152};
153
154static int __init davinci_pm_init(void)
155{
156 return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
157}
158late_initcall(davinci_pm_init);
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index a78b657e916e..adf6b5c7f1e5 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -19,25 +19,11 @@
19 * 19 *
20 */ 20 */
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h> 22#include <linux/init.h>
24#include <linux/io.h> 23#include <linux/io.h>
25 24
26#include <mach/cputype.h> 25#include <mach/cputype.h>
27#include <mach/hardware.h>
28#include <mach/psc.h> 26#include <mach/psc.h>
29#include <mach/mux.h>
30
31/* PSC register offsets */
32#define EPCPR 0x070
33#define PTCMD 0x120
34#define PTSTAT 0x128
35#define PDSTAT 0x200
36#define PDCTL1 0x304
37#define MDSTAT 0x800
38#define MDCTL 0xA00
39
40#define MDSTAT_STATE_MASK 0x1f
41 27
42/* Return nonzero iff the domain's clock is active */ 28/* Return nonzero iff the domain's clock is active */
43int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) 29int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index c530c7333d0a..7ce5ba086575 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -28,14 +28,8 @@
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/io.h> 29#include <linux/io.h>
30 30
31#include <asm/irq.h>
32#include <mach/hardware.h>
33#include <mach/serial.h> 31#include <mach/serial.h>
34#include <mach/irqs.h>
35#include <mach/cputype.h> 32#include <mach/cputype.h>
36#include <mach/common.h>
37
38#include "clock.h"
39 33
40static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, 34static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
41 int offset) 35 int offset)
diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S
new file mode 100644
index 000000000000..fb5e72b532b0
--- /dev/null
+++ b/arch/arm/mach-davinci/sleep.S
@@ -0,0 +1,224 @@
1/*
2 * (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16 * MA 02111-1307 USA
17 */
18
19/* replicated define because linux/bitops.h cannot be included in assembly */
20#define BIT(nr) (1 << (nr))
21
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <mach/psc.h>
25#include <mach/memory.h>
26
27#include "clock.h"
28
29/* Arbitrary, hardware currently does not update PHYRDY correctly */
30#define PHYRDY_CYCLES 0x1000
31
32/* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */
33#define PLL_BYPASS_CYCLES (PLL_BYPASS_TIME * 25)
34#define PLL_RESET_CYCLES (PLL_RESET_TIME * 25)
35#define PLL_LOCK_CYCLES (PLL_LOCK_TIME * 25)
36
37#define DEEPSLEEP_SLEEPENABLE_BIT BIT(31)
38
39 .text
40/*
41 * Move DaVinci into deep sleep state
42 *
43 * Note: This code is copied to internal SRAM by PM code. When the DaVinci
44 * wakes up it continues execution at the point it went to sleep.
45 * Register Usage:
46 * r0: contains virtual base for DDR2 controller
47 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
48 * r2: contains PSC number for DDR2
49 * r3: contains virtual base DDR2 PLL controller
50 * r4: contains virtual address of the DEEPSLEEP register
51 */
52ENTRY(davinci_cpu_suspend)
53 stmfd sp!, {r0-r12, lr} @ save registers on stack
54
55 ldr ip, CACHE_FLUSH
56 blx ip
57
58 ldmia r0, {r0-r4}
59
60 /*
61 * Switch DDR to self-refresh mode.
62 */
63
64 /* calculate SDRCR address */
65 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
66 bic ip, ip, #DDR2_SRPD_BIT
67 orr ip, ip, #DDR2_LPMODEN_BIT
68 str ip, [r0, #DDR2_SDRCR_OFFSET]
69
70 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
71 orr ip, ip, #DDR2_MCLKSTOPEN_BIT
72 str ip, [r0, #DDR2_SDRCR_OFFSET]
73
74 mov ip, #PHYRDY_CYCLES
751: subs ip, ip, #0x1
76 bne 1b
77
78 /* Disable DDR2 LPSC */
79 mov r7, r0
80 mov r0, #0x2
81 bl davinci_ddr_psc_config
82 mov r0, r7
83
84 /* Disable clock to DDR PHY */
85 ldr ip, [r3, #PLLDIV1]
86 bic ip, ip, #PLLDIV_EN
87 str ip, [r3, #PLLDIV1]
88
89 /* Put the DDR PLL in bypass and power down */
90 ldr ip, [r3, #PLLCTL]
91 bic ip, ip, #PLLCTL_PLLENSRC
92 bic ip, ip, #PLLCTL_PLLEN
93 str ip, [r3, #PLLCTL]
94
95 /* Wait for PLL to switch to bypass */
96 mov ip, #PLL_BYPASS_CYCLES
972: subs ip, ip, #0x1
98 bne 2b
99
100 /* Power down the PLL */
101 ldr ip, [r3, #PLLCTL]
102 orr ip, ip, #PLLCTL_PLLPWRDN
103 str ip, [r3, #PLLCTL]
104
105 /* Go to deep sleep */
106 ldr ip, [r4]
107 orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
108 /* System goes to sleep beyond after this instruction */
109 str ip, [r4]
110
111 /* Wake up from sleep */
112
113 /* Clear sleep enable */
114 ldr ip, [r4]
115 bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
116 str ip, [r4]
117
118 /* initialize the DDR PLL controller */
119
120 /* Put PLL in reset */
121 ldr ip, [r3, #PLLCTL]
122 bic ip, ip, #PLLCTL_PLLRST
123 str ip, [r3, #PLLCTL]
124
125 /* Clear PLL power down */
126 ldr ip, [r3, #PLLCTL]
127 bic ip, ip, #PLLCTL_PLLPWRDN
128 str ip, [r3, #PLLCTL]
129
130 mov ip, #PLL_RESET_CYCLES
1313: subs ip, ip, #0x1
132 bne 3b
133
134 /* Bring PLL out of reset */
135 ldr ip, [r3, #PLLCTL]
136 orr ip, ip, #PLLCTL_PLLRST
137 str ip, [r3, #PLLCTL]
138
139 /* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
140 mov ip, #PLL_LOCK_CYCLES
1414: subs ip, ip, #0x1
142 bne 4b
143
144 /* Remove PLL from bypass mode */
145 ldr ip, [r3, #PLLCTL]
146 bic ip, ip, #PLLCTL_PLLENSRC
147 orr ip, ip, #PLLCTL_PLLEN
148 str ip, [r3, #PLLCTL]
149
150 /* Start 2x clock to DDR2 */
151
152 ldr ip, [r3, #PLLDIV1]
153 orr ip, ip, #PLLDIV_EN
154 str ip, [r3, #PLLDIV1]
155
156 /* Enable VCLK */
157
158 /* Enable DDR2 LPSC */
159 mov r7, r0
160 mov r0, #0x3
161 bl davinci_ddr_psc_config
162 mov r0, r7
163
164 /* clear MCLKSTOPEN */
165
166 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
167 bic ip, ip, #DDR2_MCLKSTOPEN_BIT
168 str ip, [r0, #DDR2_SDRCR_OFFSET]
169
170 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
171 bic ip, ip, #DDR2_LPMODEN_BIT
172 str ip, [r0, #DDR2_SDRCR_OFFSET]
173
174 /* Restore registers and return */
175 ldmfd sp!, {r0-r12, pc}
176
177ENDPROC(davinci_cpu_suspend)
178
179/*
180 * Disables or Enables DDR2 LPSC
181 * Register Usage:
182 * r0: Enable or Disable LPSC r0 = 0x3 => Enable, r0 = 0x2 => Disable LPSC
183 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
184 * r2: contains PSC number for DDR2
185 */
186ENTRY(davinci_ddr_psc_config)
187 /* Set next state in mdctl for DDR2 */
188 mov r6, #MDCTL
189 add r6, r6, r2, lsl #2
190 ldr ip, [r1, r6]
191 bic ip, ip, #MDSTAT_STATE_MASK
192 orr ip, ip, r0
193 str ip, [r1, r6]
194
195 /* Enable the Power Domain Transition Command */
196 ldr ip, [r1, #PTCMD]
197 orr ip, ip, #0x1
198 str ip, [r1, #PTCMD]
199
200 /* Check for Transition Complete (PTSTAT) */
201ptstat_done:
202 ldr ip, [r1, #PTSTAT]
203 and ip, ip, #0x1
204 cmp ip, #0x0
205 bne ptstat_done
206
207 /* Check for DDR2 clock disable completion; */
208 mov r6, #MDSTAT
209 add r6, r6, r2, lsl #2
210ddr2clk_stop_done:
211 ldr ip, [r1, r6]
212 and ip, ip, #MDSTAT_STATE_MASK
213 cmp ip, r0
214 bne ddr2clk_stop_done
215
216 mov pc, lr
217ENDPROC(davinci_ddr_psc_config)
218
219CACHE_FLUSH:
220 .word arm926_flush_kern_cache_all
221
222ENTRY(davinci_cpu_suspend_sz)
223 .word . - davinci_cpu_suspend
224ENDPROC(davinci_cpu_suspend_sz)
diff --git a/arch/arm/mach-davinci/sram.c b/arch/arm/mach-davinci/sram.c
index 4f1fc9b318b3..db0f7787faf1 100644
--- a/arch/arm/mach-davinci/sram.c
+++ b/arch/arm/mach-davinci/sram.c
@@ -9,15 +9,12 @@
9 * (at your option) any later version. 9 * (at your option) any later version.
10 */ 10 */
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/init.h> 12#include <linux/init.h>
14#include <linux/genalloc.h> 13#include <linux/genalloc.h>
15 14
16#include <mach/common.h> 15#include <mach/common.h>
17#include <mach/memory.h>
18#include <mach/sram.h> 16#include <mach/sram.h>
19 17
20
21static struct gen_pool *sram_pool; 18static struct gen_pool *sram_pool;
22 19
23void *sram_alloc(size_t len, dma_addr_t *dma) 20void *sram_alloc(size_t len, dma_addr_t *dma)
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 0d1b6d407b46..9e0b106b4f5f 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -14,20 +14,14 @@
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/clocksource.h> 15#include <linux/clocksource.h>
16#include <linux/clockchips.h> 16#include <linux/clockchips.h>
17#include <linux/spinlock.h>
18#include <linux/io.h> 17#include <linux/io.h>
19#include <linux/clk.h> 18#include <linux/clk.h>
20#include <linux/err.h> 19#include <linux/err.h>
21#include <linux/device.h>
22#include <linux/platform_device.h> 20#include <linux/platform_device.h>
23 21
24#include <mach/hardware.h> 22#include <mach/hardware.h>
25#include <asm/system.h>
26#include <asm/irq.h>
27#include <asm/mach/irq.h> 23#include <asm/mach/irq.h>
28#include <asm/mach/time.h> 24#include <asm/mach/time.h>
29#include <asm/errno.h>
30#include <mach/io.h>
31#include <mach/cputype.h> 25#include <mach/cputype.h>
32#include <mach/time.h> 26#include <mach/time.h>
33#include "clock.h" 27#include "clock.h"
@@ -259,8 +253,6 @@ static void __init timer_init(void)
259 irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq; 253 irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
260 setup_irq(irq, &t->irqaction); 254 setup_irq(irq, &t->irqaction);
261 } 255 }
262
263 timer32_config(&timers[i]);
264 } 256 }
265} 257}
266 258
@@ -337,6 +329,7 @@ static void __init davinci_timer_init(void)
337 unsigned int clocksource_id; 329 unsigned int clocksource_id;
338 static char err[] __initdata = KERN_ERR 330 static char err[] __initdata = KERN_ERR
339 "%s: can't register clocksource!\n"; 331 "%s: can't register clocksource!\n";
332 int i;
340 333
341 clockevent_id = soc_info->timer_info->clockevent_id; 334 clockevent_id = soc_info->timer_info->clockevent_id;
342 clocksource_id = soc_info->timer_info->clocksource_id; 335 clocksource_id = soc_info->timer_info->clocksource_id;
@@ -395,6 +388,9 @@ static void __init davinci_timer_init(void)
395 388
396 clockevent_davinci.cpumask = cpumask_of(0); 389 clockevent_davinci.cpumask = cpumask_of(0);
397 clockevents_register_device(&clockevent_davinci); 390 clockevents_register_device(&clockevent_davinci);
391
392 for (i=0; i< ARRAY_SIZE(timers); i++)
393 timer32_config(&timers[i]);
398} 394}
399 395
400struct sys_timer davinci_timer = { 396struct sys_timer davinci_timer = {
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 06f55931620c..31f0cbea0caa 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -1,21 +1,21 @@
1/* 1/*
2 * USB 2 * USB
3 */ 3 */
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/init.h> 4#include <linux/init.h>
7#include <linux/platform_device.h> 5#include <linux/platform_device.h>
8#include <linux/dma-mapping.h> 6#include <linux/dma-mapping.h>
9 7
10#include <linux/usb/musb.h> 8#include <linux/usb/musb.h>
11#include <linux/usb/otg.h>
12 9
13#include <mach/common.h> 10#include <mach/common.h>
14#include <mach/hardware.h>
15#include <mach/irqs.h> 11#include <mach/irqs.h>
16#include <mach/cputype.h> 12#include <mach/cputype.h>
13#include <mach/usb.h>
17 14
18#define DAVINCI_USB_OTG_BASE 0x01C64000 15#define DAVINCI_USB_OTG_BASE 0x01c64000
16
17#define DA8XX_USB0_BASE 0x01e00000
18#define DA8XX_USB1_BASE 0x01e25000
19 19
20#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE) 20#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
21static struct musb_hdrc_eps_bits musb_eps[] = { 21static struct musb_hdrc_eps_bits musb_eps[] = {
@@ -85,10 +85,10 @@ static struct platform_device usb_dev = {
85 .num_resources = ARRAY_SIZE(usb_resources), 85 .num_resources = ARRAY_SIZE(usb_resources),
86}; 86};
87 87
88void __init setup_usb(unsigned mA, unsigned potpgt_msec) 88void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
89{ 89{
90 usb_data.power = mA / 2; 90 usb_data.power = mA > 510 ? 255 : mA / 2;
91 usb_data.potpgt = potpgt_msec / 2; 91 usb_data.potpgt = (potpgt_ms + 1) / 2;
92 92
93 if (cpu_is_davinci_dm646x()) { 93 if (cpu_is_davinci_dm646x()) {
94 /* Override the defaults as DM6467 uses different IRQs. */ 94 /* Override the defaults as DM6467 uses different IRQs. */
@@ -100,11 +100,77 @@ void __init setup_usb(unsigned mA, unsigned potpgt_msec)
100 platform_device_register(&usb_dev); 100 platform_device_register(&usb_dev);
101} 101}
102 102
103#ifdef CONFIG_ARCH_DAVINCI_DA8XX
104static struct resource da8xx_usb20_resources[] = {
105 {
106 .start = DA8XX_USB0_BASE,
107 .end = DA8XX_USB0_BASE + SZ_64K - 1,
108 .flags = IORESOURCE_MEM,
109 },
110 {
111 .start = IRQ_DA8XX_USB_INT,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116int __init da8xx_register_usb20(unsigned mA, unsigned potpgt)
117{
118 usb_data.clock = "usb20";
119 usb_data.power = mA > 510 ? 255 : mA / 2;
120 usb_data.potpgt = (potpgt + 1) / 2;
121
122 usb_dev.resource = da8xx_usb20_resources;
123 usb_dev.num_resources = ARRAY_SIZE(da8xx_usb20_resources);
124
125 return platform_device_register(&usb_dev);
126}
127#endif /* CONFIG_DAVINCI_DA8XX */
128
103#else 129#else
104 130
105void __init setup_usb(unsigned mA, unsigned potpgt_msec) 131void __init davinci_setup_usb(unsigned mA, unsigned potpgt_ms)
106{ 132{
107} 133}
108 134
135#ifdef CONFIG_ARCH_DAVINCI_DA8XX
136int __init da8xx_register_usb20(unsigned mA, unsigned potpgt)
137{
138 return 0;
139}
140#endif
141
109#endif /* CONFIG_USB_MUSB_HDRC */ 142#endif /* CONFIG_USB_MUSB_HDRC */
110 143
144#ifdef CONFIG_ARCH_DAVINCI_DA8XX
145static struct resource da8xx_usb11_resources[] = {
146 [0] = {
147 .start = DA8XX_USB1_BASE,
148 .end = DA8XX_USB1_BASE + SZ_4K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = IRQ_DA8XX_IRQN,
153 .end = IRQ_DA8XX_IRQN,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static u64 da8xx_usb11_dma_mask = DMA_BIT_MASK(32);
159
160static struct platform_device da8xx_usb11_device = {
161 .name = "ohci",
162 .id = 0,
163 .dev = {
164 .dma_mask = &da8xx_usb11_dma_mask,
165 .coherent_dma_mask = DMA_BIT_MASK(32),
166 },
167 .num_resources = ARRAY_SIZE(da8xx_usb11_resources),
168 .resource = da8xx_usb11_resources,
169};
170
171int __init da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata)
172{
173 da8xx_usb11_device.dev.platform_data = pdata;
174 return platform_device_register(&da8xx_usb11_device);
175}
176#endif /* CONFIG_DAVINCI_DA8XX */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-09 10:43:23 -0400