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-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h97
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h269
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h47
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/timex.h22
-rw-r--r--arch/arm/mach-davinci/include/mach/tnetv107x.h61
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h6
8 files changed, 0 insertions, 518 deletions
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 957fb87e832e..1fc84e21664d 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -33,7 +33,6 @@ struct davinci_id {
33#define DAVINCI_CPU_ID_DM365 0x03650000 33#define DAVINCI_CPU_ID_DM365 0x03650000
34#define DAVINCI_CPU_ID_DA830 0x08300000 34#define DAVINCI_CPU_ID_DA830 0x08300000
35#define DAVINCI_CPU_ID_DA850 0x08500000 35#define DAVINCI_CPU_ID_DA850 0x08500000
36#define DAVINCI_CPU_ID_TNETV107X 0x0b8a0000
37 36
38#define IS_DAVINCI_CPU(type, id) \ 37#define IS_DAVINCI_CPU(type, id) \
39static inline int is_davinci_ ##type(void) \ 38static inline int is_davinci_ ##type(void) \
@@ -47,7 +46,6 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
47IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) 46IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
48IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) 47IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
49IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) 48IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850)
50IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
51 49
52#ifdef CONFIG_ARCH_DAVINCI_DM644x 50#ifdef CONFIG_ARCH_DAVINCI_DM644x
53#define cpu_is_davinci_dm644x() is_davinci_dm644x() 51#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -85,10 +83,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
85#define cpu_is_davinci_da850() 0 83#define cpu_is_davinci_da850() 0
86#endif 84#endif
87 85
88#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
89#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
90#else
91#define cpu_is_davinci_tnetv107x() 0
92#endif
93
94#endif 86#endif
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index ec76c7775c2e..354af71798dc 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -401,103 +401,6 @@
401 401
402#define DA850_N_CP_INTC_IRQ 101 402#define DA850_N_CP_INTC_IRQ 101
403 403
404
405/* TNETV107X specific interrupts */
406#define IRQ_TNETV107X_TDM1_TXDMA 0
407#define IRQ_TNETV107X_EXT_INT_0 1
408#define IRQ_TNETV107X_EXT_INT_1 2
409#define IRQ_TNETV107X_GPIO_INT12 3
410#define IRQ_TNETV107X_GPIO_INT13 4
411#define IRQ_TNETV107X_TIMER_0_TINT12 5
412#define IRQ_TNETV107X_TIMER_1_TINT12 6
413#define IRQ_TNETV107X_UART0 7
414#define IRQ_TNETV107X_TDM1_RXDMA 8
415#define IRQ_TNETV107X_MCDMA_INT0 9
416#define IRQ_TNETV107X_MCDMA_INT1 10
417#define IRQ_TNETV107X_TPCC 11
418#define IRQ_TNETV107X_TPCC_INT0 12
419#define IRQ_TNETV107X_TPCC_INT1 13
420#define IRQ_TNETV107X_TPCC_INT2 14
421#define IRQ_TNETV107X_TPCC_INT3 15
422#define IRQ_TNETV107X_TPTC0 16
423#define IRQ_TNETV107X_TPTC1 17
424#define IRQ_TNETV107X_TIMER_0_TINT34 18
425#define IRQ_TNETV107X_ETHSS 19
426#define IRQ_TNETV107X_TIMER_1_TINT34 20
427#define IRQ_TNETV107X_DSP2ARM_INT0 21
428#define IRQ_TNETV107X_DSP2ARM_INT1 22
429#define IRQ_TNETV107X_ARM_NPMUIRQ 23
430#define IRQ_TNETV107X_USB1 24
431#define IRQ_TNETV107X_VLYNQ 25
432#define IRQ_TNETV107X_UART0_DMATX 26
433#define IRQ_TNETV107X_UART0_DMARX 27
434#define IRQ_TNETV107X_TDM1_TXMCSP 28
435#define IRQ_TNETV107X_SSP 29
436#define IRQ_TNETV107X_MCDMA_INT2 30
437#define IRQ_TNETV107X_MCDMA_INT3 31
438#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
439#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
440#define IRQ_TNETV107X_USB0 34
441#define IRQ_TNETV107X_USB_CDMA 35
442#define IRQ_TNETV107X_LCD 36
443#define IRQ_TNETV107X_KEYPAD 37
444#define IRQ_TNETV107X_KEYPAD_FREE 38
445#define IRQ_TNETV107X_RNG 39
446#define IRQ_TNETV107X_PKA 40
447#define IRQ_TNETV107X_TDM0_TXDMA 41
448#define IRQ_TNETV107X_TDM0_RXDMA 42
449#define IRQ_TNETV107X_TDM0_TXMCSP 43
450#define IRQ_TNETV107X_TDM0_RXMCSP 44
451#define IRQ_TNETV107X_TDM1_RXMCSP 45
452#define IRQ_TNETV107X_SDIO1 46
453#define IRQ_TNETV107X_SDIO0 47
454#define IRQ_TNETV107X_TSC 48
455#define IRQ_TNETV107X_TS 49
456#define IRQ_TNETV107X_UART1 50
457#define IRQ_TNETV107X_MBX_LITE 51
458#define IRQ_TNETV107X_GPIO_INT00 52
459#define IRQ_TNETV107X_GPIO_INT01 53
460#define IRQ_TNETV107X_GPIO_INT02 54
461#define IRQ_TNETV107X_GPIO_INT03 55
462#define IRQ_TNETV107X_UART2 56
463#define IRQ_TNETV107X_UART2_DMATX 57
464#define IRQ_TNETV107X_UART2_DMARX 58
465#define IRQ_TNETV107X_IMCOP_IMX 59
466#define IRQ_TNETV107X_IMCOP_VLCD 60
467#define IRQ_TNETV107X_AES 61
468#define IRQ_TNETV107X_DES 62
469#define IRQ_TNETV107X_SHAMD5 63
470#define IRQ_TNETV107X_TPCC_ERR 68
471#define IRQ_TNETV107X_TPCC_PROT 69
472#define IRQ_TNETV107X_TPTC0_ERR 70
473#define IRQ_TNETV107X_TPTC1_ERR 71
474#define IRQ_TNETV107X_UART0_ERR 72
475#define IRQ_TNETV107X_UART1_ERR 73
476#define IRQ_TNETV107X_AEMIF_ERR 74
477#define IRQ_TNETV107X_DDR_ERR 75
478#define IRQ_TNETV107X_WDTARM_INT0 76
479#define IRQ_TNETV107X_MCDMA_ERR 77
480#define IRQ_TNETV107X_GPIO_ERR 78
481#define IRQ_TNETV107X_MPU_ADDR 79
482#define IRQ_TNETV107X_MPU_PROT 80
483#define IRQ_TNETV107X_IOPU_ADDR 81
484#define IRQ_TNETV107X_IOPU_PROT 82
485#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
486#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
487#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
488#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
489#define IRQ_TNETV107X_PLL_UNLOCK 87
490#define IRQ_TNETV107X_WDTDSP_INT0 88
491#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
492#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
493#define IRQ_TNETV107X_PBIST_CPU 91
494#define IRQ_TNETV107X_WDTARM 92
495#define IRQ_TNETV107X_PSC 93
496#define IRQ_TNETV107X_MMC0 94
497#define IRQ_TNETV107X_MMC1 95
498
499#define TNETV107X_N_CP_INTC_IRQ 96
500
501/* da850 currently has the most gpio pins (144) */ 404/* da850 currently has the most gpio pins (144) */
502#define DAVINCI_N_GPIO 144 405#define DAVINCI_N_GPIO 144
503/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */ 406/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 9e95b8a1edb6..631655e68ae0 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -972,275 +972,6 @@ enum davinci_da850_index {
972 DA850_VPIF_CLKO3, 972 DA850_VPIF_CLKO3,
973}; 973};
974 974
975enum davinci_tnetv107x_index {
976 TNETV107X_ASR_A00,
977 TNETV107X_GPIO32,
978 TNETV107X_ASR_A01,
979 TNETV107X_GPIO33,
980 TNETV107X_ASR_A02,
981 TNETV107X_GPIO34,
982 TNETV107X_ASR_A03,
983 TNETV107X_GPIO35,
984 TNETV107X_ASR_A04,
985 TNETV107X_GPIO36,
986 TNETV107X_ASR_A05,
987 TNETV107X_GPIO37,
988 TNETV107X_ASR_A06,
989 TNETV107X_GPIO38,
990 TNETV107X_ASR_A07,
991 TNETV107X_GPIO39,
992 TNETV107X_ASR_A08,
993 TNETV107X_GPIO40,
994 TNETV107X_ASR_A09,
995 TNETV107X_GPIO41,
996 TNETV107X_ASR_A10,
997 TNETV107X_GPIO42,
998 TNETV107X_ASR_A11,
999 TNETV107X_BOOT_STRP_0,
1000 TNETV107X_ASR_A12,
1001 TNETV107X_BOOT_STRP_1,
1002 TNETV107X_ASR_A13,
1003 TNETV107X_GPIO43,
1004 TNETV107X_ASR_A14,
1005 TNETV107X_GPIO44,
1006 TNETV107X_ASR_A15,
1007 TNETV107X_GPIO45,
1008 TNETV107X_ASR_A16,
1009 TNETV107X_GPIO46,
1010 TNETV107X_ASR_A17,
1011 TNETV107X_GPIO47,
1012 TNETV107X_ASR_A18,
1013 TNETV107X_GPIO48,
1014 TNETV107X_SDIO1_DATA3_0,
1015 TNETV107X_ASR_A19,
1016 TNETV107X_GPIO49,
1017 TNETV107X_SDIO1_DATA2_0,
1018 TNETV107X_ASR_A20,
1019 TNETV107X_GPIO50,
1020 TNETV107X_SDIO1_DATA1_0,
1021 TNETV107X_ASR_A21,
1022 TNETV107X_GPIO51,
1023 TNETV107X_SDIO1_DATA0_0,
1024 TNETV107X_ASR_A22,
1025 TNETV107X_GPIO52,
1026 TNETV107X_SDIO1_CMD_0,
1027 TNETV107X_ASR_A23,
1028 TNETV107X_GPIO53,
1029 TNETV107X_SDIO1_CLK_0,
1030 TNETV107X_ASR_BA_1,
1031 TNETV107X_GPIO54,
1032 TNETV107X_SYS_PLL_CLK,
1033 TNETV107X_ASR_CS0,
1034 TNETV107X_ASR_CS1,
1035 TNETV107X_ASR_CS2,
1036 TNETV107X_TDM_PLL_CLK,
1037 TNETV107X_ASR_CS3,
1038 TNETV107X_ETH_PHY_CLK,
1039 TNETV107X_ASR_D00,
1040 TNETV107X_GPIO55,
1041 TNETV107X_ASR_D01,
1042 TNETV107X_GPIO56,
1043 TNETV107X_ASR_D02,
1044 TNETV107X_GPIO57,
1045 TNETV107X_ASR_D03,
1046 TNETV107X_GPIO58,
1047 TNETV107X_ASR_D04,
1048 TNETV107X_GPIO59_0,
1049 TNETV107X_ASR_D05,
1050 TNETV107X_GPIO60_0,
1051 TNETV107X_ASR_D06,
1052 TNETV107X_GPIO61_0,
1053 TNETV107X_ASR_D07,
1054 TNETV107X_GPIO62_0,
1055 TNETV107X_ASR_D08,
1056 TNETV107X_GPIO63_0,
1057 TNETV107X_ASR_D09,
1058 TNETV107X_GPIO64_0,
1059 TNETV107X_ASR_D10,
1060 TNETV107X_SDIO1_DATA3_1,
1061 TNETV107X_ASR_D11,
1062 TNETV107X_SDIO1_DATA2_1,
1063 TNETV107X_ASR_D12,
1064 TNETV107X_SDIO1_DATA1_1,
1065 TNETV107X_ASR_D13,
1066 TNETV107X_SDIO1_DATA0_1,
1067 TNETV107X_ASR_D14,
1068 TNETV107X_SDIO1_CMD_1,
1069 TNETV107X_ASR_D15,
1070 TNETV107X_SDIO1_CLK_1,
1071 TNETV107X_ASR_OE,
1072 TNETV107X_BOOT_STRP_2,
1073 TNETV107X_ASR_RNW,
1074 TNETV107X_GPIO29_0,
1075 TNETV107X_ASR_WAIT,
1076 TNETV107X_GPIO30_0,
1077 TNETV107X_ASR_WE,
1078 TNETV107X_BOOT_STRP_3,
1079 TNETV107X_ASR_WE_DQM0,
1080 TNETV107X_GPIO31,
1081 TNETV107X_LCD_PD17_0,
1082 TNETV107X_ASR_WE_DQM1,
1083 TNETV107X_ASR_BA0_0,
1084 TNETV107X_VLYNQ_CLK,
1085 TNETV107X_GPIO14,
1086 TNETV107X_LCD_PD19_0,
1087 TNETV107X_VLYNQ_RXD0,
1088 TNETV107X_GPIO15,
1089 TNETV107X_LCD_PD20_0,
1090 TNETV107X_VLYNQ_RXD1,
1091 TNETV107X_GPIO16,
1092 TNETV107X_LCD_PD21_0,
1093 TNETV107X_VLYNQ_TXD0,
1094 TNETV107X_GPIO17,
1095 TNETV107X_LCD_PD22_0,
1096 TNETV107X_VLYNQ_TXD1,
1097 TNETV107X_GPIO18,
1098 TNETV107X_LCD_PD23_0,
1099 TNETV107X_SDIO0_CLK,
1100 TNETV107X_GPIO19,
1101 TNETV107X_SDIO0_CMD,
1102 TNETV107X_GPIO20,
1103 TNETV107X_SDIO0_DATA0,
1104 TNETV107X_GPIO21,
1105 TNETV107X_SDIO0_DATA1,
1106 TNETV107X_GPIO22,
1107 TNETV107X_SDIO0_DATA2,
1108 TNETV107X_GPIO23,
1109 TNETV107X_SDIO0_DATA3,
1110 TNETV107X_GPIO24,
1111 TNETV107X_EMU0,
1112 TNETV107X_EMU1,
1113 TNETV107X_RTCK,
1114 TNETV107X_TRST_N,
1115 TNETV107X_TCK,
1116 TNETV107X_TDI,
1117 TNETV107X_TDO,
1118 TNETV107X_TMS,
1119 TNETV107X_TDM1_CLK,
1120 TNETV107X_TDM1_RX,
1121 TNETV107X_TDM1_TX,
1122 TNETV107X_TDM1_FS,
1123 TNETV107X_KEYPAD_R0,
1124 TNETV107X_KEYPAD_R1,
1125 TNETV107X_KEYPAD_R2,
1126 TNETV107X_KEYPAD_R3,
1127 TNETV107X_KEYPAD_R4,
1128 TNETV107X_KEYPAD_R5,
1129 TNETV107X_KEYPAD_R6,
1130 TNETV107X_GPIO12,
1131 TNETV107X_KEYPAD_R7,
1132 TNETV107X_GPIO10,
1133 TNETV107X_KEYPAD_C0,
1134 TNETV107X_KEYPAD_C1,
1135 TNETV107X_KEYPAD_C2,
1136 TNETV107X_KEYPAD_C3,
1137 TNETV107X_KEYPAD_C4,
1138 TNETV107X_KEYPAD_C5,
1139 TNETV107X_KEYPAD_C6,
1140 TNETV107X_GPIO13,
1141 TNETV107X_TEST_CLK_IN,
1142 TNETV107X_KEYPAD_C7,
1143 TNETV107X_GPIO11,
1144 TNETV107X_SSP0_0,
1145 TNETV107X_SCC_DCLK,
1146 TNETV107X_LCD_PD20_1,
1147 TNETV107X_SSP0_1,
1148 TNETV107X_SCC_CS_N,
1149 TNETV107X_LCD_PD21_1,
1150 TNETV107X_SSP0_2,
1151 TNETV107X_SCC_D,
1152 TNETV107X_LCD_PD22_1,
1153 TNETV107X_SSP0_3,
1154 TNETV107X_SCC_RESETN,
1155 TNETV107X_LCD_PD23_1,
1156 TNETV107X_SSP1_0,
1157 TNETV107X_GPIO25,
1158 TNETV107X_UART2_CTS,
1159 TNETV107X_SSP1_1,
1160 TNETV107X_GPIO26,
1161 TNETV107X_UART2_RD,
1162 TNETV107X_SSP1_2,
1163 TNETV107X_GPIO27,
1164 TNETV107X_UART2_RTS,
1165 TNETV107X_SSP1_3,
1166 TNETV107X_GPIO28,
1167 TNETV107X_UART2_TD,
1168 TNETV107X_UART0_CTS,
1169 TNETV107X_UART0_RD,
1170 TNETV107X_UART0_RTS,
1171 TNETV107X_UART0_TD,
1172 TNETV107X_UART1_RD,
1173 TNETV107X_UART1_TD,
1174 TNETV107X_LCD_AC_NCS,
1175 TNETV107X_LCD_HSYNC_RNW,
1176 TNETV107X_LCD_VSYNC_A0,
1177 TNETV107X_LCD_MCLK,
1178 TNETV107X_LCD_PD16_0,
1179 TNETV107X_LCD_PCLK_E,
1180 TNETV107X_LCD_PD00,
1181 TNETV107X_LCD_PD01,
1182 TNETV107X_LCD_PD02,
1183 TNETV107X_LCD_PD03,
1184 TNETV107X_LCD_PD04,
1185 TNETV107X_LCD_PD05,
1186 TNETV107X_LCD_PD06,
1187 TNETV107X_LCD_PD07,
1188 TNETV107X_LCD_PD08,
1189 TNETV107X_GPIO59_1,
1190 TNETV107X_LCD_PD09,
1191 TNETV107X_GPIO60_1,
1192 TNETV107X_LCD_PD10,
1193 TNETV107X_ASR_BA0_1,
1194 TNETV107X_GPIO61_1,
1195 TNETV107X_LCD_PD11,
1196 TNETV107X_GPIO62_1,
1197 TNETV107X_LCD_PD12,
1198 TNETV107X_GPIO63_1,
1199 TNETV107X_LCD_PD13,
1200 TNETV107X_GPIO64_1,
1201 TNETV107X_LCD_PD14,
1202 TNETV107X_GPIO29_1,
1203 TNETV107X_LCD_PD15,
1204 TNETV107X_GPIO30_1,
1205 TNETV107X_EINT0,
1206 TNETV107X_GPIO08,
1207 TNETV107X_EINT1,
1208 TNETV107X_GPIO09,
1209 TNETV107X_GPIO00,
1210 TNETV107X_LCD_PD20_2,
1211 TNETV107X_TDM_CLK_IN_2,
1212 TNETV107X_GPIO01,
1213 TNETV107X_LCD_PD21_2,
1214 TNETV107X_24M_CLK_OUT_1,
1215 TNETV107X_GPIO02,
1216 TNETV107X_LCD_PD22_2,
1217 TNETV107X_GPIO03,
1218 TNETV107X_LCD_PD23_2,
1219 TNETV107X_GPIO04,
1220 TNETV107X_LCD_PD16_1,
1221 TNETV107X_USB0_RXERR,
1222 TNETV107X_GPIO05,
1223 TNETV107X_LCD_PD17_1,
1224 TNETV107X_TDM_CLK_IN_1,
1225 TNETV107X_GPIO06,
1226 TNETV107X_LCD_PD18,
1227 TNETV107X_24M_CLK_OUT_2,
1228 TNETV107X_GPIO07,
1229 TNETV107X_LCD_PD19_1,
1230 TNETV107X_USB1_RXERR,
1231 TNETV107X_ETH_PLL_CLK,
1232 TNETV107X_MDIO,
1233 TNETV107X_MDC,
1234 TNETV107X_AIC_MUTE_STAT_N,
1235 TNETV107X_TDM0_CLK,
1236 TNETV107X_AIC_HNS_EN_N,
1237 TNETV107X_TDM0_FS,
1238 TNETV107X_AIC_HDS_EN_STAT_N,
1239 TNETV107X_TDM0_TX,
1240 TNETV107X_AIC_HNF_EN_STAT_N,
1241 TNETV107X_TDM0_RX,
1242};
1243
1244#define PINMUX(x) (4 * (x)) 975#define PINMUX(x) (4 * (x))
1245 976
1246#ifdef CONFIG_DAVINCI_MUX 977#ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 0a22710493fd..99d47cfa301f 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -182,53 +182,6 @@
182#define DA8XX_LPSC1_CR_P3_SS 26 182#define DA8XX_LPSC1_CR_P3_SS 26
183#define DA8XX_LPSC1_L3_CBA_RAM 31 183#define DA8XX_LPSC1_L3_CBA_RAM 31
184 184
185/* TNETV107X LPSC Assignments */
186#define TNETV107X_LPSC_ARM 0
187#define TNETV107X_LPSC_GEM 1
188#define TNETV107X_LPSC_DDR2_PHY 2
189#define TNETV107X_LPSC_TPCC 3
190#define TNETV107X_LPSC_TPTC0 4
191#define TNETV107X_LPSC_TPTC1 5
192#define TNETV107X_LPSC_RAM 6
193#define TNETV107X_LPSC_MBX_LITE 7
194#define TNETV107X_LPSC_LCD 8
195#define TNETV107X_LPSC_ETHSS 9
196#define TNETV107X_LPSC_AEMIF 10
197#define TNETV107X_LPSC_CHIP_CFG 11
198#define TNETV107X_LPSC_TSC 12
199#define TNETV107X_LPSC_ROM 13
200#define TNETV107X_LPSC_UART2 14
201#define TNETV107X_LPSC_PKTSEC 15
202#define TNETV107X_LPSC_SECCTL 16
203#define TNETV107X_LPSC_KEYMGR 17
204#define TNETV107X_LPSC_KEYPAD 18
205#define TNETV107X_LPSC_GPIO 19
206#define TNETV107X_LPSC_MDIO 20
207#define TNETV107X_LPSC_SDIO0 21
208#define TNETV107X_LPSC_UART0 22
209#define TNETV107X_LPSC_UART1 23
210#define TNETV107X_LPSC_TIMER0 24
211#define TNETV107X_LPSC_TIMER1 25
212#define TNETV107X_LPSC_WDT_ARM 26
213#define TNETV107X_LPSC_WDT_DSP 27
214#define TNETV107X_LPSC_SSP 28
215#define TNETV107X_LPSC_TDM0 29
216#define TNETV107X_LPSC_VLYNQ 30
217#define TNETV107X_LPSC_MCDMA 31
218#define TNETV107X_LPSC_USB0 32
219#define TNETV107X_LPSC_TDM1 33
220#define TNETV107X_LPSC_DEBUGSS 34
221#define TNETV107X_LPSC_ETHSS_RGMII 35
222#define TNETV107X_LPSC_SYSTEM 36
223#define TNETV107X_LPSC_IMCOP 37
224#define TNETV107X_LPSC_SPARE 38
225#define TNETV107X_LPSC_SDIO1 39
226#define TNETV107X_LPSC_USB1 40
227#define TNETV107X_LPSC_USBSS 41
228#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42
229#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43
230#define TNETV107X_LPSC_MAX 44
231
232/* PSC register offsets */ 185/* PSC register offsets */
233#define EPCPR 0x070 186#define EPCPR 0x070
234#define PTCMD 0x120 187#define PTCMD 0x120
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index ce402cd21fa0..d4b4aa87964f 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -23,14 +23,6 @@
23#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000) 23#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
24#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000) 24#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
25 25
26#define TNETV107X_UART0_BASE 0x08108100
27#define TNETV107X_UART1_BASE 0x08088400
28#define TNETV107X_UART2_BASE 0x08108300
29
30#define TNETV107X_UART0_VIRT IOMEM(0xfee08100)
31#define TNETV107X_UART1_VIRT IOMEM(0xfed88400)
32#define TNETV107X_UART2_VIRT IOMEM(0xfee08300)
33
34/* DaVinci UART register offsets */ 26/* DaVinci UART register offsets */
35#define UART_DAVINCI_PWREMU 0x0c 27#define UART_DAVINCI_PWREMU 0x0c
36#define UART_DM646X_SCR 0x10 28#define UART_DM646X_SCR 0x10
diff --git a/arch/arm/mach-davinci/include/mach/timex.h b/arch/arm/mach-davinci/include/mach/timex.h
deleted file mode 100644
index 9b885298f106..000000000000
--- a/arch/arm/mach-davinci/include/mach/timex.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * DaVinci timer defines
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_TIMEX_H
12#define __ASM_ARCH_TIMEX_H
13
14/*
15 * Alert: Not all timers of the DaVinci family run at a frequency of 27MHz,
16 * but we should be fine as long as CLOCK_TICK_RATE or LATCH (see include/
17 * linux/jiffies.h) are not used directly in code. Currently none of the
18 * code relevant to DaVinci platform depends on these values directly.
19 */
20#define CLOCK_TICK_RATE 27000000
21
22#endif /* __ASM_ARCH_TIMEX_H__ */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
deleted file mode 100644
index 494fcf5ccfe1..000000000000
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Texas Instruments TNETV107X SoC Specific Defines
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef __ASM_ARCH_DAVINCI_TNETV107X_H
16#define __ASM_ARCH_DAVINCI_TNETV107X_H
17
18#include <asm/sizes.h>
19
20#define TNETV107X_DDR_BASE 0x80000000
21
22/*
23 * Fixed mapping for early init starts here. If low-level debug is enabled,
24 * this area also gets mapped via io_pg_offset and io_phys by the boot code.
25 * To fit in with the io_pg_offset calculation, the io base address selected
26 * here _must_ be a multiple of 2^20.
27 */
28#define TNETV107X_IO_BASE 0x08000000
29#define TNETV107X_IO_VIRT (IO_VIRT + SZ_1M)
30
31#define TNETV107X_N_GPIO 65
32
33#ifndef __ASSEMBLY__
34
35#include <linux/serial_8250.h>
36#include <linux/input/matrix_keypad.h>
37#include <linux/mfd/ti_ssp.h>
38#include <linux/reboot.h>
39
40#include <linux/platform_data/mmc-davinci.h>
41#include <linux/platform_data/mtd-davinci.h>
42#include <mach/serial.h>
43
44struct tnetv107x_device_info {
45 struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
46 struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
47 struct matrix_keypad_platform_data *keypad_config;
48 struct ti_ssp_data *ssp_config;
49};
50
51extern struct platform_device tnetv107x_wdt_device;
52extern struct platform_device tnetv107x_serial_device[];
53
54extern void tnetv107x_init(void);
55extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
56extern void tnetv107x_irq_init(void);
57void tnetv107x_restart(enum reboot_mode mode, const char *cmd);
58
59#endif
60
61#endif /* __ASM_ARCH_DAVINCI_TNETV107X_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index f49c2916aa3a..8fb97b93b6bb 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -68,9 +68,6 @@ static inline void set_uart_info(u32 phys)
68#define DEBUG_LL_DA8XX(machine, port) \ 68#define DEBUG_LL_DA8XX(machine, port) \
69 _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE) 69 _DEBUG_LL_ENTRY(machine, DA8XX_UART##port##_BASE)
70 70
71#define DEBUG_LL_TNETV107X(machine, port) \
72 _DEBUG_LL_ENTRY(machine, TNETV107X_UART##port##_BASE)
73
74static inline void __arch_decomp_setup(unsigned long arch_id) 71static inline void __arch_decomp_setup(unsigned long arch_id)
75{ 72{
76 /* 73 /*
@@ -94,9 +91,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
94 DEBUG_LL_DA8XX(davinci_da850_evm, 2); 91 DEBUG_LL_DA8XX(davinci_da850_evm, 2);
95 DEBUG_LL_DA8XX(mityomapl138, 1); 92 DEBUG_LL_DA8XX(mityomapl138, 1);
96 DEBUG_LL_DA8XX(omapl138_hawkboard, 2); 93 DEBUG_LL_DA8XX(omapl138_hawkboard, 2);
97
98 /* TNETV107x boards */
99 DEBUG_LL_TNETV107X(tnetv107x, 1);
100 } while (0); 94 } while (0);
101} 95}
102 96
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 10:23:37 -0400