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-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h69
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h48
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h109
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h9
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h404
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h41
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h4
8 files changed, 688 insertions, 4 deletions
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 56b92d49e293..fd41189e5c62 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -31,6 +31,7 @@ struct davinci_id {
31#define DAVINCI_CPU_ID_DM6467 0x64670000 31#define DAVINCI_CPU_ID_DM6467 0x64670000
32#define DAVINCI_CPU_ID_DM355 0x03550000 32#define DAVINCI_CPU_ID_DM355 0x03550000
33#define DAVINCI_CPU_ID_DM365 0x03650000 33#define DAVINCI_CPU_ID_DM365 0x03650000
34#define DAVINCI_CPU_ID_DA830 0x08300000
34 35
35#define IS_DAVINCI_CPU(type, id) \ 36#define IS_DAVINCI_CPU(type, id) \
36static inline int is_davinci_ ##type(void) \ 37static inline int is_davinci_ ##type(void) \
@@ -42,6 +43,7 @@ IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
42IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) 43IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
43IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) 44IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
44IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) 45IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
46IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
45 47
46#ifdef CONFIG_ARCH_DAVINCI_DM644x 48#ifdef CONFIG_ARCH_DAVINCI_DM644x
47#define cpu_is_davinci_dm644x() is_davinci_dm644x() 49#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -67,4 +69,10 @@ IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
67#define cpu_is_davinci_dm365() 0 69#define cpu_is_davinci_dm365() 0
68#endif 70#endif
69 71
72#ifdef CONFIG_ARCH_DAVINCI_DA830
73#define cpu_is_davinci_da830() is_davinci_da830()
74#else
75#define cpu_is_davinci_da830() 0
76#endif
77
70#endif 78#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
new file mode 100644
index 000000000000..084db271c7c4
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -0,0 +1,69 @@
1/*
2 * Chip specific defines for DA8XX/OMAP L1XX SoC
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
12#define __ASM_ARCH_DAVINCI_DA8XX_H
13
14#include <mach/serial.h>
15#include <mach/edma.h>
16#include <mach/i2c.h>
17#include <mach/emac.h>
18
19/*
20 * The cp_intc interrupt controller for the da8xx isn't in the same
21 * chunk of physical memory space as the other registers (like it is
22 * on the davincis) so it needs to be mapped separately. It will be
23 * mapped early on when the I/O space is mapped and we'll put it just
24 * before the I/O space in the processor's virtual memory space.
25 */
26#define DA8XX_CP_INTC_BASE 0xfffee000
27#define DA8XX_CP_INTC_SIZE SZ_8K
28#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
29
30#define DA8XX_BOOT_CFG_BASE (IO_PHYS + 0x14000)
31
32void __init da830_init(void);
33
34int da8xx_register_edma(void);
35int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
36int da8xx_register_watchdog(void);
37int da8xx_register_emac(void);
38
39extern struct platform_device da8xx_serial_device;
40extern struct emac_platform_data da8xx_emac_pdata;
41
42extern const short da830_emif25_pins[];
43extern const short da830_spi0_pins[];
44extern const short da830_spi1_pins[];
45extern const short da830_mmc_sd_pins[];
46extern const short da830_uart0_pins[];
47extern const short da830_uart1_pins[];
48extern const short da830_uart2_pins[];
49extern const short da830_usb20_pins[];
50extern const short da830_usb11_pins[];
51extern const short da830_uhpi_pins[];
52extern const short da830_cpgmac_pins[];
53extern const short da830_emif3c_pins[];
54extern const short da830_mcasp0_pins[];
55extern const short da830_mcasp1_pins[];
56extern const short da830_mcasp2_pins[];
57extern const short da830_i2c0_pins[];
58extern const short da830_i2c1_pins[];
59extern const short da830_lcdcntl_pins[];
60extern const short da830_pwm_pins[];
61extern const short da830_ecap0_pins[];
62extern const short da830_ecap1_pins[];
63extern const short da830_ecap2_pins[];
64extern const short da830_eqep0_pins[];
65extern const short da830_eqep1_pins[];
66
67int da830_pinmux_setup(const short pins[]);
68
69#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index ba2ebdd058a0..a85cbedc9b0a 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -139,6 +139,54 @@ struct edmacc_param {
139#define DAVINCI_DMA_PWM1 53 139#define DAVINCI_DMA_PWM1 53
140#define DAVINCI_DMA_PWM2 54 140#define DAVINCI_DMA_PWM2 54
141 141
142/* DA830 specific EDMA3 information */
143#define EDMA_DA830_NUM_DMACH 32
144#define EDMA_DA830_NUM_TCC 32
145#define EDMA_DA830_NUM_PARAMENTRY 128
146#define EDMA_DA830_NUM_EVQUE 2
147#define EDMA_DA830_NUM_TC 2
148#define EDMA_DA830_CHMAP_EXIST 0
149#define EDMA_DA830_NUM_REGIONS 4
150#define DA830_DMACH2EVENT_MAP0 0x000FC03Fu
151#define DA830_DMACH2EVENT_MAP1 0x00000000u
152#define DA830_EDMA_ARM_OWN 0x30FFCCFFu
153
154/* DA830 specific EDMA3 Events Information */
155enum DA830_edma_ch {
156 DA830_DMACH_MCASP0_RX,
157 DA830_DMACH_MCASP0_TX,
158 DA830_DMACH_MCASP1_RX,
159 DA830_DMACH_MCASP1_TX,
160 DA830_DMACH_MCASP2_RX,
161 DA830_DMACH_MCASP2_TX,
162 DA830_DMACH_GPIO_BNK0INT,
163 DA830_DMACH_GPIO_BNK1INT,
164 DA830_DMACH_UART0_RX,
165 DA830_DMACH_UART0_TX,
166 DA830_DMACH_TMR64P0_EVTOUT12,
167 DA830_DMACH_TMR64P0_EVTOUT34,
168 DA830_DMACH_UART1_RX,
169 DA830_DMACH_UART1_TX,
170 DA830_DMACH_SPI0_RX,
171 DA830_DMACH_SPI0_TX,
172 DA830_DMACH_MMCSD_RX,
173 DA830_DMACH_MMCSD_TX,
174 DA830_DMACH_SPI1_RX,
175 DA830_DMACH_SPI1_TX,
176 DA830_DMACH_DMAX_EVTOUT6,
177 DA830_DMACH_DMAX_EVTOUT7,
178 DA830_DMACH_GPIO_BNK2INT,
179 DA830_DMACH_GPIO_BNK3INT,
180 DA830_DMACH_I2C0_RX,
181 DA830_DMACH_I2C0_TX,
182 DA830_DMACH_I2C1_RX,
183 DA830_DMACH_I2C1_TX,
184 DA830_DMACH_GPIO_BNK4INT,
185 DA830_DMACH_GPIO_BNK5INT,
186 DA830_DMACH_UART2_RX,
187 DA830_DMACH_UART2_TX
188};
189
142/*ch_status paramater of callback function possible values*/ 190/*ch_status paramater of callback function possible values*/
143#define DMA_COMPLETE 1 191#define DMA_COMPLETE 1
144#define DMA_CC_ERROR 2 192#define DMA_CC_ERROR 2
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 0d34f2fb0993..735e378d27ee 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -99,9 +99,6 @@
99#define IRQ_EMUINT 63 99#define IRQ_EMUINT 63
100 100
101#define DAVINCI_N_AINTC_IRQ 64 101#define DAVINCI_N_AINTC_IRQ 64
102#define DAVINCI_N_GPIO 104
103
104#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
105 102
106#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
107 104
@@ -242,4 +239,110 @@
242#define IRQ_DM365_TCERRINT3 62 239#define IRQ_DM365_TCERRINT3 62
243#define IRQ_DM365_EMUINT 63 240#define IRQ_DM365_EMUINT 63
244 241
242/* DA8XX interrupts */
243#define IRQ_DA8XX_COMMTX 0
244#define IRQ_DA8XX_COMMRX 1
245#define IRQ_DA8XX_NINT 2
246#define IRQ_DA8XX_EVTOUT0 3
247#define IRQ_DA8XX_EVTOUT1 4
248#define IRQ_DA8XX_EVTOUT2 5
249#define IRQ_DA8XX_EVTOUT3 6
250#define IRQ_DA8XX_EVTOUT4 7
251#define IRQ_DA8XX_EVTOUT5 8
252#define IRQ_DA8XX_EVTOUT6 9
253#define IRQ_DA8XX_EVTOUT7 10
254#define IRQ_DA8XX_CCINT0 11
255#define IRQ_DA8XX_CCERRINT 12
256#define IRQ_DA8XX_TCERRINT0 13
257#define IRQ_DA8XX_AEMIFINT 14
258#define IRQ_DA8XX_I2CINT0 15
259#define IRQ_DA8XX_MMCSDINT0 16
260#define IRQ_DA8XX_MMCSDINT1 17
261#define IRQ_DA8XX_ALLINT0 18
262#define IRQ_DA8XX_RTC 19
263#define IRQ_DA8XX_SPINT0 20
264#define IRQ_DA8XX_TINT12_0 21
265#define IRQ_DA8XX_TINT34_0 22
266#define IRQ_DA8XX_TINT12_1 23
267#define IRQ_DA8XX_TINT34_1 24
268#define IRQ_DA8XX_UARTINT0 25
269#define IRQ_DA8XX_KEYMGRINT 26
270#define IRQ_DA8XX_SECINT 26
271#define IRQ_DA8XX_SECKEYERR 26
272#define IRQ_DA8XX_CHIPINT0 28
273#define IRQ_DA8XX_CHIPINT1 29
274#define IRQ_DA8XX_CHIPINT2 30
275#define IRQ_DA8XX_CHIPINT3 31
276#define IRQ_DA8XX_TCERRINT1 32
277#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33
278#define IRQ_DA8XX_C0_RX_PULSE 34
279#define IRQ_DA8XX_C0_TX_PULSE 35
280#define IRQ_DA8XX_C0_MISC_PULSE 36
281#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37
282#define IRQ_DA8XX_C1_RX_PULSE 38
283#define IRQ_DA8XX_C1_TX_PULSE 39
284#define IRQ_DA8XX_C1_MISC_PULSE 40
285#define IRQ_DA8XX_MEMERR 41
286#define IRQ_DA8XX_GPIO0 42
287#define IRQ_DA8XX_GPIO1 43
288#define IRQ_DA8XX_GPIO2 44
289#define IRQ_DA8XX_GPIO3 45
290#define IRQ_DA8XX_GPIO4 46
291#define IRQ_DA8XX_GPIO5 47
292#define IRQ_DA8XX_GPIO6 48
293#define IRQ_DA8XX_GPIO7 49
294#define IRQ_DA8XX_GPIO8 50
295#define IRQ_DA8XX_I2CINT1 51
296#define IRQ_DA8XX_LCDINT 52
297#define IRQ_DA8XX_UARTINT1 53
298#define IRQ_DA8XX_MCASPINT 54
299#define IRQ_DA8XX_ALLINT1 55
300#define IRQ_DA8XX_SPINT1 56
301#define IRQ_DA8XX_UHPI_INT1 57
302#define IRQ_DA8XX_USB_INT 58
303#define IRQ_DA8XX_IRQN 59
304#define IRQ_DA8XX_RWAKEUP 60
305#define IRQ_DA8XX_UARTINT2 61
306#define IRQ_DA8XX_DFTSSINT 62
307#define IRQ_DA8XX_EHRPWM0 63
308#define IRQ_DA8XX_EHRPWM0TZ 64
309#define IRQ_DA8XX_EHRPWM1 65
310#define IRQ_DA8XX_EHRPWM1TZ 66
311#define IRQ_DA8XX_ECAP0 69
312#define IRQ_DA8XX_ECAP1 70
313#define IRQ_DA8XX_ECAP2 71
314#define IRQ_DA8XX_ARMCLKSTOPREQ 90
315
316/* DA830 specific interrupts */
317#define IRQ_DA830_MPUERR 27
318#define IRQ_DA830_IOPUERR 27
319#define IRQ_DA830_BOOTCFGERR 27
320#define IRQ_DA830_EHRPWM2 67
321#define IRQ_DA830_EHRPWM2TZ 68
322#define IRQ_DA830_EQEP0 72
323#define IRQ_DA830_EQEP1 73
324#define IRQ_DA830_T12CMPINT0_0 74
325#define IRQ_DA830_T12CMPINT1_0 75
326#define IRQ_DA830_T12CMPINT2_0 76
327#define IRQ_DA830_T12CMPINT3_0 77
328#define IRQ_DA830_T12CMPINT4_0 78
329#define IRQ_DA830_T12CMPINT5_0 79
330#define IRQ_DA830_T12CMPINT6_0 80
331#define IRQ_DA830_T12CMPINT7_0 81
332#define IRQ_DA830_T12CMPINT0_1 82
333#define IRQ_DA830_T12CMPINT1_1 83
334#define IRQ_DA830_T12CMPINT2_1 84
335#define IRQ_DA830_T12CMPINT3_1 85
336#define IRQ_DA830_T12CMPINT4_1 86
337#define IRQ_DA830_T12CMPINT5_1 87
338#define IRQ_DA830_T12CMPINT6_1 88
339#define IRQ_DA830_T12CMPINT7_1 89
340
341#define DA830_N_CP_INTC_IRQ 96
342
343/* da830 currently has the most gpio pins (128) */
344#define DAVINCI_N_GPIO 128
345/* da830 currently has the most irqs so use DA830_N_CP_INTC_IRQ */
346#define NR_IRQS (DA830_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
347
245#endif /* __ASM_ARCH_IRQS_H */ 348#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index c712c7cdf38f..80309aed534a 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -20,9 +20,16 @@
20/************************************************************************** 20/**************************************************************************
21 * Definitions 21 * Definitions
22 **************************************************************************/ 22 **************************************************************************/
23#define DAVINCI_DDR_BASE 0x80000000 23#define DAVINCI_DDR_BASE 0x80000000
24#define DA8XX_DDR_BASE 0xc0000000
24 25
26#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
27#error Cannot enable DaVinci and DA8XX platforms concurrently
28#elif defined(CONFIG_ARCH_DAVINCI_DA8XX)
29#define PHYS_OFFSET DA8XX_DDR_BASE
30#else
25#define PHYS_OFFSET DAVINCI_DDR_BASE 31#define PHYS_OFFSET DAVINCI_DDR_BASE
32#endif
26 33
27/* 34/*
28 * Increase size of DMA-consistent memory region 35 * Increase size of DMA-consistent memory region
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 55765e1fdb78..ae4f6dd3623c 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -242,6 +242,410 @@ enum davinci_dm365_index {
242 DM365_EVT26_MMC0_RX, 242 DM365_EVT26_MMC0_RX,
243}; 243};
244 244
245enum da830_index {
246 DA830_GPIO7_14,
247 DA830_RTCK,
248 DA830_GPIO7_15,
249 DA830_EMU_0,
250 DA830_EMB_SDCKE,
251 DA830_EMB_CLK_GLUE,
252 DA830_EMB_CLK,
253 DA830_NEMB_CS_0,
254 DA830_NEMB_CAS,
255 DA830_NEMB_RAS,
256 DA830_NEMB_WE,
257 DA830_EMB_BA_1,
258 DA830_EMB_BA_0,
259 DA830_EMB_A_0,
260 DA830_EMB_A_1,
261 DA830_EMB_A_2,
262 DA830_EMB_A_3,
263 DA830_EMB_A_4,
264 DA830_EMB_A_5,
265 DA830_GPIO7_0,
266 DA830_GPIO7_1,
267 DA830_GPIO7_2,
268 DA830_GPIO7_3,
269 DA830_GPIO7_4,
270 DA830_GPIO7_5,
271 DA830_GPIO7_6,
272 DA830_GPIO7_7,
273 DA830_EMB_A_6,
274 DA830_EMB_A_7,
275 DA830_EMB_A_8,
276 DA830_EMB_A_9,
277 DA830_EMB_A_10,
278 DA830_EMB_A_11,
279 DA830_EMB_A_12,
280 DA830_EMB_D_31,
281 DA830_GPIO7_8,
282 DA830_GPIO7_9,
283 DA830_GPIO7_10,
284 DA830_GPIO7_11,
285 DA830_GPIO7_12,
286 DA830_GPIO7_13,
287 DA830_GPIO3_13,
288 DA830_EMB_D_30,
289 DA830_EMB_D_29,
290 DA830_EMB_D_28,
291 DA830_EMB_D_27,
292 DA830_EMB_D_26,
293 DA830_EMB_D_25,
294 DA830_EMB_D_24,
295 DA830_EMB_D_23,
296 DA830_EMB_D_22,
297 DA830_EMB_D_21,
298 DA830_EMB_D_20,
299 DA830_EMB_D_19,
300 DA830_EMB_D_18,
301 DA830_EMB_D_17,
302 DA830_EMB_D_16,
303 DA830_NEMB_WE_DQM_3,
304 DA830_NEMB_WE_DQM_2,
305 DA830_EMB_D_0,
306 DA830_EMB_D_1,
307 DA830_EMB_D_2,
308 DA830_EMB_D_3,
309 DA830_EMB_D_4,
310 DA830_EMB_D_5,
311 DA830_EMB_D_6,
312 DA830_GPIO6_0,
313 DA830_GPIO6_1,
314 DA830_GPIO6_2,
315 DA830_GPIO6_3,
316 DA830_GPIO6_4,
317 DA830_GPIO6_5,
318 DA830_GPIO6_6,
319 DA830_EMB_D_7,
320 DA830_EMB_D_8,
321 DA830_EMB_D_9,
322 DA830_EMB_D_10,
323 DA830_EMB_D_11,
324 DA830_EMB_D_12,
325 DA830_EMB_D_13,
326 DA830_EMB_D_14,
327 DA830_GPIO6_7,
328 DA830_GPIO6_8,
329 DA830_GPIO6_9,
330 DA830_GPIO6_10,
331 DA830_GPIO6_11,
332 DA830_GPIO6_12,
333 DA830_GPIO6_13,
334 DA830_GPIO6_14,
335 DA830_EMB_D_15,
336 DA830_NEMB_WE_DQM_1,
337 DA830_NEMB_WE_DQM_0,
338 DA830_SPI0_SOMI_0,
339 DA830_SPI0_SIMO_0,
340 DA830_SPI0_CLK,
341 DA830_NSPI0_ENA,
342 DA830_NSPI0_SCS_0,
343 DA830_EQEP0I,
344 DA830_EQEP0S,
345 DA830_EQEP1I,
346 DA830_NUART0_CTS,
347 DA830_NUART0_RTS,
348 DA830_EQEP0A,
349 DA830_EQEP0B,
350 DA830_GPIO6_15,
351 DA830_GPIO5_14,
352 DA830_GPIO5_15,
353 DA830_GPIO5_0,
354 DA830_GPIO5_1,
355 DA830_GPIO5_2,
356 DA830_GPIO5_3,
357 DA830_GPIO5_4,
358 DA830_SPI1_SOMI_0,
359 DA830_SPI1_SIMO_0,
360 DA830_SPI1_CLK,
361 DA830_UART0_RXD,
362 DA830_UART0_TXD,
363 DA830_AXR1_10,
364 DA830_AXR1_11,
365 DA830_NSPI1_ENA,
366 DA830_I2C1_SCL,
367 DA830_I2C1_SDA,
368 DA830_EQEP1S,
369 DA830_I2C0_SDA,
370 DA830_I2C0_SCL,
371 DA830_UART2_RXD,
372 DA830_TM64P0_IN12,
373 DA830_TM64P0_OUT12,
374 DA830_GPIO5_5,
375 DA830_GPIO5_6,
376 DA830_GPIO5_7,
377 DA830_GPIO5_8,
378 DA830_GPIO5_9,
379 DA830_GPIO5_10,
380 DA830_GPIO5_11,
381 DA830_GPIO5_12,
382 DA830_NSPI1_SCS_0,
383 DA830_USB0_DRVVBUS,
384 DA830_AHCLKX0,
385 DA830_ACLKX0,
386 DA830_AFSX0,
387 DA830_AHCLKR0,
388 DA830_ACLKR0,
389 DA830_AFSR0,
390 DA830_UART2_TXD,
391 DA830_AHCLKX2,
392 DA830_ECAP0_APWM0,
393 DA830_RMII_MHZ_50_CLK,
394 DA830_ECAP1_APWM1,
395 DA830_USB_REFCLKIN,
396 DA830_GPIO5_13,
397 DA830_GPIO4_15,
398 DA830_GPIO2_11,
399 DA830_GPIO2_12,
400 DA830_GPIO2_13,
401 DA830_GPIO2_14,
402 DA830_GPIO2_15,
403 DA830_GPIO3_12,
404 DA830_AMUTE0,
405 DA830_AXR0_0,
406 DA830_AXR0_1,
407 DA830_AXR0_2,
408 DA830_AXR0_3,
409 DA830_AXR0_4,
410 DA830_AXR0_5,
411 DA830_AXR0_6,
412 DA830_RMII_TXD_0,
413 DA830_RMII_TXD_1,
414 DA830_RMII_TXEN,
415 DA830_RMII_CRS_DV,
416 DA830_RMII_RXD_0,
417 DA830_RMII_RXD_1,
418 DA830_RMII_RXER,
419 DA830_AFSR2,
420 DA830_ACLKX2,
421 DA830_AXR2_3,
422 DA830_AXR2_2,
423 DA830_AXR2_1,
424 DA830_AFSX2,
425 DA830_ACLKR2,
426 DA830_NRESETOUT,
427 DA830_GPIO3_0,
428 DA830_GPIO3_1,
429 DA830_GPIO3_2,
430 DA830_GPIO3_3,
431 DA830_GPIO3_4,
432 DA830_GPIO3_5,
433 DA830_GPIO3_6,
434 DA830_AXR0_7,
435 DA830_AXR0_8,
436 DA830_UART1_RXD,
437 DA830_UART1_TXD,
438 DA830_AXR0_11,
439 DA830_AHCLKX1,
440 DA830_ACLKX1,
441 DA830_AFSX1,
442 DA830_MDIO_CLK,
443 DA830_MDIO_D,
444 DA830_AXR0_9,
445 DA830_AXR0_10,
446 DA830_EPWM0B,
447 DA830_EPWM0A,
448 DA830_EPWMSYNCI,
449 DA830_AXR2_0,
450 DA830_EPWMSYNC0,
451 DA830_GPIO3_7,
452 DA830_GPIO3_8,
453 DA830_GPIO3_9,
454 DA830_GPIO3_10,
455 DA830_GPIO3_11,
456 DA830_GPIO3_14,
457 DA830_GPIO3_15,
458 DA830_GPIO4_10,
459 DA830_AHCLKR1,
460 DA830_ACLKR1,
461 DA830_AFSR1,
462 DA830_AMUTE1,
463 DA830_AXR1_0,
464 DA830_AXR1_1,
465 DA830_AXR1_2,
466 DA830_AXR1_3,
467 DA830_ECAP2_APWM2,
468 DA830_EHRPWMGLUETZ,
469 DA830_EQEP1A,
470 DA830_GPIO4_11,
471 DA830_GPIO4_12,
472 DA830_GPIO4_13,
473 DA830_GPIO4_14,
474 DA830_GPIO4_0,
475 DA830_GPIO4_1,
476 DA830_GPIO4_2,
477 DA830_GPIO4_3,
478 DA830_AXR1_4,
479 DA830_AXR1_5,
480 DA830_AXR1_6,
481 DA830_AXR1_7,
482 DA830_AXR1_8,
483 DA830_AXR1_9,
484 DA830_EMA_D_0,
485 DA830_EMA_D_1,
486 DA830_EQEP1B,
487 DA830_EPWM2B,
488 DA830_EPWM2A,
489 DA830_EPWM1B,
490 DA830_EPWM1A,
491 DA830_MMCSD_DAT_0,
492 DA830_MMCSD_DAT_1,
493 DA830_UHPI_HD_0,
494 DA830_UHPI_HD_1,
495 DA830_GPIO4_4,
496 DA830_GPIO4_5,
497 DA830_GPIO4_6,
498 DA830_GPIO4_7,
499 DA830_GPIO4_8,
500 DA830_GPIO4_9,
501 DA830_GPIO0_0,
502 DA830_GPIO0_1,
503 DA830_EMA_D_2,
504 DA830_EMA_D_3,
505 DA830_EMA_D_4,
506 DA830_EMA_D_5,
507 DA830_EMA_D_6,
508 DA830_EMA_D_7,
509 DA830_EMA_D_8,
510 DA830_EMA_D_9,
511 DA830_MMCSD_DAT_2,
512 DA830_MMCSD_DAT_3,
513 DA830_MMCSD_DAT_4,
514 DA830_MMCSD_DAT_5,
515 DA830_MMCSD_DAT_6,
516 DA830_MMCSD_DAT_7,
517 DA830_UHPI_HD_8,
518 DA830_UHPI_HD_9,
519 DA830_UHPI_HD_2,
520 DA830_UHPI_HD_3,
521 DA830_UHPI_HD_4,
522 DA830_UHPI_HD_5,
523 DA830_UHPI_HD_6,
524 DA830_UHPI_HD_7,
525 DA830_LCD_D_8,
526 DA830_LCD_D_9,
527 DA830_GPIO0_2,
528 DA830_GPIO0_3,
529 DA830_GPIO0_4,
530 DA830_GPIO0_5,
531 DA830_GPIO0_6,
532 DA830_GPIO0_7,
533 DA830_GPIO0_8,
534 DA830_GPIO0_9,
535 DA830_EMA_D_10,
536 DA830_EMA_D_11,
537 DA830_EMA_D_12,
538 DA830_EMA_D_13,
539 DA830_EMA_D_14,
540 DA830_EMA_D_15,
541 DA830_EMA_A_0,
542 DA830_EMA_A_1,
543 DA830_UHPI_HD_10,
544 DA830_UHPI_HD_11,
545 DA830_UHPI_HD_12,
546 DA830_UHPI_HD_13,
547 DA830_UHPI_HD_14,
548 DA830_UHPI_HD_15,
549 DA830_LCD_D_7,
550 DA830_MMCSD_CLK,
551 DA830_LCD_D_10,
552 DA830_LCD_D_11,
553 DA830_LCD_D_12,
554 DA830_LCD_D_13,
555 DA830_LCD_D_14,
556 DA830_LCD_D_15,
557 DA830_UHPI_HCNTL0,
558 DA830_GPIO0_10,
559 DA830_GPIO0_11,
560 DA830_GPIO0_12,
561 DA830_GPIO0_13,
562 DA830_GPIO0_14,
563 DA830_GPIO0_15,
564 DA830_GPIO1_0,
565 DA830_GPIO1_1,
566 DA830_EMA_A_2,
567 DA830_EMA_A_3,
568 DA830_EMA_A_4,
569 DA830_EMA_A_5,
570 DA830_EMA_A_6,
571 DA830_EMA_A_7,
572 DA830_EMA_A_8,
573 DA830_EMA_A_9,
574 DA830_MMCSD_CMD,
575 DA830_LCD_D_6,
576 DA830_LCD_D_3,
577 DA830_LCD_D_2,
578 DA830_LCD_D_1,
579 DA830_LCD_D_0,
580 DA830_LCD_PCLK,
581 DA830_LCD_HSYNC,
582 DA830_UHPI_HCNTL1,
583 DA830_GPIO1_2,
584 DA830_GPIO1_3,
585 DA830_GPIO1_4,
586 DA830_GPIO1_5,
587 DA830_GPIO1_6,
588 DA830_GPIO1_7,
589 DA830_GPIO1_8,
590 DA830_GPIO1_9,
591 DA830_EMA_A_10,
592 DA830_EMA_A_11,
593 DA830_EMA_A_12,
594 DA830_EMA_BA_1,
595 DA830_EMA_BA_0,
596 DA830_EMA_CLK,
597 DA830_EMA_SDCKE,
598 DA830_NEMA_CAS,
599 DA830_LCD_VSYNC,
600 DA830_NLCD_AC_ENB_CS,
601 DA830_LCD_MCLK,
602 DA830_LCD_D_5,
603 DA830_LCD_D_4,
604 DA830_OBSCLK,
605 DA830_NEMA_CS_4,
606 DA830_UHPI_HHWIL,
607 DA830_AHCLKR2,
608 DA830_GPIO1_10,
609 DA830_GPIO1_11,
610 DA830_GPIO1_12,
611 DA830_GPIO1_13,
612 DA830_GPIO1_14,
613 DA830_GPIO1_15,
614 DA830_GPIO2_0,
615 DA830_GPIO2_1,
616 DA830_NEMA_RAS,
617 DA830_NEMA_WE,
618 DA830_NEMA_CS_0,
619 DA830_NEMA_CS_2,
620 DA830_NEMA_CS_3,
621 DA830_NEMA_OE,
622 DA830_NEMA_WE_DQM_1,
623 DA830_NEMA_WE_DQM_0,
624 DA830_NEMA_CS_5,
625 DA830_UHPI_HRNW,
626 DA830_NUHPI_HAS,
627 DA830_NUHPI_HCS,
628 DA830_NUHPI_HDS1,
629 DA830_NUHPI_HDS2,
630 DA830_NUHPI_HINT,
631 DA830_AXR0_12,
632 DA830_AMUTE2,
633 DA830_AXR0_13,
634 DA830_AXR0_14,
635 DA830_AXR0_15,
636 DA830_GPIO2_2,
637 DA830_GPIO2_3,
638 DA830_GPIO2_4,
639 DA830_GPIO2_5,
640 DA830_GPIO2_6,
641 DA830_GPIO2_7,
642 DA830_GPIO2_8,
643 DA830_GPIO2_9,
644 DA830_EMA_WAIT_0,
645 DA830_NUHPI_HRDY,
646 DA830_GPIO2_10,
647};
648
245#ifdef CONFIG_DAVINCI_MUX 649#ifdef CONFIG_DAVINCI_MUX
246/* setup pin muxing */ 650/* setup pin muxing */
247extern int davinci_cfg_reg(unsigned long reg_cfg); 651extern int davinci_cfg_reg(unsigned long reg_cfg);
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 2bb414b14297..6b9621d88284 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -136,6 +136,47 @@
136#define DM646X_LPSC_TIMER1 35 136#define DM646X_LPSC_TIMER1 35
137#define DM646X_LPSC_ARM_INTC 45 137#define DM646X_LPSC_ARM_INTC 45
138 138
139/* PSC0 defines */
140#define DA8XX_LPSC0_TPCC 0
141#define DA8XX_LPSC0_TPTC0 1
142#define DA8XX_LPSC0_TPTC1 2
143#define DA8XX_LPSC0_EMIF25 3
144#define DA8XX_LPSC0_SPI0 4
145#define DA8XX_LPSC0_MMC_SD 5
146#define DA8XX_LPSC0_AINTC 6
147#define DA8XX_LPSC0_ARM_RAM_ROM 7
148#define DA8XX_LPSC0_SECU_MGR 8
149#define DA8XX_LPSC0_UART0 9
150#define DA8XX_LPSC0_SCR0_SS 10
151#define DA8XX_LPSC0_SCR1_SS 11
152#define DA8XX_LPSC0_SCR2_SS 12
153#define DA8XX_LPSC0_DMAX 13
154#define DA8XX_LPSC0_ARM 14
155#define DA8XX_LPSC0_GEM 15
156
157/* PSC1 defines */
158#define DA8XX_LPSC1_USB20 1
159#define DA8XX_LPSC1_USB11 2
160#define DA8XX_LPSC1_GPIO 3
161#define DA8XX_LPSC1_UHPI 4
162#define DA8XX_LPSC1_CPGMAC 5
163#define DA8XX_LPSC1_EMIF3C 6
164#define DA8XX_LPSC1_McASP0 7
165#define DA830_LPSC1_McASP1 8
166#define DA830_LPSC1_McASP2 9
167#define DA8XX_LPSC1_SPI1 10
168#define DA8XX_LPSC1_I2C 11
169#define DA8XX_LPSC1_UART1 12
170#define DA8XX_LPSC1_UART2 13
171#define DA8XX_LPSC1_LCDC 16
172#define DA8XX_LPSC1_PWM 17
173#define DA8XX_LPSC1_ECAP 20
174#define DA830_LPSC1_EQEP 21
175#define DA8XX_LPSC1_SCR_P0_SS 24
176#define DA8XX_LPSC1_SCR_P1_SS 25
177#define DA8XX_LPSC1_CR_P3_SS 26
178#define DA8XX_LPSC1_L3_CBA_RAM 31
179
139extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); 180extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
140extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, 181extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
141 unsigned int id, char enable); 182 unsigned int id, char enable);
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 794fa5cf93c1..57e68e610ee9 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -18,6 +18,10 @@
18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 18#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 19#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
20 20
21#define DA8XX_UART0_BASE (IO_PHYS + 0x042000)
22#define DA8XX_UART1_BASE (IO_PHYS + 0x10c000)
23#define DA8XX_UART2_BASE (IO_PHYS + 0x10d000)
24
21/* DaVinci UART register offsets */ 25/* DaVinci UART register offsets */
22#define UART_DAVINCI_PWREMU 0x0c 26#define UART_DAVINCI_PWREMU 0x0c
23#define UART_DM646X_SCR 0x10 27#define UART_DM646X_SCR 0x10
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 13:06:51 -0500