diff options
Diffstat (limited to 'arch/arm/mach-davinci/include/mach/mux.h')
-rw-r--r-- | arch/arm/mach-davinci/include/mach/mux.h | 220 |
1 files changed, 174 insertions, 46 deletions
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h index c24b6782804d..bae22cb3e27b 100644 --- a/arch/arm/mach-davinci/include/mach/mux.h +++ b/arch/arm/mach-davinci/include/mach/mux.h | |||
@@ -1,55 +1,183 @@ | |||
1 | /* | 1 | /* |
2 | * DaVinci pin multiplexing defines | 2 | * Table of the DAVINCI register configurations for the PINMUX combinations |
3 | * | 3 | * |
4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> | 4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> |
5 | * | 5 | * |
6 | * Based on linux/include/asm-arm/arch-omap/mux.h: | ||
7 | * Copyright (C) 2003 - 2005 Nokia Corporation | ||
8 | * | ||
9 | * Written by Tony Lindgren | ||
10 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | 11 | * 2007 (c) MontaVista Software, Inc. This file is licensed under |
7 | * the terms of the GNU General Public License version 2. This program | 12 | * the terms of the GNU General Public License version 2. This program |
8 | * is licensed "as is" without any warranty of any kind, whether express | 13 | * is licensed "as is" without any warranty of any kind, whether express |
9 | * or implied. | 14 | * or implied. |
15 | * | ||
16 | * Copyright (C) 2008 Texas Instruments. | ||
10 | */ | 17 | */ |
11 | #ifndef __ASM_ARCH_MUX_H | 18 | |
12 | #define __ASM_ARCH_MUX_H | 19 | #ifndef __INC_MACH_MUX_H |
13 | 20 | #define __INC_MACH_MUX_H | |
14 | #define DAVINCI_MUX_AEAW0 0 | 21 | |
15 | #define DAVINCI_MUX_AEAW1 1 | 22 | /* System module registers */ |
16 | #define DAVINCI_MUX_AEAW2 2 | 23 | #define PINMUX0 0x00 |
17 | #define DAVINCI_MUX_AEAW3 3 | 24 | #define PINMUX1 0x04 |
18 | #define DAVINCI_MUX_AEAW4 4 | 25 | /* dm355 only */ |
19 | #define DAVINCI_MUX_AECS4 10 | 26 | #define PINMUX2 0x08 |
20 | #define DAVINCI_MUX_AECS5 11 | 27 | #define PINMUX3 0x0c |
21 | #define DAVINCI_MUX_VLYNQWD0 12 | 28 | #define PINMUX4 0x10 |
22 | #define DAVINCI_MUX_VLYNQWD1 13 | 29 | #define INTMUX 0x18 |
23 | #define DAVINCI_MUX_VLSCREN 14 | 30 | #define EVTMUX 0x1c |
24 | #define DAVINCI_MUX_VLYNQEN 15 | 31 | |
25 | #define DAVINCI_MUX_HDIREN 16 | 32 | struct mux_config { |
26 | #define DAVINCI_MUX_ATAEN 17 | 33 | const char *name; |
27 | #define DAVINCI_MUX_RGB666 22 | 34 | const char *mux_reg_name; |
28 | #define DAVINCI_MUX_RGB888 23 | 35 | const unsigned char mux_reg; |
29 | #define DAVINCI_MUX_LOEEN 24 | 36 | const unsigned char mask_offset; |
30 | #define DAVINCI_MUX_LFLDEN 25 | 37 | const unsigned char mask; |
31 | #define DAVINCI_MUX_CWEN 26 | 38 | const unsigned char mode; |
32 | #define DAVINCI_MUX_CFLDEN 27 | 39 | bool debug; |
33 | #define DAVINCI_MUX_HPIEN 29 | 40 | }; |
34 | #define DAVINCI_MUX_1394EN 30 | 41 | |
35 | #define DAVINCI_MUX_EMACEN 31 | 42 | enum davinci_dm644x_index { |
36 | 43 | /* ATA and HDDIR functions */ | |
37 | #define DAVINCI_MUX_LEVEL2 32 | 44 | DM644X_HDIREN, |
38 | #define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) | 45 | DM644X_ATAEN, |
39 | #define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) | 46 | DM644X_ATAEN_DISABLE, |
40 | #define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) | 47 | |
41 | #define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) | 48 | /* HPI functions */ |
42 | #define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) | 49 | DM644X_HPIEN_DISABLE, |
43 | #define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) | 50 | |
44 | #define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) | 51 | /* AEAW functions */ |
45 | #define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) | 52 | DM644X_AEAW, |
46 | #define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) | 53 | |
47 | #define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) | 54 | /* Memory Stick */ |
48 | #define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) | 55 | DM644X_MSTK, |
49 | #define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) | 56 | |
50 | #define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) | 57 | /* I2C */ |
51 | #define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) | 58 | DM644X_I2C, |
52 | 59 | ||
53 | extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); | 60 | /* ASP function */ |
54 | 61 | DM644X_MCBSP, | |
55 | #endif /* __ASM_ARCH_MUX_H */ | 62 | |
63 | /* UART1 */ | ||
64 | DM644X_UART1, | ||
65 | |||
66 | /* UART2 */ | ||
67 | DM644X_UART2, | ||
68 | |||
69 | /* PWM0 */ | ||
70 | DM644X_PWM0, | ||
71 | |||
72 | /* PWM1 */ | ||
73 | DM644X_PWM1, | ||
74 | |||
75 | /* PWM2 */ | ||
76 | DM644X_PWM2, | ||
77 | |||
78 | /* VLYNQ function */ | ||
79 | DM644X_VLYNQEN, | ||
80 | DM644X_VLSCREN, | ||
81 | DM644X_VLYNQWD, | ||
82 | |||
83 | /* EMAC and MDIO function */ | ||
84 | DM644X_EMACEN, | ||
85 | |||
86 | /* GPIO3V[0:16] pins */ | ||
87 | DM644X_GPIO3V, | ||
88 | |||
89 | /* GPIO pins */ | ||
90 | DM644X_GPIO0, | ||
91 | DM644X_GPIO3, | ||
92 | DM644X_GPIO43_44, | ||
93 | DM644X_GPIO46_47, | ||
94 | |||
95 | /* VPBE */ | ||
96 | DM644X_RGB666, | ||
97 | |||
98 | /* LCD */ | ||
99 | DM644X_LOEEN, | ||
100 | DM644X_LFLDEN, | ||
101 | }; | ||
102 | |||
103 | enum davinci_dm646x_index { | ||
104 | /* ATA function */ | ||
105 | DM646X_ATAEN, | ||
106 | |||
107 | /* AUDIO Clock */ | ||
108 | DM646X_AUDCK1, | ||
109 | DM646X_AUDCK0, | ||
110 | |||
111 | /* CRGEN Control */ | ||
112 | DM646X_CRGMUX, | ||
113 | |||
114 | /* VPIF Control */ | ||
115 | DM646X_STSOMUX_DISABLE, | ||
116 | DM646X_STSIMUX_DISABLE, | ||
117 | DM646X_PTSOMUX_DISABLE, | ||
118 | DM646X_PTSIMUX_DISABLE, | ||
119 | |||
120 | /* TSIF Control */ | ||
121 | DM646X_STSOMUX, | ||
122 | DM646X_STSIMUX, | ||
123 | DM646X_PTSOMUX_PARALLEL, | ||
124 | DM646X_PTSIMUX_PARALLEL, | ||
125 | DM646X_PTSOMUX_SERIAL, | ||
126 | DM646X_PTSIMUX_SERIAL, | ||
127 | }; | ||
128 | |||
129 | enum davinci_dm355_index { | ||
130 | /* MMC/SD 0 */ | ||
131 | DM355_MMCSD0, | ||
132 | |||
133 | /* MMC/SD 1 */ | ||
134 | DM355_SD1_CLK, | ||
135 | DM355_SD1_CMD, | ||
136 | DM355_SD1_DATA3, | ||
137 | DM355_SD1_DATA2, | ||
138 | DM355_SD1_DATA1, | ||
139 | DM355_SD1_DATA0, | ||
140 | |||
141 | /* I2C */ | ||
142 | DM355_I2C_SDA, | ||
143 | DM355_I2C_SCL, | ||
144 | |||
145 | /* ASP0 function */ | ||
146 | DM355_MCBSP0_BDX, | ||
147 | DM355_MCBSP0_X, | ||
148 | DM355_MCBSP0_BFSX, | ||
149 | DM355_MCBSP0_BDR, | ||
150 | DM355_MCBSP0_R, | ||
151 | DM355_MCBSP0_BFSR, | ||
152 | |||
153 | /* SPI0 */ | ||
154 | DM355_SPI0_SDI, | ||
155 | DM355_SPI0_SDENA0, | ||
156 | DM355_SPI0_SDENA1, | ||
157 | |||
158 | /* IRQ muxing */ | ||
159 | DM355_INT_EDMA_CC, | ||
160 | DM355_INT_EDMA_TC0_ERR, | ||
161 | DM355_INT_EDMA_TC1_ERR, | ||
162 | |||
163 | /* EDMA event muxing */ | ||
164 | DM355_EVT8_ASP1_TX, | ||
165 | DM355_EVT9_ASP1_RX, | ||
166 | DM355_EVT26_MMC0_RX, | ||
167 | }; | ||
168 | |||
169 | #ifdef CONFIG_DAVINCI_MUX | ||
170 | /* setup pin muxing */ | ||
171 | extern void davinci_mux_init(void); | ||
172 | extern int davinci_mux_register(const struct mux_config *pins, | ||
173 | unsigned long size); | ||
174 | extern int davinci_cfg_reg(unsigned long reg_cfg); | ||
175 | #else | ||
176 | /* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */ | ||
177 | static inline void davinci_mux_init(void) {} | ||
178 | static inline int davinci_mux_register(const struct mux_config *pins, | ||
179 | unsigned long size) { return 0; } | ||
180 | static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } | ||
181 | #endif | ||
182 | |||
183 | #endif /* __INC_MACH_MUX_H */ | ||