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Diffstat (limited to 'arch/arm/mach-davinci/include/mach/gpio.h')
-rw-r--r--arch/arm/mach-davinci/include/mach/gpio.h79
1 files changed, 2 insertions, 77 deletions
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index fbece126c2bf..fbaae4772b91 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -13,80 +13,10 @@
13#ifndef __DAVINCI_GPIO_H 13#ifndef __DAVINCI_GPIO_H
14#define __DAVINCI_GPIO_H 14#define __DAVINCI_GPIO_H
15 15
16#include <linux/io.h>
17#include <linux/spinlock.h>
18
19#include <asm-generic/gpio.h> 16#include <asm-generic/gpio.h>
20 17
21#include <mach/irqs.h> 18/* The inline versions use the static inlines in the driver header */
22#include <mach/common.h> 19#include "gpio-davinci.h"
23
24#define DAVINCI_GPIO_BASE 0x01C67000
25
26enum davinci_gpio_type {
27 GPIO_TYPE_DAVINCI = 0,
28 GPIO_TYPE_TNETV107X,
29};
30
31/*
32 * basic gpio routines
33 *
34 * board-specific init should be done by arch/.../.../board-XXX.c (maybe
35 * initializing banks together) rather than boot loaders; kexec() won't
36 * go through boot loaders.
37 *
38 * the gpio clock will be turned on when gpios are used, and you may also
39 * need to pay attention to PINMUX registers to be sure those pins are
40 * used as gpios, not with other peripherals.
41 *
42 * On-chip GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation,
43 * and maybe for later updates, code may write GPIO(N). These may be
44 * all 1.8V signals, all 3.3V ones, or a mix of the two. A given chip
45 * may not support all the GPIOs in that range.
46 *
47 * GPIOs can also be on external chips, numbered after the ones built-in
48 * to the DaVinci chip. For now, they won't be usable as IRQ sources.
49 */
50#define GPIO(X) (X) /* 0 <= X <= (DAVINCI_N_GPIO - 1) */
51
52/* Convert GPIO signal to GPIO pin number */
53#define GPIO_TO_PIN(bank, gpio) (16 * (bank) + (gpio))
54
55struct davinci_gpio_controller {
56 struct gpio_chip chip;
57 int irq_base;
58 spinlock_t lock;
59 void __iomem *regs;
60 void __iomem *set_data;
61 void __iomem *clr_data;
62 void __iomem *in_data;
63};
64
65/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
66 * with constant parameters; or in outlined code they execute at runtime.
67 *
68 * You'd access the controller directly when reading or writing more than
69 * one gpio value at a time, and to support wired logic where the value
70 * being driven by the cpu need not match the value read back.
71 *
72 * These are NOT part of the cross-platform GPIO interface
73 */
74static inline struct davinci_gpio_controller *
75__gpio_to_controller(unsigned gpio)
76{
77 struct davinci_gpio_controller *ctlrs = davinci_soc_info.gpio_ctlrs;
78 int index = gpio / 32;
79
80 if (!ctlrs || index >= davinci_soc_info.gpio_ctlrs_num)
81 return NULL;
82
83 return ctlrs + index;
84}
85
86static inline u32 __gpio_mask(unsigned gpio)
87{
88 return 1 << (gpio % 32);
89}
90 20
91/* 21/*
92 * The get/set/clear functions will inline when called with constant 22 * The get/set/clear functions will inline when called with constant
@@ -147,11 +77,6 @@ static inline int gpio_cansleep(unsigned gpio)
147 return __gpio_cansleep(gpio); 77 return __gpio_cansleep(gpio);
148} 78}
149 79
150static inline int gpio_to_irq(unsigned gpio)
151{
152 return __gpio_to_irq(gpio);
153}
154
155static inline int irq_to_gpio(unsigned irq) 80static inline int irq_to_gpio(unsigned irq)
156{ 81{
157 /* don't support the reverse mapping */ 82 /* don't support the reverse mapping */