1 files changed, 43 insertions, 0 deletions

diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index da30078a80c1..941a308e1253 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -16,6 +16,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
 #include <mach/cns3xxx.h>
 #include "core.h"
 
@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(void)
 struct sys_timer cns3xxx_timer = {
         .init = cns3xxx_timer_init,
 };
+
+#ifdef CONFIG_CACHE_L2X0
+
+void __init cns3xxx_l2x0_init(void)
+{
+        void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
+        u32 val;
+
+        if (WARN_ON(!base))
+                return;
+
+        /*
+         * Tag RAM Control register
+         *
+         * bit[10:8]    - 1 cycle of write accesses latency
+         * bit[6:4]     - 1 cycle of read accesses latency
+         * bit[3:0]     - 1 cycle of setup latency
+         *
+         * 1 cycle of latency for setup, read and write accesses
+         */
+        val = readl(base + L2X0_TAG_LATENCY_CTRL);
+        val &= 0xfffff888;
+        writel(val, base + L2X0_TAG_LATENCY_CTRL);
+
+        /*
+         * Data RAM Control register
+         *
+         * bit[10:8]    - 1 cycles of write accesses latency
+         * bit[6:4]     - 1 cycles of read accesses latency
+         * bit[3:0]     - 1 cycle of setup latency
+         *
+         * 1 cycle of latency for setup, read and write accesses
+         */
+        val = readl(base + L2X0_DATA_LATENCY_CTRL);
+        val &= 0xfffff888;
+        writel(val, base + L2X0_DATA_LATENCY_CTRL);
+
+        /* 32 KiB, 8-way, parity disable */
+        l2x0_init(base, 0x00540000, 0xfe000fff);
+}
+
+#endif /* CONFIG_CACHE_L2X0 */