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-rw-r--r--arch/arm/mach-bcmring/include/csp/dmacHw.h596
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h145
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h406
3 files changed, 1147 insertions, 0 deletions
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
new file mode 100644
index 000000000000..5d510130a25f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -0,0 +1,596 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw.h
18*
19* @brief API definitions for low level DMA controller driver
20*
21*/
22/****************************************************************************/
23#ifndef _DMACHW_H
24#define _DMACHW_H
25
26#include <stddef.h>
27
28#include <csp/stdint.h>
29#include <mach/csp/dmacHw_reg.h>
30
31/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
32
33 System specific channel ID should be defined as follows
34
35 For example:
36
37 #include <dmacHw.h>
38 ...
39 #define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5)
40 #define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0)
41 #define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1)
42 #define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3)
43 #define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4)
44 ...
45 #define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4)
46 #define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5)
47 #define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6)
48 ...
49*/
50#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c)
51
52typedef enum {
53 dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */
54 dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */
55 dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */
56 dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */
57 dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */
58 dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */
59 dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */
60 dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */
61} dmacHw_CHANNEL_PRIORITY_e;
62
63/* Source destination master interface */
64typedef enum {
65 dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */
66 dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */
67 dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */
68 dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */
69} dmacHw_MASTER_INTERFACE_e;
70
71typedef enum {
72 dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */
73 dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */
74 dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */
75 dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */
76 dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */
77 dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */
78 dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */
79 dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */
80} dmacHw_TRANSACTION_WIDTH_e;
81
82typedef enum {
83 dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */
84 dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
85 dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
86 dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
87 dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */
88 dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
89 dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
90 dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
91} dmacHw_BURST_WIDTH_e;
92
93typedef enum {
94 dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */
95 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */
96 dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */
97 dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */
98} dmacHw_TRANSFER_TYPE_e;
99
100typedef enum {
101 dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */
102 dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */
103 dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */
104} dmacHw_TRANSFER_MODE_e;
105
106typedef enum {
107 dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */
108 dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */
109 dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */
110 dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */
111 dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */
112 dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */
113} dmacHw_ADDRESS_UPDATE_MODE_e;
114
115typedef enum {
116 dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */
117 dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */
118} dmacHw_FLOW_CONTROL_e;
119
120typedef enum {
121 dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */
122 dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */
123 dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */
124} dmacHw_TRANSFER_STATUS_e;
125
126typedef enum {
127 dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */
128 dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
129} dmacHw_INTERRUPT_e;
130
131typedef enum {
132 dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */
133 dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */
134 dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */
135 dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */
136} dmacHw_INTERRUPT_STATUS_e;
137
138typedef enum {
139 dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */
140 dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */
141 dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */
142 dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */
143 dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */
144} dmacHw_CONTROLLER_ATTRIB_e;
145
146typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */
147typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using
148 "dmacHw_MAKE_CHANNEL_ID" macro
149 */
150/* DMA channel configuration parameters */
151typedef struct {
152 uint32_t srcPeripheralPort; /* Source peripheral port */
153 uint32_t dstPeripheralPort; /* Destination peripheral port */
154 uint32_t srcStatusRegisterAddress; /* Source status register address */
155 uint32_t dstStatusRegisterAddress; /* Destination status register address of type */
156
157 uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */
158 uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
159 uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */
160 uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */
161 uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor.
162 0 = Maximum possible.
163 */
164
165 dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
166 dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
167 dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */
168 dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */
169 dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */
170 dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */
171 dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */
172 dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */
173 dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */
174 dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */
175 dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */
176 dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */
177 dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */
178 dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */
179 dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */
180} dmacHw_CONFIG_t;
181
182/****************************************************************************/
183/**
184* @brief Initializes DMA
185*
186* This function initializes DMA CSP driver
187*
188* @note
189* Must be called before using any DMA channel
190*/
191/****************************************************************************/
192void dmacHw_initDma(void);
193
194/****************************************************************************/
195/**
196* @brief Exit function for DMA
197*
198* This function isolates DMA from the system
199*
200*/
201/****************************************************************************/
202void dmacHw_exitDma(void);
203
204/****************************************************************************/
205/**
206* @brief Gets a handle to a DMA channel
207*
208* This function returns a handle, representing a control block of a particular DMA channel
209*
210* @return -1 - On Failure
211* handle - On Success, representing a channel control block
212*
213* @note
214* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
215*/
216/****************************************************************************/
217dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
218 );
219
220/****************************************************************************/
221/**
222* @brief Initializes a DMA channel for use
223*
224* This function initializes and resets a DMA channel for use
225*
226* @return -1 - On Failure
227* 0 - On Success
228*
229* @note
230* None
231*/
232/****************************************************************************/
233int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
234 );
235
236/****************************************************************************/
237/**
238* @brief Estimates number of descriptor needed to perform certain DMA transfer
239*
240*
241* @return On failure : -1
242* On success : Number of descriptor count
243*
244*
245*/
246/****************************************************************************/
247int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
248 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
249 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
250 size_t dataLen /* [ IN ] Data length in bytes */
251 );
252
253/****************************************************************************/
254/**
255* @brief Initializes descriptor ring
256*
257* This function will initializes the descriptor ring of a DMA channel
258*
259*
260* @return -1 - On failure
261* 0 - On success
262* @note
263* - "len" parameter should be obtained from "dmacHw_descriptorLen"
264* - Descriptor buffer MUST be 32 bit aligned and uncached as it
265* is accessed by ARM and DMA
266*/
267/****************************************************************************/
268int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
269 uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
270 uint32_t len, /* [ IN ] Size of the pBuf */
271 uint32_t num /* [ IN ] Number of descriptor in the ring */
272 );
273
274/****************************************************************************/
275/**
276* @brief Finds amount of memory required to form a descriptor ring
277*
278*
279* @return Number of bytes required to form a descriptor ring
280*
281*
282* @note
283* None
284*/
285/****************************************************************************/
286uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
287 );
288
289/****************************************************************************/
290/**
291* @brief Configure DMA channel
292*
293* @return 0 : On success
294* -1 : On failure
295*/
296/****************************************************************************/
297int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
298 dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
299 );
300
301/****************************************************************************/
302/**
303* @brief Set descriptors for known data length
304*
305* When DMA has to work as a flow controller, this function prepares the
306* descriptor chain to transfer data
307*
308* from:
309* - Memory to memory
310* - Peripheral to memory
311* - Memory to Peripheral
312* - Peripheral to Peripheral
313*
314* @return -1 - On failure
315* 0 - On success
316*
317*/
318/****************************************************************************/
319int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
320 void *pDescriptor, /* [ IN ] Descriptor buffer */
321 void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
322 void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
323 size_t dataLen /* [ IN ] Length in bytes */
324 );
325
326/****************************************************************************/
327/**
328* @brief Indicates whether DMA transfer is in progress or completed
329*
330* @return DMA transfer status
331* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
332* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
333* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
334*
335*/
336/****************************************************************************/
337dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
338 );
339
340/****************************************************************************/
341/**
342* @brief Set descriptor carrying control information
343*
344* This function will be used to send specific control information to the device
345* using the DMA channel
346*
347*
348* @return -1 - On failure
349* 0 - On success
350*
351* @note
352* None
353*/
354/****************************************************************************/
355int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
356 void *pDescriptor, /* [ IN ] Descriptor buffer */
357 uint32_t ctlAddress, /* [ IN ] Address of the device control register */
358 uint32_t control /* [ IN ] Device control information */
359 );
360
361/****************************************************************************/
362/**
363* @brief Read data DMA transferred to memory
364*
365* This function will read data that has been DMAed to memory while transfering from:
366* - Memory to memory
367* - Peripheral to memory
368*
369* @return 0 - No more data is available to read
370* 1 - More data might be available to read
371*
372*/
373/****************************************************************************/
374int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
375 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
376 void *pDescriptor, /* [ IN ] Descriptor buffer */
377 void **ppBbuf, /* [ OUT ] Data received */
378 size_t *pLlen /* [ OUT ] Length of the data received */
379 );
380
381/****************************************************************************/
382/**
383* @brief Prepares descriptor ring, when source peripheral working as a flow controller
384*
385* This function will form the descriptor ring by allocating buffers, when source peripheral
386* has to work as a flow controller to transfer data from:
387* - Peripheral to memory.
388*
389* @return -1 - On failure
390* 0 - On success
391*
392*
393* @note
394* None
395*/
396/****************************************************************************/
397int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
398 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
399 void *pDescriptor, /* [ IN ] Descriptor buffer */
400 uint32_t srcAddr, /* [ IN ] Source peripheral address */
401 void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */
402 int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */
403 int num /* [ IN ] Number of descriptor to set */
404 );
405
406/****************************************************************************/
407/**
408* @brief Program channel register to initiate transfer
409*
410* @return void
411*
412*
413* @note
414* - Descriptor buffer MUST ALWAYS be flushed before calling this function
415* - This function should also be called from ISR to program the channel with
416* pending descriptors
417*/
418/****************************************************************************/
419void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
420 dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
421 void *pDescriptor /* [ IN ] Descriptor buffer */
422 );
423
424/****************************************************************************/
425/**
426* @brief Resets descriptor control information
427*
428* @return void
429*/
430/****************************************************************************/
431void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */
432 );
433
434/****************************************************************************/
435/**
436* @brief Program channel register to stop transfer
437*
438* Ensures the channel is not doing any transfer after calling this function
439*
440* @return void
441*
442*/
443/****************************************************************************/
444void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
445 );
446
447/****************************************************************************/
448/**
449* @brief Check the existance of pending descriptor
450*
451* This function confirmes if there is any pending descriptor in the chain
452* to program the channel
453*
454* @return 1 : Channel need to be programmed with pending descriptor
455* 0 : No more pending descriptor to programe the channel
456*
457* @note
458* - This function should be called from ISR in case there are pending
459* descriptor to program the channel.
460*
461* Example:
462*
463* dmac_isr ()
464* {
465* ...
466* if (dmacHw_descriptorPending (handle))
467* {
468* dmacHw_initiateTransfer (handle);
469* }
470* }
471*
472*/
473/****************************************************************************/
474uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
475 void *pDescriptor /* [ IN ] Descriptor buffer */
476 );
477
478/****************************************************************************/
479/**
480* @brief Deallocates source or destination memory, allocated
481*
482* This function can be called to deallocate data memory that was DMAed successfully
483*
484* @return -1 - On failure
485* 0 - On success
486*
487* @note
488* This function will be called ONLY, when source OR destination address is pointing
489* to dynamic memory
490*/
491/****************************************************************************/
492int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
493 void *pDescriptor, /* [ IN ] Descriptor buffer */
494 void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */
495 );
496
497/****************************************************************************/
498/**
499* @brief Clears the interrupt
500*
501* This function clears the DMA channel specific interrupt
502*
503* @return N/A
504*
505* @note
506* Must be called under the context of ISR
507*/
508/****************************************************************************/
509void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
510 );
511
512/****************************************************************************/
513/**
514* @brief Returns the cause of channel specific DMA interrupt
515*
516* This function returns the cause of interrupt
517*
518* @return Interrupt status, each bit representing a specific type of interrupt
519* of type dmacHw_INTERRUPT_STATUS_e
520* @note
521* This function should be called under the context of ISR
522*/
523/****************************************************************************/
524dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
525 );
526
527/****************************************************************************/
528/**
529* @brief Indentifies a DMA channel causing interrupt
530*
531* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
532*
533* @return NULL : No channel causing DMA interrupt
534* ! NULL : Handle to a channel causing DMA interrupt
535* @note
536* dmacHw_clearInterrupt() must be called with a valid handle after calling this function
537*/
538/****************************************************************************/
539dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
540
541/****************************************************************************/
542/**
543* @brief Sets channel specific user data
544*
545* This function associates user data to a specif DMA channel
546*
547*/
548/****************************************************************************/
549void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
550 void *userData /* [ IN ] User data */
551 );
552
553/****************************************************************************/
554/**
555* @brief Gets channel specific user data
556*
557* This function returns user data specific to a DMA channel
558*
559* @return user data
560*/
561/****************************************************************************/
562void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
563 );
564
565/****************************************************************************/
566/**
567* @brief Displays channel specific registers and other control parameters
568*
569*
570* @return void
571*
572* @note
573* None
574*/
575/****************************************************************************/
576void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
577 void *pDescriptor, /* [ IN ] Descriptor buffer */
578 int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
579 );
580
581/****************************************************************************/
582/**
583* @brief Provides DMA controller attributes
584*
585*
586* @return DMA controller attributes
587*
588* @note
589* None
590*/
591/****************************************************************************/
592uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
593 dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
594 );
595
596#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
new file mode 100644
index 000000000000..375066ad0186
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
@@ -0,0 +1,145 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_priv.h
18*
19* @brief Private Definitions for low level DMA driver
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_PRIV_H
25#define _DMACHW_PRIV_H
26
27#include <csp/stdint.h>
28
29/* Data type for DMA Link List Item */
30typedef struct {
31 uint32_t sar; /* Source Adress Register.
32 Address must be aligned to CTLx.SRC_TR_WIDTH. */
33 uint32_t dar; /* Destination Address Register.
34 Address must be aligned to CTLx.DST_TR_WIDTH. */
35 uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
36 Address MUST be aligned to a 32-bit boundary. */
37 dmacHw_REG64_t ctl; /* Control Register. 64 bits */
38 uint32_t sstat; /* Source Status Register */
39 uint32_t dstat; /* Destination Status Register */
40 uint32_t devCtl; /* Device specific control information */
41 uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
42} dmacHw_DESC_t;
43
44/*
45 * Descriptor ring pointers
46 */
47typedef struct {
48 int num; /* Number of link items */
49 dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
50 dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
51 dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
52 dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
53 dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
54 uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
55} dmacHw_DESC_RING_t;
56
57/*
58 * DMA channel control block
59 */
60typedef struct {
61 uint32_t module; /* DMA controller module (0-1) */
62 uint32_t channel; /* DMA channel (0-7) */
63 volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
64 volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
65 void *userData; /* Channel specifc user data */
66} dmacHw_CBLK_t;
67
68#define dmacHw_ASSERT(a) if (!(a)) while (1)
69#define dmacHw_MAX_CHANNEL_COUNT 16
70#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
71#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
72#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
73#define dmacHw_MAX_BLOCKSIZE 4064
74#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
75#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
76#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
77#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
78#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
79#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
80
81/****************************************************************************/
82/**
83* @brief Get next available transaction width
84*
85*
86* @return On sucess : Next avail able transaction width
87* On failure : dmacHw_TRANSACTION_WIDTH_8
88*
89* @note
90* None
91*/
92/****************************************************************************/
93static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
94 ) {
95 if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
96 return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
97 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
98 } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
99 return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
100 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
101 }
102
103 /* Default return */
104 return dmacHw_SRC_TRANSACTION_WIDTH_8;
105}
106
107/****************************************************************************/
108/**
109* @brief Get number of bytes per transaction
110*
111* @return Number of bytes per transaction
112*
113*
114* @note
115* None
116*/
117/****************************************************************************/
118static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
119 ) {
120 int width = 1;
121 switch (tw) {
122 case dmacHw_SRC_TRANSACTION_WIDTH_8:
123 width = 1;
124 break;
125 case dmacHw_SRC_TRANSACTION_WIDTH_16:
126 case dmacHw_DST_TRANSACTION_WIDTH_16:
127 width = 2;
128 break;
129 case dmacHw_SRC_TRANSACTION_WIDTH_32:
130 case dmacHw_DST_TRANSACTION_WIDTH_32:
131 width = 4;
132 break;
133 case dmacHw_SRC_TRANSACTION_WIDTH_64:
134 case dmacHw_DST_TRANSACTION_WIDTH_64:
135 width = 8;
136 break;
137 default:
138 dmacHw_ASSERT(0);
139 }
140
141 /* Default transaction width */
142 return width;
143}
144
145#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
new file mode 100644
index 000000000000..891cea87e333
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -0,0 +1,406 @@
1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_reg.h
18*
19* @brief Definitions for low level DMA registers
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_REG_H
25#define _DMACHW_REG_H
26
27#include <csp/stdint.h>
28#include <mach/csp/mm_io.h>
29
30/* Data type for 64 bit little endian register */
31typedef struct {
32 volatile uint32_t lo; /* Lower 32 bit in little endian mode */
33 volatile uint32_t hi; /* Upper 32 bit in little endian mode */
34} dmacHw_REG64_t;
35
36/* Data type representing DMA channel registers */
37typedef struct {
38 dmacHw_REG64_t ChannelSar; /* Source Adress Register. 64 bits (upper 32 bits are reserved)
39 Address must be aligned to CTLx.SRC_TR_WIDTH.
40 */
41 dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved)
42 Address must be aligned to CTLx.DST_TR_WIDTH.
43 */
44 dmacHw_REG64_t ChannelLlp; /* Link List Pointer.64 bits (upper 32 bits are reserved)
45 LLP contains the pointer to the next LLI for block chaining using linked lists.
46 If LLPis set to 0x0, then transfers using linked lists are not enabled.
47 Address MUST be aligned to a 32-bit boundary.
48 */
49 dmacHw_REG64_t ChannelCtl; /* Control Register. 64 bits */
50 dmacHw_REG64_t ChannelSstat; /* Source Status Register */
51 dmacHw_REG64_t ChannelDstat; /* Destination Status Register */
52 dmacHw_REG64_t ChannelSstatAddr; /* Source Status Address Register */
53 dmacHw_REG64_t ChannelDstatAddr; /* Destination Status Address Register */
54 dmacHw_REG64_t ChannelConfig; /* Channel Configuration Register */
55 dmacHw_REG64_t SrcGather; /* Source gather register */
56 dmacHw_REG64_t DstScatter; /* Destination scatter register */
57} dmacHw_CH_REG_t;
58
59/* Data type for RAW interrupt status registers */
60typedef struct {
61 dmacHw_REG64_t RawTfr; /* Raw Status for IntTfr Interrupt */
62 dmacHw_REG64_t RawBlock; /* Raw Status for IntBlock Interrupt */
63 dmacHw_REG64_t RawSrcTran; /* Raw Status for IntSrcTran Interrupt */
64 dmacHw_REG64_t RawDstTran; /* Raw Status for IntDstTran Interrupt */
65 dmacHw_REG64_t RawErr; /* Raw Status for IntErr Interrupt */
66} dmacHw_INT_RAW_t;
67
68/* Data type for interrupt status registers */
69typedef struct {
70 dmacHw_REG64_t StatusTfr; /* Status for IntTfr Interrupt */
71 dmacHw_REG64_t StatusBlock; /* Status for IntBlock Interrupt */
72 dmacHw_REG64_t StatusSrcTran; /* Status for IntSrcTran Interrupt */
73 dmacHw_REG64_t StatusDstTran; /* Status for IntDstTran Interrupt */
74 dmacHw_REG64_t StatusErr; /* Status for IntErr Interrupt */
75} dmacHw_INT_STATUS_t;
76
77/* Data type for interrupt mask registers*/
78typedef struct {
79 dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
80 dmacHw_REG64_t MaskBlock; /* Mask for IntBlock Interrupt */
81 dmacHw_REG64_t MaskSrcTran; /* Mask for IntSrcTran Interrupt */
82 dmacHw_REG64_t MaskDstTran; /* Mask for IntDstTran Interrupt */
83 dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
84} dmacHw_INT_MASK_t;
85
86/* Data type for interrupt clear registers */
87typedef struct {
88 dmacHw_REG64_t ClearTfr; /* Clear for IntTfr Interrupt */
89 dmacHw_REG64_t ClearBlock; /* Clear for IntBlock Interrupt */
90 dmacHw_REG64_t ClearSrcTran; /* Clear for IntSrcTran Interrupt */
91 dmacHw_REG64_t ClearDstTran; /* Clear for IntDstTran Interrupt */
92 dmacHw_REG64_t ClearErr; /* Clear for IntErr Interrupt */
93 dmacHw_REG64_t StatusInt; /* Status for each interrupt type */
94} dmacHw_INT_CLEAR_t;
95
96/* Data type for software handshaking registers */
97typedef struct {
98 dmacHw_REG64_t ReqSrcReg; /* Source Software Transaction Request Register */
99 dmacHw_REG64_t ReqDstReg; /* Destination Software Transaction Request Register */
100 dmacHw_REG64_t SglReqSrcReg; /* Single Source Transaction Request Register */
101 dmacHw_REG64_t SglReqDstReg; /* Single Destination Transaction Request Register */
102 dmacHw_REG64_t LstSrcReg; /* Last Source Transaction Request Register */
103 dmacHw_REG64_t LstDstReg; /* Last Destination Transaction Request Register */
104} dmacHw_SW_HANDSHAKE_t;
105
106/* Data type for misc. registers */
107typedef struct {
108 dmacHw_REG64_t DmaCfgReg; /* DMA Configuration Register */
109 dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
110 dmacHw_REG64_t DmaIdReg; /* DMA ID Register */
111 dmacHw_REG64_t DmaTestReg; /* DMA Test Register */
112 dmacHw_REG64_t Reserved0; /* Reserved */
113 dmacHw_REG64_t Reserved1; /* Reserved */
114 dmacHw_REG64_t CompParm6; /* Component Parameter 6 */
115 dmacHw_REG64_t CompParm5; /* Component Parameter 5 */
116 dmacHw_REG64_t CompParm4; /* Component Parameter 4 */
117 dmacHw_REG64_t CompParm3; /* Component Parameter 3 */
118 dmacHw_REG64_t CompParm2; /* Component Parameter 2 */
119 dmacHw_REG64_t CompParm1; /* Component Parameter 1 */
120 dmacHw_REG64_t CompId; /* Compoent ID */
121} dmacHw_MISC_t;
122
123/* Base registers */
124#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
125#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
126
127extern uint32_t dmaChannelCount_0;
128extern uint32_t dmaChannelCount_1;
129
130/* Define channel specific registers */
131#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
132
133/* Raw interrupt status registers */
134#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
135#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
136#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
137#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
138#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
139#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
140
141/* Interrupt status registers */
142#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
143#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
144#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
145#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
146#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
147#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
148
149/* Interrupt status registers */
150#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
151#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
152#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
153#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
154#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
155#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
156
157/* Interrupt clear registers */
158#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
159#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
160#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
161#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
162#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
163#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
164#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
165
166/* Software handshaking registers */
167#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
168#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
169#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
170#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
171#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
172#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
173#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
174
175/* Miscellaneous registers */
176#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
177#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
178#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
179#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
180#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
181#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
182#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
183#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
184#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
185#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
186#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
187#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
188#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
189#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
190#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
191#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
192#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
193
194/* Channel control registers */
195#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
196#define dmacHw_REG_DAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
197#define dmacHw_REG_LLP(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
198
199#define dmacHw_REG_CTL_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
200#define dmacHw_REG_CTL_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
201
202#define dmacHw_REG_SSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
203#define dmacHw_REG_DSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
204#define dmacHw_REG_SSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
205#define dmacHw_REG_DSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
206
207#define dmacHw_REG_CFG_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
208#define dmacHw_REG_CFG_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
209
210#define dmacHw_REG_SGR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
211#define dmacHw_REG_SGR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
212
213#define dmacHw_REG_DSR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
214#define dmacHw_REG_DSR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
215
216#define INT_STATUS_MASK(channel) (0x00000001 << (channel))
217#define CHANNEL_BUSY(mod, channel) (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
218
219/* Bit mask for REG_DMACx_CTL_LO */
220
221#define dmacHw_REG_CTL_INT_EN 0x00000001 /* Channel interrupt enable */
222
223#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK 0x0000000E /* Destination transaction width mask */
224#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT 1
225#define dmacHw_REG_CTL_DST_TR_WIDTH_8 0x00000000 /* Destination transaction width 8 bit */
226#define dmacHw_REG_CTL_DST_TR_WIDTH_16 0x00000002 /* Destination transaction width 16 bit */
227#define dmacHw_REG_CTL_DST_TR_WIDTH_32 0x00000004 /* Destination transaction width 32 bit */
228#define dmacHw_REG_CTL_DST_TR_WIDTH_64 0x00000006 /* Destination transaction width 64 bit */
229
230#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK 0x00000070 /* Source transaction width mask */
231#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT 4
232#define dmacHw_REG_CTL_SRC_TR_WIDTH_8 0x00000000 /* Source transaction width 8 bit */
233#define dmacHw_REG_CTL_SRC_TR_WIDTH_16 0x00000010 /* Source transaction width 16 bit */
234#define dmacHw_REG_CTL_SRC_TR_WIDTH_32 0x00000020 /* Source transaction width 32 bit */
235#define dmacHw_REG_CTL_SRC_TR_WIDTH_64 0x00000030 /* Source transaction width 64 bit */
236
237#define dmacHw_REG_CTL_DS_ENABLE 0x00040000 /* Destination scatter enable */
238#define dmacHw_REG_CTL_SG_ENABLE 0x00020000 /* Source gather enable */
239
240#define dmacHw_REG_CTL_DINC_MASK 0x00000180 /* Destination address inc/dec mask */
241#define dmacHw_REG_CTL_DINC_INC 0x00000000 /* Destination address increment */
242#define dmacHw_REG_CTL_DINC_DEC 0x00000080 /* Destination address decrement */
243#define dmacHw_REG_CTL_DINC_NC 0x00000100 /* Destination address no change */
244
245#define dmacHw_REG_CTL_SINC_MASK 0x00000600 /* Source address inc/dec mask */
246#define dmacHw_REG_CTL_SINC_INC 0x00000000 /* Source address increment */
247#define dmacHw_REG_CTL_SINC_DEC 0x00000200 /* Source address decrement */
248#define dmacHw_REG_CTL_SINC_NC 0x00000400 /* Source address no change */
249
250#define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction length */
251#define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */
252#define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction length 4 */
253#define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction length 8 */
254#define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction length 16 */
255
256#define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */
257#define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */
258#define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4 */
259#define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8 */
260#define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 16 */
261
262#define dmacHw_REG_CTL_TTFC_MASK 0x00700000 /* Transfer type and flow controller */
263#define dmacHw_REG_CTL_TTFC_MM_DMAC 0x00000000 /* Memory to Memory with DMAC as flow controller */
264#define dmacHw_REG_CTL_TTFC_MP_DMAC 0x00100000 /* Memory to Peripheral with DMAC as flow controller */
265#define dmacHw_REG_CTL_TTFC_PM_DMAC 0x00200000 /* Peripheral to Memory with DMAC as flow controller */
266#define dmacHw_REG_CTL_TTFC_PP_DMAC 0x00300000 /* Peripheral to Peripheral with DMAC as flow controller */
267#define dmacHw_REG_CTL_TTFC_PM_PERI 0x00400000 /* Peripheral to Memory with Peripheral as flow controller */
268#define dmacHw_REG_CTL_TTFC_PP_SPERI 0x00500000 /* Peripheral to Peripheral with Source Peripheral as flow controller */
269#define dmacHw_REG_CTL_TTFC_MP_PERI 0x00600000 /* Memory to Peripheral with Peripheral as flow controller */
270#define dmacHw_REG_CTL_TTFC_PP_DPERI 0x00700000 /* Peripheral to Peripheral with Destination Peripheral as flow controller */
271
272#define dmacHw_REG_CTL_DMS_MASK 0x01800000 /* Destination AHB master interface */
273#define dmacHw_REG_CTL_DMS_1 0x00000000 /* Destination AHB master interface 1 */
274#define dmacHw_REG_CTL_DMS_2 0x00800000 /* Destination AHB master interface 2 */
275
276#define dmacHw_REG_CTL_SMS_MASK 0x06000000 /* Source AHB master interface */
277#define dmacHw_REG_CTL_SMS_1 0x00000000 /* Source AHB master interface 1 */
278#define dmacHw_REG_CTL_SMS_2 0x02000000 /* Source AHB master interface 2 */
279
280#define dmacHw_REG_CTL_LLP_DST_EN 0x08000000 /* Block chaining enable for destination side */
281#define dmacHw_REG_CTL_LLP_SRC_EN 0x10000000 /* Block chaining enable for source side */
282
283/* Bit mask for REG_DMACx_CTL_HI */
284#define dmacHw_REG_CTL_BLOCK_TS_MASK 0x00000FFF /* Block transfer size */
285#define dmacHw_REG_CTL_DONE 0x00001000 /* Block trasnfer done */
286
287/* Bit mask for REG_DMACx_CFG_LO */
288#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT 5 /* Channel priority shift */
289#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK 0x000000E0 /* Channel priority mask */
290#define dmacHw_REG_CFG_LO_CH_PRIORITY_0 0x00000000 /* Channel priority 0 */
291#define dmacHw_REG_CFG_LO_CH_PRIORITY_1 0x00000020 /* Channel priority 1 */
292#define dmacHw_REG_CFG_LO_CH_PRIORITY_2 0x00000040 /* Channel priority 2 */
293#define dmacHw_REG_CFG_LO_CH_PRIORITY_3 0x00000060 /* Channel priority 3 */
294#define dmacHw_REG_CFG_LO_CH_PRIORITY_4 0x00000080 /* Channel priority 4 */
295#define dmacHw_REG_CFG_LO_CH_PRIORITY_5 0x000000A0 /* Channel priority 5 */
296#define dmacHw_REG_CFG_LO_CH_PRIORITY_6 0x000000C0 /* Channel priority 6 */
297#define dmacHw_REG_CFG_LO_CH_PRIORITY_7 0x000000E0 /* Channel priority 7 */
298
299#define dmacHw_REG_CFG_LO_CH_SUSPEND 0x00000100 /* Channel suspend */
300#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY 0x00000200 /* Channel FIFO empty */
301#define dmacHw_REG_CFG_LO_DST_CH_SW_HS 0x00000400 /* Destination channel SW handshaking */
302#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS 0x00000800 /* Source channel SW handshaking */
303
304#define dmacHw_REG_CFG_LO_CH_LOCK_MASK 0x00003000 /* Channel locking mask */
305#define dmacHw_REG_CFG_LO_CH_LOCK_DMA 0x00000000 /* Channel lock over the entire DMA transfer operation */
306#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK 0x00001000 /* Channel lock over the block transfer operation */
307#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS 0x00002000 /* Channel lock over the transaction */
308#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE 0x00010000 /* Channel lock enable */
309
310#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK 0x0000C000 /* Bus locking mask */
311#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA 0x00000000 /* Bus lock over the entire DMA transfer operation */
312#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK 0x00004000 /* Bus lock over the block transfer operation */
313#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS 0x00008000 /* Bus lock over the transaction */
314#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE 0x00020000 /* Bus lock enable */
315
316#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW 0x00040000 /* Destination channel handshaking signal polarity low */
317#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW 0x00080000 /* Source channel handshaking signal polarity low */
318
319#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK 0x3FF00000 /* Maximum AMBA burst length */
320
321#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC 0x40000000 /* Source address auto reload */
322#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST 0x80000000 /* Destination address auto reload */
323
324/* Bit mask for REG_DMACx_CFG_HI */
325#define dmacHw_REG_CFG_HI_FC_DST_READY 0x00000001 /* Source transaction request is serviced when destination is ready */
326#define dmacHw_REG_CFG_HI_FIFO_ENOUGH 0x00000002 /* Initiate burst transaction when enough data in available in FIFO */
327
328#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK 0x0000001C /* AHB protection mask */
329#define dmacHw_REG_CFG_HI_AHB_HPROT_1 0x00000004 /* AHB protection 1 */
330#define dmacHw_REG_CFG_HI_AHB_HPROT_2 0x00000008 /* AHB protection 2 */
331#define dmacHw_REG_CFG_HI_AHB_HPROT_3 0x00000010 /* AHB protection 3 */
332
333#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT 0x00000020 /* Destination status update enable */
334#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT 0x00000040 /* Source status update enable */
335
336#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK 0x00000780 /* Source peripheral hardware interface mask */
337#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK 0x00007800 /* Destination peripheral hardware interface mask */
338
339/* DMA Configuration Parameters */
340#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS 0x00000700 /* Number of channels */
341#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE 0x00001800 /* Number of master interface */
342#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE 0x0000000f /* Maximum brust size */
343#define dmacHw_REG_COMP_PARAM_DATA_WIDTH 0x00006000 /* Data transfer width */
344
345/* Define GET/SET macros to program the registers */
346#define dmacHw_SET_SAR(module, channel, addr) (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
347#define dmacHw_SET_DAR(module, channel, addr) (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
348#define dmacHw_SET_LLP(module, channel, ptr) (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
349
350#define dmacHw_GET_SSTAT(module, channel) (dmacHw_REG_SSTAT((module), (channel)))
351#define dmacHw_GET_DSTAT(module, channel) (dmacHw_REG_DSTAT((module), (channel)))
352
353#define dmacHw_SET_SSTATAR(module, channel, addr) (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
354#define dmacHw_SET_DSTATAR(module, channel, addr) (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
355
356#define dmacHw_SET_CONTROL_LO(module, channel, ctl) (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
357#define dmacHw_RESET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)) = 0)
358#define dmacHw_GET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)))
359
360#define dmacHw_SET_CONTROL_HI(module, channel, ctl) (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
361#define dmacHw_RESET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) = 0)
362#define dmacHw_GET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)))
363
364#define dmacHw_GET_BLOCK_SIZE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
365#define dmacHw_DMA_COMPLETE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
366
367#define dmacHw_SET_CONFIG_LO(module, channel, cfg) (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
368#define dmacHw_RESET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)) = 0)
369#define dmacHw_GET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)))
370#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
371#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
372#define dmacHw_SET_AHB_HPROT(module, channel, protect) (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
373
374#define dmacHw_SET_CONFIG_HI(module, channel, cfg) (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
375#define dmacHw_RESET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)) = 0)
376#define dmacHw_GET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)))
377#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
378#define dmacHw_SRC_PERI_INTF(intf) (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
379#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
380#define dmacHw_DST_PERI_INTF(intf) (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
381
382#define dmacHw_DMA_START(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
383#define dmacHw_DMA_STOP(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
384#define dmacHw_DMA_ENABLE(module) (dmacHw_REG_MISC_CFG((module)) = 1)
385#define dmacHw_DMA_DISABLE(module) (dmacHw_REG_MISC_CFG((module)) = 0)
386
387#define dmacHw_TRAN_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
388#define dmacHw_BLOCK_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
389#define dmacHw_ERROR_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
390
391#define dmacHw_TRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
392#define dmacHw_BLOCK_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
393#define dmacHw_ERROR_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
394#define dmacHw_STRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
395#define dmacHw_DTRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
396
397#define dmacHw_TRAN_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
398#define dmacHw_BLOCK_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
399#define dmacHw_ERROR_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
400
401#define dmacHw_GET_NUM_CHANNEL(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
402#define dmacHw_GET_NUM_INTERFACE(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
403#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
404#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
405
406#endif /* _DMACHW_REG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 15:33:18 -0500