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-rw-r--r--arch/arm/mach-bcmring/include/mach/io.h35
1 files changed, 6 insertions, 29 deletions
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
index 4db0eff90357..dae5e9b166ea 100644
--- a/arch/arm/mach-bcmring/include/mach/io.h
+++ b/arch/arm/mach-bcmring/include/mach/io.h
@@ -23,34 +23,11 @@
23 23
24#define IO_SPACE_LIMIT 0xffffffff 24#define IO_SPACE_LIMIT 0xffffffff
25 25
26#define __io(a) ((void __iomem *)HW_IO_PHYS_TO_VIRT(a)) 26/*
27 27 * We don't actually have real ISA nor PCI buses, but there is so many
28/* Do not enable mem_pci for a big endian arm architecture or unexpected byteswaps will */ 28 * drivers out there that might just work if we fake them...
29/* happen in readw/writew etc. */ 29 */
30 30#define __io(a) __typesafe_io(a)
31#define readb(c) __raw_readb(c) 31#define __mem_pci(a) (a)
32#define readw(c) __raw_readw(c)
33#define readl(c) __raw_readl(c)
34#define readb_relaxed(addr) readb(addr)
35#define readw_relaxed(addr) readw(addr)
36#define readl_relaxed(addr) readl(addr)
37
38#define readsb(p, d, l) __raw_readsb(p, d, l)
39#define readsw(p, d, l) __raw_readsw(p, d, l)
40#define readsl(p, d, l) __raw_readsl(p, d, l)
41
42#define writeb(v, c) __raw_writeb(v, c)
43#define writew(v, c) __raw_writew(v, c)
44#define writel(v, c) __raw_writel(v, c)
45
46#define writesb(p, d, l) __raw_writesb(p, d, l)
47#define writesw(p, d, l) __raw_writesw(p, d, l)
48#define writesl(p, d, l) __raw_writesl(p, d, l)
49
50#define memset_io(c, v, l) _memset_io((c), (v), (l))
51#define memcpy_fromio(a, c, l) _memcpy_fromio((a), (c), (l))
52#define memcpy_toio(c, a, l) _memcpy_toio((c), (a), (l))
53
54#define eth_io_copy_and_sum(s, c, l, b) eth_copy_and_sum((s), (c), (l), (b))
55 32
56#endif 33#endif