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diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
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1/*****************************************************************************
2* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file dmacHw_priv.h
18*
19* @brief Private Definitions for low level DMA driver
20*
21*/
22/****************************************************************************/
23
24#ifndef _DMACHW_PRIV_H
25#define _DMACHW_PRIV_H
26
27#include <csp/stdint.h>
28
29/* Data type for DMA Link List Item */
30typedef struct {
31 uint32_t sar; /* Source Adress Register.
32 Address must be aligned to CTLx.SRC_TR_WIDTH. */
33 uint32_t dar; /* Destination Address Register.
34 Address must be aligned to CTLx.DST_TR_WIDTH. */
35 uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
36 Address MUST be aligned to a 32-bit boundary. */
37 dmacHw_REG64_t ctl; /* Control Register. 64 bits */
38 uint32_t sstat; /* Source Status Register */
39 uint32_t dstat; /* Destination Status Register */
40 uint32_t devCtl; /* Device specific control information */
41 uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
42} dmacHw_DESC_t;
43
44/*
45 * Descriptor ring pointers
46 */
47typedef struct {
48 int num; /* Number of link items */
49 dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */
50 dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */
51 dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */
52 dmacHw_DESC_t *pEnd; /* End of current descriptor chain */
53 dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */
54 uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */
55} dmacHw_DESC_RING_t;
56
57/*
58 * DMA channel control block
59 */
60typedef struct {
61 uint32_t module; /* DMA controller module (0-1) */
62 uint32_t channel; /* DMA channel (0-7) */
63 volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */
64 volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */
65 void *userData; /* Channel specifc user data */
66} dmacHw_CBLK_t;
67
68#define dmacHw_ASSERT(a) if (!(a)) while (1)
69#define dmacHw_MAX_CHANNEL_COUNT 16
70#define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF
71#define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE
72#define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF)
73#define dmacHw_MAX_BLOCKSIZE 4064
74#define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr)
75#define dmacHw_ADDRESS_MASK(byte) ((byte) - 1)
76#define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
77#define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle))
78#define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp))
79#define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
80
81/****************************************************************************/
82/**
83* @brief Get next available transaction width
84*
85*
86* @return On sucess : Next avail able transaction width
87* On failure : dmacHw_TRANSACTION_WIDTH_8
88*
89* @note
90* None
91*/
92/****************************************************************************/
93static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */
94 ) {
95 if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
96 return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
97 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
98 } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
99 return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
100 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
101 }
102
103 /* Default return */
104 return dmacHw_SRC_TRANSACTION_WIDTH_8;
105}
106
107/****************************************************************************/
108/**
109* @brief Get number of bytes per transaction
110*
111* @return Number of bytes per transaction
112*
113*
114* @note
115* None
116*/
117/****************************************************************************/
118static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */
119 ) {
120 int width = 1;
121 switch (tw) {
122 case dmacHw_SRC_TRANSACTION_WIDTH_8:
123 width = 1;
124 break;
125 case dmacHw_SRC_TRANSACTION_WIDTH_16:
126 case dmacHw_DST_TRANSACTION_WIDTH_16:
127 width = 2;
128 break;
129 case dmacHw_SRC_TRANSACTION_WIDTH_32:
130 case dmacHw_DST_TRANSACTION_WIDTH_32:
131 width = 4;
132 break;
133 case dmacHw_SRC_TRANSACTION_WIDTH_64:
134 case dmacHw_DST_TRANSACTION_WIDTH_64:
135 width = 8;
136 break;
137 default:
138 dmacHw_ASSERT(0);
139 }
140
141 /* Default transaction width */
142 return width;
143}
144
145#endif /* _DMACHW_PRIV_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 14:53:16 -0500