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-rw-r--r--arch/arm/mach-at91/Makefile2
-rw-r--r--arch/arm/mach-at91/Makefile.boot8
-rw-r--r--arch/arm/mach-at91/at91rm9200.c8
-rw-r--r--arch/arm/mach-at91/at91rm9200_devices.c14
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c37
-rw-r--r--arch/arm/mach-at91/at91sam9260.c30
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c59
-rw-r--r--arch/arm/mach-at91/at91sam9261.c10
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c31
-rw-r--r--arch/arm/mach-at91/at91sam9263.c11
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c59
-rw-r--r--arch/arm/mach-at91/at91sam926x_time.c68
-rw-r--r--arch/arm/mach-at91/at91sam9_alt_reset.S12
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c14
-rw-r--r--arch/arm/mach-at91/at91sam9g45_devices.c52
-rw-r--r--arch/arm/mach-at91/at91sam9g45_reset.S12
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c10
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c31
-rw-r--r--arch/arm/mach-at91/at91sam9x5.c7
-rw-r--r--arch/arm/mach-at91/at91x40.c2
-rw-r--r--arch/arm/mach-at91/at91x40_time.c28
-rw-r--r--arch/arm/mach-at91/board-cpu9krea.c5
-rw-r--r--arch/arm/mach-at91/board-cpuat91.c1
-rw-r--r--arch/arm/mach-at91/board-dt.c20
-rw-r--r--arch/arm/mach-at91/board-eco920.c5
-rw-r--r--arch/arm/mach-at91/board-kb9202.c1
-rw-r--r--arch/arm/mach-at91/board-picotux200.c1
-rw-r--r--arch/arm/mach-at91/board-rm9200dk.c1
-rw-r--r--arch/arm/mach-at91/board-rm9200ek.c1
-rw-r--r--arch/arm/mach-at91/board-snapper9260.c10
-rw-r--r--arch/arm/mach-at91/board-yl-9200.c3
-rw-r--r--arch/arm/mach-at91/clock.c88
-rw-r--r--arch/arm/mach-at91/generic.h16
-rw-r--r--arch/arm/mach-at91/gpio.c625
-rw-r--r--arch/arm/mach-at91/include/mach/at91_matrix.h23
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pio.h25
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pmc.h56
-rw-r--r--arch/arm/mach-at91/include/mach/at91_ramc.h32
-rw-r--r--arch/arm/mach-at91/include/mach/at91_st.h32
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h10
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_mc.h58
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h63
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h14
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260_matrix.h36
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h10
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261_matrix.h18
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h12
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263_matrix.h74
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_sdramc.h6
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h12
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h84
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h7
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h42
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9x5.h5
-rw-r--r--arch/arm/mach-at91/include/mach/at91x40.h18
-rw-r--r--arch/arm/mach-at91/include/mach/gpio.h17
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h3
-rw-r--r--arch/arm/mach-at91/include/mach/io.h18
-rw-r--r--arch/arm/mach-at91/irq.c132
-rw-r--r--arch/arm/mach-at91/pm.c35
-rw-r--r--arch/arm/mach-at91/pm.h11
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S271
-rw-r--r--arch/arm/mach-at91/setup.c9
64 files changed, 1675 insertions, 746 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 1b6518518d99..8512e53bed93 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_d
20obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o 20obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
21obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o 21obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
22obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o 22obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
23obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o 23obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o sam9_smc.o
24obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 24obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
25 25
26# AT91RM9200 board-specific support 26# AT91RM9200 board-specific support
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 2fd051eb2449..0da66ca4a4f8 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -13,4 +13,10 @@ params_phys-y := 0x20000100
13initrd_phys-y := 0x20410000 13initrd_phys-y := 0x20410000
14endif 14endif
15 15
16dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb 16# Keep dtb files sorted alphabetically for each SoC
17# sam9g20
18dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
19# sam9g45
20dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
21# sam9x5
22dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index dd6e2de13420..0df1045311e4 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -295,7 +295,7 @@ static void at91rm9200_idle(void)
295 * Disable the processor clock. The processor will be automatically 295 * Disable the processor clock. The processor will be automatically
296 * re-enabled by an interrupt or by a reset. 296 * re-enabled by an interrupt or by a reset.
297 */ 297 */
298 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); 298 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
299} 299}
300 300
301static void at91rm9200_restart(char mode, const char *cmd) 301static void at91rm9200_restart(char mode, const char *cmd)
@@ -303,8 +303,8 @@ static void at91rm9200_restart(char mode, const char *cmd)
303 /* 303 /*
304 * Perform a hardware reset with the use of the Watchdog timer. 304 * Perform a hardware reset with the use of the Watchdog timer.
305 */ 305 */
306 at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); 306 at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
307 at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); 307 at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
308} 308}
309 309
310/* -------------------------------------------------------------------- 310/* --------------------------------------------------------------------
@@ -319,6 +319,8 @@ static void __init at91rm9200_map_io(void)
319 319
320static void __init at91rm9200_ioremap_registers(void) 320static void __init at91rm9200_ioremap_registers(void)
321{ 321{
322 at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
323 at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
322} 324}
323 325
324static void __init at91rm9200_initialize(void) 326static void __init at91rm9200_initialize(void)
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 97676bdae998..99ce5c955e39 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -21,6 +21,7 @@
21#include <mach/board.h> 21#include <mach/board.h>
22#include <mach/at91rm9200.h> 22#include <mach/at91rm9200.h>
23#include <mach/at91rm9200_mc.h> 23#include <mach/at91rm9200_mc.h>
24#include <mach/at91_ramc.h>
24 25
25#include "generic.h" 26#include "generic.h"
26 27
@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
241 data->chipselect = 4; /* can only use EBI ChipSelect 4 */ 242 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
242 243
243 /* CF takes over CS4, CS5, CS6 */ 244 /* CF takes over CS4, CS5, CS6 */
244 csa = at91_sys_read(AT91_EBI_CSA); 245 csa = at91_ramc_read(0, AT91_EBI_CSA);
245 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH); 246 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
246 247
247 /* 248 /*
248 * Static memory controller timing adjustments. 249 * Static memory controller timing adjustments.
249 * REVISIT: these timings are in terms of MCK cycles, so 250 * REVISIT: these timings are in terms of MCK cycles, so
250 * when MCK changes (cpufreq etc) so must these values... 251 * when MCK changes (cpufreq etc) so must these values...
251 */ 252 */
252 at91_sys_write(AT91_SMC_CSR(4), 253 at91_ramc_write(0, AT91_SMC_CSR(4),
253 AT91_SMC_ACSS_STD 254 AT91_SMC_ACSS_STD
254 | AT91_SMC_DBW_16 255 | AT91_SMC_DBW_16
255 | AT91_SMC_BAT 256 | AT91_SMC_BAT
@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
407 return; 408 return;
408 409
409 /* enable the address range of CS3 */ 410 /* enable the address range of CS3 */
410 csa = at91_sys_read(AT91_EBI_CSA); 411 csa = at91_ramc_read(0, AT91_EBI_CSA);
411 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA); 412 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
412 413
413 /* set the bus interface characteristics */ 414 /* set the bus interface characteristics */
414 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN 415 at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
415 | AT91_SMC_NWS_(5) 416 | AT91_SMC_NWS_(5)
416 | AT91_SMC_TDF_(1) 417 | AT91_SMC_TDF_(1)
417 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */ 418 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
@@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
1114} 1115}
1115 1116
1116static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1117static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1117struct platform_device *atmel_default_console_device; /* the serial console device */
1118 1118
1119void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1119void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1120{ 1120{
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index a028cdf8f974..dd7f782b0b91 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
43{ 43{
44 unsigned long x1, x2; 44 unsigned long x1, x2;
45 45
46 x1 = at91_sys_read(AT91_ST_CRTR); 46 x1 = at91_st_read(AT91_ST_CRTR);
47 do { 47 do {
48 x2 = at91_sys_read(AT91_ST_CRTR); 48 x2 = at91_st_read(AT91_ST_CRTR);
49 if (x1 == x2) 49 if (x1 == x2)
50 break; 50 break;
51 x1 = x2; 51 x1 = x2;
@@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
58 */ 58 */
59static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) 59static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
60{ 60{
61 u32 sr = at91_sys_read(AT91_ST_SR) & irqmask; 61 u32 sr = at91_st_read(AT91_ST_SR) & irqmask;
62 62
63 /* 63 /*
64 * irqs should be disabled here, but as the irq is shared they are only 64 * irqs should be disabled here, but as the irq is shared they are only
@@ -110,22 +110,22 @@ static void
110clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) 110clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
111{ 111{
112 /* Disable and flush pending timer interrupts */ 112 /* Disable and flush pending timer interrupts */
113 at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); 113 at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
114 (void) at91_sys_read(AT91_ST_SR); 114 at91_st_read(AT91_ST_SR);
115 115
116 last_crtr = read_CRTR(); 116 last_crtr = read_CRTR();
117 switch (mode) { 117 switch (mode) {
118 case CLOCK_EVT_MODE_PERIODIC: 118 case CLOCK_EVT_MODE_PERIODIC:
119 /* PIT for periodic irqs; fixed rate of 1/HZ */ 119 /* PIT for periodic irqs; fixed rate of 1/HZ */
120 irqmask = AT91_ST_PITS; 120 irqmask = AT91_ST_PITS;
121 at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH); 121 at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
122 break; 122 break;
123 case CLOCK_EVT_MODE_ONESHOT: 123 case CLOCK_EVT_MODE_ONESHOT:
124 /* ALM for oneshot irqs, set by next_event() 124 /* ALM for oneshot irqs, set by next_event()
125 * before 32 seconds have passed 125 * before 32 seconds have passed
126 */ 126 */
127 irqmask = AT91_ST_ALMS; 127 irqmask = AT91_ST_ALMS;
128 at91_sys_write(AT91_ST_RTAR, last_crtr); 128 at91_st_write(AT91_ST_RTAR, last_crtr);
129 break; 129 break;
130 case CLOCK_EVT_MODE_SHUTDOWN: 130 case CLOCK_EVT_MODE_SHUTDOWN:
131 case CLOCK_EVT_MODE_UNUSED: 131 case CLOCK_EVT_MODE_UNUSED:
@@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
133 irqmask = 0; 133 irqmask = 0;
134 break; 134 break;
135 } 135 }
136 at91_sys_write(AT91_ST_IER, irqmask); 136 at91_st_write(AT91_ST_IER, irqmask);
137} 137}
138 138
139static int 139static int
@@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
156 alm = read_CRTR(); 156 alm = read_CRTR();
157 157
158 /* Cancel any pending alarm; flush any pending IRQ */ 158 /* Cancel any pending alarm; flush any pending IRQ */
159 at91_sys_write(AT91_ST_RTAR, alm); 159 at91_st_write(AT91_ST_RTAR, alm);
160 (void) at91_sys_read(AT91_ST_SR); 160 at91_st_read(AT91_ST_SR);
161 161
162 /* Schedule alarm by writing RTAR. */ 162 /* Schedule alarm by writing RTAR. */
163 alm += delta; 163 alm += delta;
164 at91_sys_write(AT91_ST_RTAR, alm); 164 at91_st_write(AT91_ST_RTAR, alm);
165 165
166 return status; 166 return status;
167} 167}
@@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
175 .set_mode = clkevt32k_mode, 175 .set_mode = clkevt32k_mode,
176}; 176};
177 177
178void __iomem *at91_st_base;
179
180void __init at91rm9200_ioremap_st(u32 addr)
181{
182 at91_st_base = ioremap(addr, 256);
183 if (!at91_st_base)
184 panic("Impossible to ioremap ST\n");
185}
186
178/* 187/*
179 * ST (system timer) module supports both clockevents and clocksource. 188 * ST (system timer) module supports both clockevents and clocksource.
180 */ 189 */
181void __init at91rm9200_timer_init(void) 190void __init at91rm9200_timer_init(void)
182{ 191{
183 /* Disable all timer interrupts, and clear any pending ones */ 192 /* Disable all timer interrupts, and clear any pending ones */
184 at91_sys_write(AT91_ST_IDR, 193 at91_st_write(AT91_ST_IDR,
185 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); 194 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
186 (void) at91_sys_read(AT91_ST_SR); 195 at91_st_read(AT91_ST_SR);
187 196
188 /* Make IRQs happen for the system timer */ 197 /* Make IRQs happen for the system timer */
189 setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); 198 setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
@@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
192 * directly for the clocksource and all clockevents, after adjusting 201 * directly for the clocksource and all clockevents, after adjusting
193 * its prescaler from the 1 Hz default. 202 * its prescaler from the 1 Hz default.
194 */ 203 */
195 at91_sys_write(AT91_ST_RTMR, 1); 204 at91_st_write(AT91_ST_RTMR, 1);
196 205
197 /* Setup timer clockevent, with minimum of two ticks (important!!) */ 206 /* Setup timer clockevent, with minimum of two ticks (important!!) */
198 clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); 207 clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 9ac8c6fe3363..14b5a9c9a514 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -209,6 +209,13 @@ static struct clk_lookup periph_clocks_lookups[] = {
209 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk), 209 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
210 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk), 210 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
211 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk), 211 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
212 /* more tc lookup table for DT entries */
213 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
214 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
215 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
216 CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
217 CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
218 CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
212 /* fake hclk clock */ 219 /* fake hclk clock */
213 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), 220 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
214 CLKDEV_CON_ID("pioA", &pioA_clk), 221 CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -310,34 +317,27 @@ static void __init at91sam9xe_map_io(void)
310 317
311static void __init at91sam9260_map_io(void) 318static void __init at91sam9260_map_io(void)
312{ 319{
313 if (cpu_is_at91sam9xe()) { 320 if (cpu_is_at91sam9xe())
314 at91sam9xe_map_io(); 321 at91sam9xe_map_io();
315 } else if (cpu_is_at91sam9g20()) { 322 else if (cpu_is_at91sam9g20())
316 at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE); 323 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
317 at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE); 324 else
318 } else { 325 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
319 at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
320 at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
321 }
322} 326}
323 327
324static void __init at91sam9260_ioremap_registers(void) 328static void __init at91sam9260_ioremap_registers(void)
325{ 329{
326 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); 330 at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
327 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC); 331 at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
332 at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
328 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); 333 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
329 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); 334 at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
330} 335 at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
331
332static void at91sam9260_idle(void)
333{
334 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
335 cpu_do_idle();
336} 336}
337 337
338static void __init at91sam9260_initialize(void) 338static void __init at91sam9260_initialize(void)
339{ 339{
340 arm_pm_idle = at91sam9260_idle; 340 arm_pm_idle = at91sam9_idle;
341 arm_pm_restart = at91sam9_alt_restart; 341 arm_pm_restart = at91sam9_alt_restart;
342 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) 342 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
343 | (1 << AT91SAM9260_ID_IRQ2); 343 | (1 << AT91SAM9260_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 5a24f0b4554d..7e5651ee9f85 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,6 +21,7 @@
21#include <mach/cpu.h> 21#include <mach/cpu.h>
22#include <mach/at91sam9260.h> 22#include <mach/at91sam9260.h>
23#include <mach/at91sam9260_matrix.h> 23#include <mach/at91sam9260_matrix.h>
24#include <mach/at91_matrix.h>
24#include <mach/at91sam9_smc.h> 25#include <mach/at91sam9_smc.h>
25 26
26#include "generic.h" 27#include "generic.h"
@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
422 if (!data) 423 if (!data)
423 return; 424 return;
424 425
425 csa = at91_sys_read(AT91_MATRIX_EBICSA); 426 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
426 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 427 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
427 428
428 /* enable pin */ 429 /* enable pin */
429 if (gpio_is_valid(data->enable_pin)) 430 if (gpio_is_valid(data->enable_pin))
@@ -641,7 +642,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
641static struct resource tcb0_resources[] = { 642static struct resource tcb0_resources[] = {
642 [0] = { 643 [0] = {
643 .start = AT91SAM9260_BASE_TCB0, 644 .start = AT91SAM9260_BASE_TCB0,
644 .end = AT91SAM9260_BASE_TCB0 + SZ_16K - 1, 645 .end = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
645 .flags = IORESOURCE_MEM, 646 .flags = IORESOURCE_MEM,
646 }, 647 },
647 [1] = { 648 [1] = {
@@ -671,7 +672,7 @@ static struct platform_device at91sam9260_tcb0_device = {
671static struct resource tcb1_resources[] = { 672static struct resource tcb1_resources[] = {
672 [0] = { 673 [0] = {
673 .start = AT91SAM9260_BASE_TCB1, 674 .start = AT91SAM9260_BASE_TCB1,
674 .end = AT91SAM9260_BASE_TCB1 + SZ_16K - 1, 675 .end = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
675 .flags = IORESOURCE_MEM, 676 .flags = IORESOURCE_MEM,
676 }, 677 },
677 [1] = { 678 [1] = {
@@ -698,8 +699,25 @@ static struct platform_device at91sam9260_tcb1_device = {
698 .num_resources = ARRAY_SIZE(tcb1_resources), 699 .num_resources = ARRAY_SIZE(tcb1_resources),
699}; 700};
700 701
702#if defined(CONFIG_OF)
703static struct of_device_id tcb_ids[] = {
704 { .compatible = "atmel,at91rm9200-tcb" },
705 { /*sentinel*/ }
706};
707#endif
708
701static void __init at91_add_device_tc(void) 709static void __init at91_add_device_tc(void)
702{ 710{
711#if defined(CONFIG_OF)
712 struct device_node *np;
713
714 np = of_find_matching_node(NULL, tcb_ids);
715 if (np) {
716 of_node_put(np);
717 return;
718 }
719#endif
720
703 platform_device_register(&at91sam9260_tcb0_device); 721 platform_device_register(&at91sam9260_tcb0_device);
704 platform_device_register(&at91sam9260_tcb1_device); 722 platform_device_register(&at91sam9260_tcb1_device);
705} 723}
@@ -717,18 +735,42 @@ static struct resource rtt_resources[] = {
717 .start = AT91SAM9260_BASE_RTT, 735 .start = AT91SAM9260_BASE_RTT,
718 .end = AT91SAM9260_BASE_RTT + SZ_16 - 1, 736 .end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
719 .flags = IORESOURCE_MEM, 737 .flags = IORESOURCE_MEM,
720 } 738 }, {
739 .flags = IORESOURCE_MEM,
740 },
721}; 741};
722 742
723static struct platform_device at91sam9260_rtt_device = { 743static struct platform_device at91sam9260_rtt_device = {
724 .name = "at91_rtt", 744 .name = "at91_rtt",
725 .id = 0, 745 .id = 0,
726 .resource = rtt_resources, 746 .resource = rtt_resources,
727 .num_resources = ARRAY_SIZE(rtt_resources),
728}; 747};
729 748
749
750#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
751static void __init at91_add_device_rtt_rtc(void)
752{
753 at91sam9260_rtt_device.name = "rtc-at91sam9";
754 /*
755 * The second resource is needed:
756 * GPBR will serve as the storage for RTC time offset
757 */
758 at91sam9260_rtt_device.num_resources = 2;
759 rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
760 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
761 rtt_resources[1].end = rtt_resources[1].start + 3;
762}
763#else
764static void __init at91_add_device_rtt_rtc(void)
765{
766 /* Only one resource is needed: RTT not used as RTC */
767 at91sam9260_rtt_device.num_resources = 1;
768}
769#endif
770
730static void __init at91_add_device_rtt(void) 771static void __init at91_add_device_rtt(void)
731{ 772{
773 at91_add_device_rtt_rtc();
732 platform_device_register(&at91sam9260_rtt_device); 774 platform_device_register(&at91sam9260_rtt_device);
733} 775}
734 776
@@ -1139,7 +1181,6 @@ static inline void configure_usart5_pins(void)
1139} 1181}
1140 1182
1141static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1183static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1142struct platform_device *atmel_default_console_device; /* the serial console device */
1143 1184
1144void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1185void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1145{ 1186{
@@ -1264,7 +1305,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1264 if (!data) 1305 if (!data)
1265 return; 1306 return;
1266 1307
1267 csa = at91_sys_read(AT91_MATRIX_EBICSA); 1308 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
1268 1309
1269 switch (data->chipselect) { 1310 switch (data->chipselect) {
1270 case 4: 1311 case 4:
@@ -1287,7 +1328,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
1287 return; 1328 return;
1288 } 1329 }
1289 1330
1290 at91_sys_write(AT91_MATRIX_EBICSA, csa); 1331 at91_matrix_write(AT91_MATRIX_EBICSA, csa);
1291 1332
1292 if (gpio_is_valid(data->rst_pin)) { 1333 if (gpio_is_valid(data->rst_pin)) {
1293 at91_set_multi_drive(data->rst_pin, 0); 1334 at91_set_multi_drive(data->rst_pin, 0);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index ab76868f01f5..684c5dfd92ac 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -283,19 +283,15 @@ static void __init at91sam9261_ioremap_registers(void)
283{ 283{
284 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC); 284 at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
285 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC); 285 at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
286 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
286 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT); 287 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
287 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC); 288 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
288} 289 at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
289
290static void at91sam9261_idle(void)
291{
292 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
293 cpu_do_idle();
294} 290}
295 291
296static void __init at91sam9261_initialize(void) 292static void __init at91sam9261_initialize(void)
297{ 293{
298 arm_pm_idle = at91sam9261_idle; 294 arm_pm_idle = at91sam9_idle;
299 arm_pm_restart = at91sam9_alt_restart; 295 arm_pm_restart = at91sam9_alt_restart;
300 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) 296 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
301 | (1 << AT91SAM9261_ID_IRQ2); 297 | (1 << AT91SAM9261_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 1e28bed8f425..096da87dc00d 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -24,6 +24,7 @@
24#include <mach/board.h> 24#include <mach/board.h>
25#include <mach/at91sam9261.h> 25#include <mach/at91sam9261.h>
26#include <mach/at91sam9261_matrix.h> 26#include <mach/at91sam9261_matrix.h>
27#include <mach/at91_matrix.h>
27#include <mach/at91sam9_smc.h> 28#include <mach/at91sam9_smc.h>
28 29
29#include "generic.h" 30#include "generic.h"
@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
236 if (!data) 237 if (!data)
237 return; 238 return;
238 239
239 csa = at91_sys_read(AT91_MATRIX_EBICSA); 240 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
240 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 241 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
241 242
242 /* enable pin */ 243 /* enable pin */
243 if (gpio_is_valid(data->enable_pin)) 244 if (gpio_is_valid(data->enable_pin))
@@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
603 .start = AT91SAM9261_BASE_RTT, 604 .start = AT91SAM9261_BASE_RTT,
604 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1, 605 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
605 .flags = IORESOURCE_MEM, 606 .flags = IORESOURCE_MEM,
607 }, {
608 .flags = IORESOURCE_MEM,
606 } 609 }
607}; 610};
608 611
@@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
610 .name = "at91_rtt", 613 .name = "at91_rtt",
611 .id = 0, 614 .id = 0,
612 .resource = rtt_resources, 615 .resource = rtt_resources,
613 .num_resources = ARRAY_SIZE(rtt_resources),
614}; 616};
615 617
618#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
619static void __init at91_add_device_rtt_rtc(void)
620{
621 at91sam9261_rtt_device.name = "rtc-at91sam9";
622 /*
623 * The second resource is needed:
624 * GPBR will serve as the storage for RTC time offset
625 */
626 at91sam9261_rtt_device.num_resources = 2;
627 rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
628 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
629 rtt_resources[1].end = rtt_resources[1].start + 3;
630}
631#else
632static void __init at91_add_device_rtt_rtc(void)
633{
634 /* Only one resource is needed: RTT not used as RTC */
635 at91sam9261_rtt_device.num_resources = 1;
636}
637#endif
638
616static void __init at91_add_device_rtt(void) 639static void __init at91_add_device_rtt(void)
617{ 640{
641 at91_add_device_rtt_rtc();
618 platform_device_register(&at91sam9261_rtt_device); 642 platform_device_register(&at91sam9261_rtt_device);
619} 643}
620 644
@@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
991} 1015}
992 1016
993static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1017static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
994struct platform_device *atmel_default_console_device; /* the serial console device */
995 1018
996void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1019void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
997{ 1020{
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 247ab633abcc..0b4fa5a7f685 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -303,20 +303,17 @@ static void __init at91sam9263_ioremap_registers(void)
303{ 303{
304 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC); 304 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
305 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC); 305 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
306 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
307 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
306 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT); 308 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
307 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0); 309 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
308 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1); 310 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
309} 311 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
310
311static void at91sam9263_idle(void)
312{
313 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
314 cpu_do_idle();
315} 312}
316 313
317static void __init at91sam9263_initialize(void) 314static void __init at91sam9263_initialize(void)
318{ 315{
319 arm_pm_idle = at91sam9263_idle; 316 arm_pm_idle = at91sam9_idle;
320 arm_pm_restart = at91sam9_alt_restart; 317 arm_pm_restart = at91sam9_alt_restart;
321 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1); 318 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
322 319
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 70709ab0102a..53688c46f956 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -23,6 +23,7 @@
23#include <mach/board.h> 23#include <mach/board.h>
24#include <mach/at91sam9263.h> 24#include <mach/at91sam9263.h>
25#include <mach/at91sam9263_matrix.h> 25#include <mach/at91sam9263_matrix.h>
26#include <mach/at91_matrix.h>
26#include <mach/at91sam9_smc.h> 27#include <mach/at91sam9_smc.h>
27 28
28#include "generic.h" 29#include "generic.h"
@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
409 * we assume SMC timings are configured by board code, 410 * we assume SMC timings are configured by board code,
410 * except True IDE where timings are controlled by driver 411 * except True IDE where timings are controlled by driver
411 */ 412 */
412 ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA); 413 ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
413 switch (data->chipselect) { 414 switch (data->chipselect) {
414 case 4: 415 case 4:
415 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */ 416 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
428 data->chipselect); 429 data->chipselect);
429 return; 430 return;
430 } 431 }
431 at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa); 432 at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
432 433
433 if (gpio_is_valid(data->det_pin)) { 434 if (gpio_is_valid(data->det_pin)) {
434 at91_set_gpio_input(data->det_pin, 1); 435 at91_set_gpio_input(data->det_pin, 1);
@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
496 if (!data) 497 if (!data)
497 return; 498 return;
498 499
499 csa = at91_sys_read(AT91_MATRIX_EBI0CSA); 500 csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
500 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); 501 at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
501 502
502 /* enable pin */ 503 /* enable pin */
503 if (gpio_is_valid(data->enable_pin)) 504 if (gpio_is_valid(data->enable_pin))
@@ -966,6 +967,8 @@ static struct resource rtt0_resources[] = {
966 .start = AT91SAM9263_BASE_RTT0, 967 .start = AT91SAM9263_BASE_RTT0,
967 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1, 968 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
968 .flags = IORESOURCE_MEM, 969 .flags = IORESOURCE_MEM,
970 }, {
971 .flags = IORESOURCE_MEM,
969 } 972 }
970}; 973};
971 974
@@ -973,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
973 .name = "at91_rtt", 976 .name = "at91_rtt",
974 .id = 0, 977 .id = 0,
975 .resource = rtt0_resources, 978 .resource = rtt0_resources,
976 .num_resources = ARRAY_SIZE(rtt0_resources),
977}; 979};
978 980
979static struct resource rtt1_resources[] = { 981static struct resource rtt1_resources[] = {
@@ -981,6 +983,8 @@ static struct resource rtt1_resources[] = {
981 .start = AT91SAM9263_BASE_RTT1, 983 .start = AT91SAM9263_BASE_RTT1,
982 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1, 984 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
983 .flags = IORESOURCE_MEM, 985 .flags = IORESOURCE_MEM,
986 }, {
987 .flags = IORESOURCE_MEM,
984 } 988 }
985}; 989};
986 990
@@ -988,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
988 .name = "at91_rtt", 992 .name = "at91_rtt",
989 .id = 1, 993 .id = 1,
990 .resource = rtt1_resources, 994 .resource = rtt1_resources,
991 .num_resources = ARRAY_SIZE(rtt1_resources),
992}; 995};
993 996
997#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
998static void __init at91_add_device_rtt_rtc(void)
999{
1000 struct platform_device *pdev;
1001 struct resource *r;
1002
1003 switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
1004 case 0:
1005 /*
1006 * The second resource is needed only for the chosen RTT:
1007 * GPBR will serve as the storage for RTC time offset
1008 */
1009 at91sam9263_rtt0_device.num_resources = 2;
1010 at91sam9263_rtt1_device.num_resources = 1;
1011 pdev = &at91sam9263_rtt0_device;
1012 r = rtt0_resources;
1013 break;
1014 case 1:
1015 at91sam9263_rtt0_device.num_resources = 1;
1016 at91sam9263_rtt1_device.num_resources = 2;
1017 pdev = &at91sam9263_rtt1_device;
1018 r = rtt1_resources;
1019 break;
1020 default:
1021 pr_err("at91sam9263: only supports 2 RTT (%d)\n",
1022 CONFIG_RTC_DRV_AT91SAM9_RTT);
1023 return;
1024 }
1025
1026 pdev->name = "rtc-at91sam9";
1027 r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1028 r[1].end = r[1].start + 3;
1029}
1030#else
1031static void __init at91_add_device_rtt_rtc(void)
1032{
1033 /* Only one resource is needed: RTT not used as RTC */
1034 at91sam9263_rtt0_device.num_resources = 1;
1035 at91sam9263_rtt1_device.num_resources = 1;
1036}
1037#endif
1038
994static void __init at91_add_device_rtt(void) 1039static void __init at91_add_device_rtt(void)
995{ 1040{
1041 at91_add_device_rtt_rtc();
996 platform_device_register(&at91sam9263_rtt0_device); 1042 platform_device_register(&at91sam9263_rtt0_device);
997 platform_device_register(&at91sam9263_rtt1_device); 1043 platform_device_register(&at91sam9263_rtt1_device);
998} 1044}
@@ -1378,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
1378} 1424}
1379 1425
1380static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1426static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1381struct platform_device *atmel_default_console_device; /* the serial console device */
1382 1427
1383void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1428void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1384{ 1429{
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index d89ead740a99..a94758b42737 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,9 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/clockchips.h> 16#include <linux/clockchips.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
17 20
18#include <asm/mach/time.h> 21#include <asm/mach/time.h>
19 22
@@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
133static struct irqaction at91sam926x_pit_irq = { 136static struct irqaction at91sam926x_pit_irq = {
134 .name = "at91_tick", 137 .name = "at91_tick",
135 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 138 .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
136 .handler = at91sam926x_pit_interrupt 139 .handler = at91sam926x_pit_interrupt,
140 .irq = AT91_ID_SYS,
137}; 141};
138 142
139static void at91sam926x_pit_reset(void) 143static void at91sam926x_pit_reset(void)
@@ -149,6 +153,51 @@ static void at91sam926x_pit_reset(void)
149 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); 153 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
150} 154}
151 155
156#ifdef CONFIG_OF
157static struct of_device_id pit_timer_ids[] = {
158 { .compatible = "atmel,at91sam9260-pit" },
159 { /* sentinel */ }
160};
161
162static int __init of_at91sam926x_pit_init(void)
163{
164 struct device_node *np;
165 int ret;
166
167 np = of_find_matching_node(NULL, pit_timer_ids);
168 if (!np)
169 goto err;
170
171 pit_base_addr = of_iomap(np, 0);
172 if (!pit_base_addr)
173 goto node_err;
174
175 /* Get the interrupts property */
176 ret = irq_of_parse_and_map(np, 0);
177 if (!ret) {
178 pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
179 goto ioremap_err;
180 }
181 at91sam926x_pit_irq.irq = ret;
182
183 of_node_put(np);
184
185 return 0;
186
187ioremap_err:
188 iounmap(pit_base_addr);
189node_err:
190 of_node_put(np);
191err:
192 return -EINVAL;
193}
194#else
195static int __init of_at91sam926x_pit_init(void)
196{
197 return -EINVAL;
198}
199#endif
200
152/* 201/*
153 * Set up both clocksource and clockevent support. 202 * Set up both clocksource and clockevent support.
154 */ 203 */
@@ -156,6 +205,10 @@ static void __init at91sam926x_pit_init(void)
156{ 205{
157 unsigned long pit_rate; 206 unsigned long pit_rate;
158 unsigned bits; 207 unsigned bits;
208 int ret;
209
210 /* For device tree enabled device: initialize here */
211 of_at91sam926x_pit_init();
159 212
160 /* 213 /*
161 * Use our actual MCK to figure out how many MCK/16 ticks per 214 * Use our actual MCK to figure out how many MCK/16 ticks per
@@ -177,7 +230,9 @@ static void __init at91sam926x_pit_init(void)
177 clocksource_register_hz(&pit_clk, pit_rate); 230 clocksource_register_hz(&pit_clk, pit_rate);
178 231
179 /* Set up irq handler */ 232 /* Set up irq handler */
180 setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq); 233 ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
234 if (ret)
235 pr_crit("AT91: PIT: Unable to setup IRQ\n");
181 236
182 /* Set up and register clockevents */ 237 /* Set up and register clockevents */
183 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift); 238 pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,6 +248,15 @@ static void at91sam926x_pit_suspend(void)
193 248
194void __init at91sam926x_ioremap_pit(u32 addr) 249void __init at91sam926x_ioremap_pit(u32 addr)
195{ 250{
251#if defined(CONFIG_OF)
252 struct device_node *np =
253 of_find_matching_node(NULL, pit_timer_ids);
254
255 if (np) {
256 of_node_put(np);
257 return;
258 }
259#endif
196 pit_base_addr = ioremap(addr, 16); 260 pit_base_addr = ioremap(addr, 16);
197 261
198 if (!pit_base_addr) 262 if (!pit_base_addr)
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 518e42377171..7af2e108b8a0 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -15,16 +15,17 @@
15 15
16#include <linux/linkage.h> 16#include <linux/linkage.h>
17#include <mach/hardware.h> 17#include <mach/hardware.h>
18#include <mach/at91sam9_sdramc.h> 18#include <mach/at91_ramc.h>
19#include <mach/at91_rstc.h> 19#include <mach/at91_rstc.h>
20 20
21 .arm 21 .arm
22 22
23 .globl at91sam9_alt_restart 23 .globl at91sam9_alt_restart
24 24
25at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants 25at91sam9_alt_restart: ldr r0, =at91_ramc_base @ preload constants
26 ldr r1, =at91_rstc_base 26 ldr r0, [r0]
27 ldr r1, [r1] 27 ldr r4, =at91_rstc_base
28 ldr r1, [r4]
28 29
29 mov r2, #1 30 mov r2, #1
30 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN 31 mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -37,6 +38,3 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
37 str r4, [r1, #AT91_RSTC_CR] @ reset processor 38 str r4, [r1, #AT91_RSTC_CR] @ reset processor
38 39
39 b . 40 b .
40
41.at91_va_base_sdramc:
42 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 5b12192e52ec..0014573dfe17 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -229,6 +229,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
229 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk), 229 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
230 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk), 230 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
231 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk), 231 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
232 /* more tc lookup table for DT entries */
233 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
234 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
232 /* fake hclk clock */ 235 /* fake hclk clock */
233 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), 236 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
234 CLKDEV_CON_ID("pioA", &pioA_clk), 237 CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -317,12 +320,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
317 } 320 }
318}; 321};
319 322
320static void at91sam9g45_idle(void)
321{
322 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
323 cpu_do_idle();
324}
325
326/* -------------------------------------------------------------------- 323/* --------------------------------------------------------------------
327 * AT91SAM9G45 processor initialization 324 * AT91SAM9G45 processor initialization
328 * -------------------------------------------------------------------- */ 325 * -------------------------------------------------------------------- */
@@ -337,13 +334,16 @@ static void __init at91sam9g45_ioremap_registers(void)
337{ 334{
338 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC); 335 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
339 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC); 336 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
337 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
338 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
340 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT); 339 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
341 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC); 340 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
341 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
342} 342}
343 343
344static void __init at91sam9g45_initialize(void) 344static void __init at91sam9g45_initialize(void)
345{ 345{
346 arm_pm_idle = at91sam9g45_idle; 346 arm_pm_idle = at91sam9_idle;
347 arm_pm_restart = at91sam9g45_restart; 347 arm_pm_restart = at91sam9g45_restart;
348 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); 348 at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
349 349
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index bd4e68cd3e2f..4320b2096789 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -25,6 +25,7 @@
25#include <mach/board.h> 25#include <mach/board.h>
26#include <mach/at91sam9g45.h> 26#include <mach/at91sam9g45.h>
27#include <mach/at91sam9g45_matrix.h> 27#include <mach/at91sam9g45_matrix.h>
28#include <mach/at91_matrix.h>
28#include <mach/at91sam9_smc.h> 29#include <mach/at91sam9_smc.h>
29#include <mach/at_hdmac.h> 30#include <mach/at_hdmac.h>
30#include <mach/atmel-mci.h> 31#include <mach/atmel-mci.h>
@@ -557,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
557 if (!data) 558 if (!data)
558 return; 559 return;
559 560
560 csa = at91_sys_read(AT91_MATRIX_EBICSA); 561 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
561 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); 562 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
562 563
563 /* enable pin */ 564 /* enable pin */
564 if (gpio_is_valid(data->enable_pin)) 565 if (gpio_is_valid(data->enable_pin))
@@ -1051,7 +1052,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1051static struct resource tcb0_resources[] = { 1052static struct resource tcb0_resources[] = {
1052 [0] = { 1053 [0] = {
1053 .start = AT91SAM9G45_BASE_TCB0, 1054 .start = AT91SAM9G45_BASE_TCB0,
1054 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1, 1055 .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1055 .flags = IORESOURCE_MEM, 1056 .flags = IORESOURCE_MEM,
1056 }, 1057 },
1057 [1] = { 1058 [1] = {
@@ -1072,7 +1073,7 @@ static struct platform_device at91sam9g45_tcb0_device = {
1072static struct resource tcb1_resources[] = { 1073static struct resource tcb1_resources[] = {
1073 [0] = { 1074 [0] = {
1074 .start = AT91SAM9G45_BASE_TCB1, 1075 .start = AT91SAM9G45_BASE_TCB1,
1075 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1, 1076 .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1076 .flags = IORESOURCE_MEM, 1077 .flags = IORESOURCE_MEM,
1077 }, 1078 },
1078 [1] = { 1079 [1] = {
@@ -1089,8 +1090,25 @@ static struct platform_device at91sam9g45_tcb1_device = {
1089 .num_resources = ARRAY_SIZE(tcb1_resources), 1090 .num_resources = ARRAY_SIZE(tcb1_resources),
1090}; 1091};
1091 1092
1093#if defined(CONFIG_OF)
1094static struct of_device_id tcb_ids[] = {
1095 { .compatible = "atmel,at91rm9200-tcb" },
1096 { /*sentinel*/ }
1097};
1098#endif
1099
1092static void __init at91_add_device_tc(void) 1100static void __init at91_add_device_tc(void)
1093{ 1101{
1102#if defined(CONFIG_OF)
1103 struct device_node *np;
1104
1105 np = of_find_matching_node(NULL, tcb_ids);
1106 if (np) {
1107 of_node_put(np);
1108 return;
1109 }
1110#endif
1111
1094 platform_device_register(&at91sam9g45_tcb0_device); 1112 platform_device_register(&at91sam9g45_tcb0_device);
1095 platform_device_register(&at91sam9g45_tcb1_device); 1113 platform_device_register(&at91sam9g45_tcb1_device);
1096} 1114}
@@ -1193,6 +1211,8 @@ static struct resource rtt_resources[] = {
1193 .start = AT91SAM9G45_BASE_RTT, 1211 .start = AT91SAM9G45_BASE_RTT,
1194 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1, 1212 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1195 .flags = IORESOURCE_MEM, 1213 .flags = IORESOURCE_MEM,
1214 }, {
1215 .flags = IORESOURCE_MEM,
1196 } 1216 }
1197}; 1217};
1198 1218
@@ -1200,11 +1220,32 @@ static struct platform_device at91sam9g45_rtt_device = {
1200 .name = "at91_rtt", 1220 .name = "at91_rtt",
1201 .id = 0, 1221 .id = 0,
1202 .resource = rtt_resources, 1222 .resource = rtt_resources,
1203 .num_resources = ARRAY_SIZE(rtt_resources),
1204}; 1223};
1205 1224
1225#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1226static void __init at91_add_device_rtt_rtc(void)
1227{
1228 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1229 /*
1230 * The second resource is needed:
1231 * GPBR will serve as the storage for RTC time offset
1232 */
1233 at91sam9g45_rtt_device.num_resources = 2;
1234 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1235 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1236 rtt_resources[1].end = rtt_resources[1].start + 3;
1237}
1238#else
1239static void __init at91_add_device_rtt_rtc(void)
1240{
1241 /* Only one resource is needed: RTT not used as RTC */
1242 at91sam9g45_rtt_device.num_resources = 1;
1243}
1244#endif
1245
1206static void __init at91_add_device_rtt(void) 1246static void __init at91_add_device_rtt(void)
1207{ 1247{
1248 at91_add_device_rtt_rtc();
1208 platform_device_register(&at91sam9g45_rtt_device); 1249 platform_device_register(&at91sam9g45_rtt_device);
1209} 1250}
1210 1251
@@ -1659,7 +1700,6 @@ static inline void configure_usart3_pins(unsigned pins)
1659} 1700}
1660 1701
1661static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1702static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1662struct platform_device *atmel_default_console_device; /* the serial console device */
1663 1703
1664void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1704void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1665{ 1705{
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 0468be10980b..9d457182c86c 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -12,7 +12,7 @@
12 12
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/at91sam9_ddrsdr.h> 15#include <mach/at91_ramc.h>
16#include <mach/at91_rstc.h> 16#include <mach/at91_rstc.h>
17 17
18 .arm 18 .arm
@@ -20,9 +20,10 @@
20 .globl at91sam9g45_restart 20 .globl at91sam9g45_restart
21 21
22at91sam9g45_restart: 22at91sam9g45_restart:
23 ldr r0, .at91_va_base_sdramc0 @ preload constants 23 ldr r5, =at91_ramc_base @ preload constants
24 ldr r1, =at91_rstc_base 24 ldr r0, [r5]
25 ldr r1, [r1] 25 ldr r4, =at91_rstc_base
26 ldr r1, [r4]
26 27
27 mov r2, #1 28 mov r2, #1
28 mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN 29 mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
@@ -35,6 +36,3 @@ at91sam9g45_restart:
35 str r4, [r1, #AT91_RSTC_CR] @ reset processor 36 str r4, [r1, #AT91_RSTC_CR] @ reset processor
36 37
37 b . 38 b .
38
39.at91_va_base_sdramc0:
40 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index fd60e226a987..63d9372eb18e 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -288,19 +288,15 @@ static void __init at91sam9rl_ioremap_registers(void)
288{ 288{
289 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC); 289 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
290 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC); 290 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
291 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
291 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT); 292 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
292 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC); 293 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
293} 294 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
294
295static void at91sam9rl_idle(void)
296{
297 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
298 cpu_do_idle();
299} 295}
300 296
301static void __init at91sam9rl_initialize(void) 297static void __init at91sam9rl_initialize(void)
302{ 298{
303 arm_pm_idle = at91sam9rl_idle; 299 arm_pm_idle = at91sam9_idle;
304 arm_pm_restart = at91sam9_alt_restart; 300 arm_pm_restart = at91sam9_alt_restart;
305 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0); 301 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
306 302
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 9be71c11d0f0..eda72e83037d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -20,6 +20,7 @@
20#include <mach/board.h> 20#include <mach/board.h>
21#include <mach/at91sam9rl.h> 21#include <mach/at91sam9rl.h>
22#include <mach/at91sam9rl_matrix.h> 22#include <mach/at91sam9rl_matrix.h>
23#include <mach/at91_matrix.h>
23#include <mach/at91sam9_smc.h> 24#include <mach/at91sam9_smc.h>
24#include <mach/at_hdmac.h> 25#include <mach/at_hdmac.h>
25 26
@@ -265,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
265 if (!data) 266 if (!data)
266 return; 267 return;
267 268
268 csa = at91_sys_read(AT91_MATRIX_EBICSA); 269 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
269 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 270 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
270 271
271 /* enable pin */ 272 /* enable pin */
272 if (gpio_is_valid(data->enable_pin)) 273 if (gpio_is_valid(data->enable_pin))
@@ -682,6 +683,8 @@ static struct resource rtt_resources[] = {
682 .start = AT91SAM9RL_BASE_RTT, 683 .start = AT91SAM9RL_BASE_RTT,
683 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1, 684 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
684 .flags = IORESOURCE_MEM, 685 .flags = IORESOURCE_MEM,
686 }, {
687 .flags = IORESOURCE_MEM,
685 } 688 }
686}; 689};
687 690
@@ -689,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
689 .name = "at91_rtt", 692 .name = "at91_rtt",
690 .id = 0, 693 .id = 0,
691 .resource = rtt_resources, 694 .resource = rtt_resources,
692 .num_resources = ARRAY_SIZE(rtt_resources),
693}; 695};
694 696
697#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
698static void __init at91_add_device_rtt_rtc(void)
699{
700 at91sam9rl_rtt_device.name = "rtc-at91sam9";
701 /*
702 * The second resource is needed:
703 * GPBR will serve as the storage for RTC time offset
704 */
705 at91sam9rl_rtt_device.num_resources = 2;
706 rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
707 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
708 rtt_resources[1].end = rtt_resources[1].start + 3;
709}
710#else
711static void __init at91_add_device_rtt_rtc(void)
712{
713 /* Only one resource is needed: RTT not used as RTC */
714 at91sam9rl_rtt_device.num_resources = 1;
715}
716#endif
717
695static void __init at91_add_device_rtt(void) 718static void __init at91_add_device_rtt(void)
696{ 719{
720 at91_add_device_rtt_rtc();
697 platform_device_register(&at91sam9rl_rtt_device); 721 platform_device_register(&at91sam9rl_rtt_device);
698} 722}
699 723
@@ -1128,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
1128} 1152}
1129 1153
1130static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ 1154static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1131struct platform_device *atmel_default_console_device; /* the serial console device */
1132 1155
1133void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) 1156void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1134{ 1157{
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 1c3444d2ee0c..a34d96afa746 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -301,8 +301,7 @@ static void __init at91sam9x5_map_io(void)
301 301
302static void __init at91sam9x5_ioremap_registers(void) 302static void __init at91sam9x5_ioremap_registers(void)
303{ 303{
304 if (of_at91sam926x_pit_init() < 0) 304 at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
305 panic("Impossible to find PIT\n");
306} 305}
307 306
308void __init at91sam9x5_initialize(void) 307void __init at91sam9x5_initialize(void)
@@ -317,10 +316,6 @@ void __init at91sam9x5_initialize(void)
317/* -------------------------------------------------------------------- 316/* --------------------------------------------------------------------
318 * AT91SAM9x5 devices (temporary before modification of code) 317 * AT91SAM9x5 devices (temporary before modification of code)
319 * -------------------------------------------------------------------- */ 318 * -------------------------------------------------------------------- */
320void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
321void __init at91_set_serial_console(unsigned portnr) {}
322struct platform_device *atmel_default_console_device = NULL;
323
324void __init at91_add_device_nand(struct atmel_nand_data *data) {} 319void __init at91_add_device_nand(struct atmel_nand_data *data) {}
325 320
326/* -------------------------------------------------------------------- 321/* --------------------------------------------------------------------
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 0154b7f44ff1..5400a1d65035 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -44,7 +44,7 @@ static void at91x40_idle(void)
44 * Disable the processor clock. The processor will be automatically 44 * Disable the processor clock. The processor will be automatically
45 * re-enabled by an interrupt or by a reset. 45 * re-enabled by an interrupt or by a reset.
46 */ 46 */
47 at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU); 47 __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
48 cpu_do_idle(); 48 cpu_do_idle();
49} 49}
50 50
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index dfff2895f4b2..6ca680a1d5d1 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -28,6 +28,12 @@
28#include <asm/mach/time.h> 28#include <asm/mach/time.h>
29#include <mach/at91_tc.h> 29#include <mach/at91_tc.h>
30 30
31#define at91_tc_read(field) \
32 __raw_readl(AT91_TC + field)
33
34#define at91_tc_write(field, value) \
35 __raw_writel(value, AT91_TC + field);
36
31/* 37/*
32 * 3 counter/timer units present. 38 * 3 counter/timer units present.
33 */ 39 */
@@ -37,12 +43,12 @@
37 43
38static unsigned long at91x40_gettimeoffset(void) 44static unsigned long at91x40_gettimeoffset(void)
39{ 45{
40 return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128)); 46 return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
41} 47}
42 48
43static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id) 49static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
44{ 50{
45 at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR); 51 at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
46 timer_tick(); 52 timer_tick();
47 return IRQ_HANDLED; 53 return IRQ_HANDLED;
48} 54}
@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
57{ 63{
58 unsigned int v; 64 unsigned int v;
59 65
60 at91_sys_write(AT91_TC + AT91_TC_BCR, 0); 66 at91_tc_write(AT91_TC_BCR, 0);
61 v = at91_sys_read(AT91_TC + AT91_TC_BMR); 67 v = at91_tc_read(AT91_TC_BMR);
62 v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE; 68 v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
63 at91_sys_write(AT91_TC + AT91_TC_BMR, v); 69 at91_tc_write(AT91_TC_BMR, v);
64 70
65 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS); 71 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
66 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG)); 72 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
67 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff); 73 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
68 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1); 74 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
69 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4)); 75 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
70 76
71 setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq); 77 setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
72 78
73 at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN)); 79 at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
74} 80}
75 81
76struct sys_timer at91x40_timer = { 82struct sys_timer at91x40_timer = {
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 9ab3d1ea326d..989e1c5a9ca0 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -43,6 +43,7 @@
43#include <mach/board.h> 43#include <mach/board.h>
44#include <mach/at91sam9_smc.h> 44#include <mach/at91sam9_smc.h>
45#include <mach/at91sam9260_matrix.h> 45#include <mach/at91sam9260_matrix.h>
46#include <mach/at91_matrix.h>
46 47
47#include "sam9_smc.h" 48#include "sam9_smc.h"
48#include "generic.h" 49#include "generic.h"
@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
238{ 239{
239 unsigned long csa; 240 unsigned long csa;
240 241
241 csa = at91_sys_read(AT91_MATRIX_EBICSA); 242 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
242 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V); 243 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
243 244
244 /* configure chip-select 0 (NOR) */ 245 /* configure chip-select 0 (NOR) */
245 sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config); 246 sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 368e1427ad99..e094cc81fe25 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -38,6 +38,7 @@
38 38
39#include <mach/board.h> 39#include <mach/board.h>
40#include <mach/at91rm9200_mc.h> 40#include <mach/at91rm9200_mc.h>
41#include <mach/at91_ramc.h>
41#include <mach/cpu.h> 42#include <mach/cpu.h>
42 43
43#include "generic.h" 44#include "generic.h"
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index 05793156d178..583b72472ad9 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -15,7 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/irqdomain.h> 18#include <linux/of.h>
19#include <linux/of_irq.h> 19#include <linux/of_irq.h>
20#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21 21
@@ -38,12 +38,6 @@ static void __init ek_init_early(void)
38{ 38{
39 /* Initialize processor: 12.000 MHz crystal */ 39 /* Initialize processor: 12.000 MHz crystal */
40 at91_initialize(12000000); 40 at91_initialize(12000000);
41
42 /* DGBU on ttyS0. (Rx & Tx only) */
43 at91_register_uart(0, 0, 0);
44
45 /* set serial console to ttyS0 (ie, DBGU) */
46 at91_set_serial_console(0);
47} 41}
48 42
49/* det_pin is not connected */ 43/* det_pin is not connected */
@@ -88,15 +82,17 @@ static void __init ek_add_device_nand(void)
88 at91_add_device_nand(&ek_nand_data); 82 at91_add_device_nand(&ek_nand_data);
89} 83}
90 84
91static const struct of_device_id aic_of_match[] __initconst = { 85static const struct of_device_id irq_of_match[] __initconst = {
92 { .compatible = "atmel,at91rm9200-aic", }, 86
93 {}, 87 { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
88 { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
89 { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
90 { /*sentinel*/ }
94}; 91};
95 92
96static void __init at91_dt_init_irq(void) 93static void __init at91_dt_init_irq(void)
97{ 94{
98 irq_domain_generate_simple(aic_of_match, 0xfffff000, 0); 95 of_irq_init(irq_of_match);
99 at91_init_irq_default();
100} 96}
101 97
102static void __init at91_dt_device_init(void) 98static void __init at91_dt_device_init(void)
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 07ef35b0ec2c..f23aabef8551 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -26,6 +26,7 @@
26 26
27#include <mach/board.h> 27#include <mach/board.h>
28#include <mach/at91rm9200_mc.h> 28#include <mach/at91rm9200_mc.h>
29#include <mach/at91_ramc.h>
29#include <mach/cpu.h> 30#include <mach/cpu.h>
30 31
31#include "generic.h" 32#include "generic.h"
@@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
110 at91_add_device_mmc(0, &eco920_mmc_data); 111 at91_add_device_mmc(0, &eco920_mmc_data);
111 platform_device_register(&eco920_flash); 112 platform_device_register(&eco920_flash);
112 113
113 at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1) 114 at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
114 | AT91_SMC_RWSETUP_(1) 115 | AT91_SMC_RWSETUP_(1)
115 | AT91_SMC_DBW_8 116 | AT91_SMC_DBW_8
116 | AT91_SMC_WSEN 117 | AT91_SMC_WSEN
@@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
122 at91_set_deglitch(AT91_PIN_PA23, 1); 123 at91_set_deglitch(AT91_PIN_PA23, 1);
123 124
124/* Initialization of the Static Memory Controller for Chip Select 3 */ 125/* Initialization of the Static Memory Controller for Chip Select 3 */
125 at91_sys_write(AT91_SMC_CSR(3), 126 at91_ramc_write(0, AT91_SMC_CSR(3),
126 AT91_SMC_DBW_16 | /* 16 bit */ 127 AT91_SMC_DBW_16 | /* 16 bit */
127 AT91_SMC_WSEN | 128 AT91_SMC_WSEN |
128 AT91_SMC_NWS_(5) | /* wait states */ 129 AT91_SMC_NWS_(5) | /* wait states */
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index d75a4a2ad9c2..bb9914582013 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -38,6 +38,7 @@
38#include <mach/board.h> 38#include <mach/board.h>
39#include <mach/cpu.h> 39#include <mach/cpu.h>
40#include <mach/at91rm9200_mc.h> 40#include <mach/at91rm9200_mc.h>
41#include <mach/at91_ramc.h>
41 42
42#include "generic.h" 43#include "generic.h"
43 44
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab024fa11d5c..59e35dd14863 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -39,6 +39,7 @@
39 39
40#include <mach/board.h> 40#include <mach/board.h>
41#include <mach/at91rm9200_mc.h> 41#include <mach/at91rm9200_mc.h>
42#include <mach/at91_ramc.h>
42 43
43#include "generic.h" 44#include "generic.h"
44 45
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 782f37946af5..9083df04e7ed 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -41,6 +41,7 @@
41#include <mach/hardware.h> 41#include <mach/hardware.h>
42#include <mach/board.h> 42#include <mach/board.h>
43#include <mach/at91rm9200_mc.h> 43#include <mach/at91rm9200_mc.h>
44#include <mach/at91_ramc.h>
44 45
45#include "generic.h" 46#include "generic.h"
46 47
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index ef7c12a92246..11cbaa8946fe 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -41,6 +41,7 @@
41#include <mach/hardware.h> 41#include <mach/hardware.h>
42#include <mach/board.h> 42#include <mach/board.h>
43#include <mach/at91rm9200_mc.h> 43#include <mach/at91rm9200_mc.h>
44#include <mach/at91_ramc.h>
44 45
45#include "generic.h" 46#include "generic.h"
46 47
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 4770db08e5a6..3c2e3fcc310c 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -145,11 +145,11 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
145 /* Audio codec */ 145 /* Audio codec */
146 I2C_BOARD_INFO("tlv320aic23", 0x1a), 146 I2C_BOARD_INFO("tlv320aic23", 0x1a),
147 }, 147 },
148 { 148};
149
150static struct i2c_board_info __initdata snapper9260_i2c_isl1208 = {
149 /* RTC */ 151 /* RTC */
150 I2C_BOARD_INFO("isl1208", 0x6f), 152 I2C_BOARD_INFO("isl1208", 0x6f),
151 .irq = gpio_to_irq(AT91_PIN_PA31),
152 },
153}; 153};
154 154
155static void __init snapper9260_add_device_nand(void) 155static void __init snapper9260_add_device_nand(void)
@@ -163,6 +163,10 @@ static void __init snapper9260_board_init(void)
163{ 163{
164 at91_add_device_i2c(snapper9260_i2c_devices, 164 at91_add_device_i2c(snapper9260_i2c_devices,
165 ARRAY_SIZE(snapper9260_i2c_devices)); 165 ARRAY_SIZE(snapper9260_i2c_devices));
166
167 snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
168 i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
169
166 at91_add_device_serial(); 170 at91_add_device_serial();
167 at91_add_device_usbh(&snapper9260_usbh_data); 171 at91_add_device_usbh(&snapper9260_usbh_data);
168 at91_add_device_udc(&snapper9260_udc_data); 172 at91_add_device_udc(&snapper9260_udc_data);
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index bbd553e1cd93..52f460768f71 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -45,6 +45,7 @@
45#include <mach/hardware.h> 45#include <mach/hardware.h>
46#include <mach/board.h> 46#include <mach/board.h>
47#include <mach/at91rm9200_mc.h> 47#include <mach/at91rm9200_mc.h>
48#include <mach/at91_ramc.h>
48#include <mach/cpu.h> 49#include <mach/cpu.h>
49 50
50#include "generic.h" 51#include "generic.h"
@@ -393,7 +394,7 @@ static void yl9200_init_video(void)
393 at91_set_A_periph(AT91_PIN_PC6, 0); 394 at91_set_A_periph(AT91_PIN_PC6, 0);
394 395
395 /* Initialization of the Static Memory Controller for Chip Select 2 */ 396 /* Initialization of the Static Memory Controller for Chip Select 2 */
396 at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */ 397 at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
397 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */ 398 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
398 | AT91_SMC_TDF_(0x100) /* float time */ 399 | AT91_SMC_TDF_(0x100) /* float time */
399 ); 400 );
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a5291e0e7004..be51ca7f694d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -28,9 +28,12 @@
28#include <mach/at91_pmc.h> 28#include <mach/at91_pmc.h>
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30 30
31#include <asm/proc-fns.h>
32
31#include "clock.h" 33#include "clock.h"
32#include "generic.h" 34#include "generic.h"
33 35
36void __iomem *at91_pmc_base;
34 37
35/* 38/*
36 * There's a lot more which can be done with clocks, including cpufreq 39 * There's a lot more which can be done with clocks, including cpufreq
@@ -123,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
123 value = 0; 126 value = 0;
124 127
125 // REVISIT: Add work-around for AT91RM9200 Errata #26 ? 128 // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
126 at91_sys_write(AT91_CKGR_PLLBR, value); 129 at91_pmc_write(AT91_CKGR_PLLBR, value);
127 130
128 do { 131 do {
129 cpu_relax(); 132 cpu_relax();
130 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); 133 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
131} 134}
132 135
133static struct clk pllb = { 136static struct clk pllb = {
@@ -142,24 +145,24 @@ static struct clk pllb = {
142static void pmc_sys_mode(struct clk *clk, int is_on) 145static void pmc_sys_mode(struct clk *clk, int is_on)
143{ 146{
144 if (is_on) 147 if (is_on)
145 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask); 148 at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
146 else 149 else
147 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); 150 at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
148} 151}
149 152
150static void pmc_uckr_mode(struct clk *clk, int is_on) 153static void pmc_uckr_mode(struct clk *clk, int is_on)
151{ 154{
152 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); 155 unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
153 156
154 if (is_on) { 157 if (is_on) {
155 is_on = AT91_PMC_LOCKU; 158 is_on = AT91_PMC_LOCKU;
156 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); 159 at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
157 } else 160 } else
158 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); 161 at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
159 162
160 do { 163 do {
161 cpu_relax(); 164 cpu_relax();
162 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); 165 } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
163} 166}
164 167
165/* USB function clocks (PLLB must be 48 MHz) */ 168/* USB function clocks (PLLB must be 48 MHz) */
@@ -195,9 +198,9 @@ struct clk mck = {
195static void pmc_periph_mode(struct clk *clk, int is_on) 198static void pmc_periph_mode(struct clk *clk, int is_on)
196{ 199{
197 if (is_on) 200 if (is_on)
198 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask); 201 at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
199 else 202 else
200 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask); 203 at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
201} 204}
202 205
203static struct clk __init *at91_css_to_clk(unsigned long css) 206static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -357,10 +360,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
357 if (actual && actual <= rate) { 360 if (actual && actual <= rate) {
358 u32 pckr; 361 u32 pckr;
359 362
360 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); 363 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
361 pckr &= css_mask; /* keep clock selection */ 364 pckr &= css_mask; /* keep clock selection */
362 pckr |= prescale << prescale_offset; 365 pckr |= prescale << prescale_offset;
363 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr); 366 at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
364 clk->rate_hz = actual; 367 clk->rate_hz = actual;
365 break; 368 break;
366 } 369 }
@@ -394,7 +397,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
394 397
395 clk->rate_hz = parent->rate_hz; 398 clk->rate_hz = parent->rate_hz;
396 clk->parent = parent; 399 clk->parent = parent;
397 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id); 400 at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
398 401
399 spin_unlock_irqrestore(&clk_lock, flags); 402 spin_unlock_irqrestore(&clk_lock, flags);
400 return 0; 403 return 0;
@@ -413,7 +416,7 @@ static void __init init_programmable_clock(struct clk *clk)
413 else 416 else
414 css_mask = AT91_PMC_CSS; 417 css_mask = AT91_PMC_CSS;
415 418
416 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id)); 419 pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
417 parent = at91_css_to_clk(pckr & css_mask); 420 parent = at91_css_to_clk(pckr & css_mask);
418 clk->parent = parent; 421 clk->parent = parent;
419 clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); 422 clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
@@ -430,19 +433,24 @@ static int at91_clk_show(struct seq_file *s, void *unused)
430 u32 scsr, pcsr, uckr = 0, sr; 433 u32 scsr, pcsr, uckr = 0, sr;
431 struct clk *clk; 434 struct clk *clk;
432 435
433 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); 436 scsr = at91_pmc_read(AT91_PMC_SCSR);
434 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR)); 437 pcsr = at91_pmc_read(AT91_PMC_PCSR);
435 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); 438 sr = at91_pmc_read(AT91_PMC_SR);
436 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); 439 seq_printf(s, "SCSR = %8x\n", scsr);
437 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); 440 seq_printf(s, "PCSR = %8x\n", pcsr);
441 seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
442 seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
443 seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
438 if (cpu_has_pllb()) 444 if (cpu_has_pllb())
439 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); 445 seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
440 if (cpu_has_utmi()) 446 if (cpu_has_utmi()) {
441 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR)); 447 uckr = at91_pmc_read(AT91_CKGR_UCKR);
442 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); 448 seq_printf(s, "UCKR = %8x\n", uckr);
449 }
450 seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
443 if (cpu_has_upll()) 451 if (cpu_has_upll())
444 seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB)); 452 seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
445 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); 453 seq_printf(s, "SR = %8x\n", sr);
446 454
447 seq_printf(s, "\n"); 455 seq_printf(s, "\n");
448 456
@@ -630,14 +638,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
630 if (cpu_is_at91rm9200()) { 638 if (cpu_is_at91rm9200()) {
631 uhpck.pmc_mask = AT91RM9200_PMC_UHP; 639 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
632 udpck.pmc_mask = AT91RM9200_PMC_UDP; 640 udpck.pmc_mask = AT91RM9200_PMC_UDP;
633 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); 641 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
634 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || 642 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
635 cpu_is_at91sam9263() || cpu_is_at91sam9g20() || 643 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
636 cpu_is_at91sam9g10()) { 644 cpu_is_at91sam9g10()) {
637 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 645 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
638 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 646 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
639 } 647 }
640 at91_sys_write(AT91_CKGR_PLLBR, 0); 648 at91_pmc_write(AT91_CKGR_PLLBR, 0);
641 649
642 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 650 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
643 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 651 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
@@ -654,13 +662,13 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
654 /* Setup divider by 10 to reach 48 MHz */ 662 /* Setup divider by 10 to reach 48 MHz */
655 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; 663 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
656 664
657 at91_sys_write(AT91_PMC_USB, usbr); 665 at91_pmc_write(AT91_PMC_USB, usbr);
658 666
659 /* Now set uhpck values */ 667 /* Now set uhpck values */
660 uhpck.parent = &utmi_clk; 668 uhpck.parent = &utmi_clk;
661 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 669 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
662 uhpck.rate_hz = utmi_clk.rate_hz; 670 uhpck.rate_hz = utmi_clk.rate_hz;
663 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); 671 uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
664} 672}
665 673
666int __init at91_clock_init(unsigned long main_clock) 674int __init at91_clock_init(unsigned long main_clock)
@@ -669,6 +677,10 @@ int __init at91_clock_init(unsigned long main_clock)
669 int i; 677 int i;
670 int pll_overclock = false; 678 int pll_overclock = false;
671 679
680 at91_pmc_base = ioremap(AT91_PMC, 256);
681 if (!at91_pmc_base)
682 panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
683
672 /* 684 /*
673 * When the bootloader initialized the main oscillator correctly, 685 * When the bootloader initialized the main oscillator correctly,
674 * there's no problem using the cycle counter. But if it didn't, 686 * there's no problem using the cycle counter. But if it didn't,
@@ -677,14 +689,14 @@ int __init at91_clock_init(unsigned long main_clock)
677 */ 689 */
678 if (!main_clock) { 690 if (!main_clock) {
679 do { 691 do {
680 tmp = at91_sys_read(AT91_CKGR_MCFR); 692 tmp = at91_pmc_read(AT91_CKGR_MCFR);
681 } while (!(tmp & AT91_PMC_MAINRDY)); 693 } while (!(tmp & AT91_PMC_MAINRDY));
682 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); 694 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
683 } 695 }
684 main_clk.rate_hz = main_clock; 696 main_clk.rate_hz = main_clock;
685 697
686 /* report if PLLA is more than mildly overclocked */ 698 /* report if PLLA is more than mildly overclocked */
687 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); 699 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
688 if (cpu_has_300M_plla()) { 700 if (cpu_has_300M_plla()) {
689 if (plla.rate_hz > 300000000) 701 if (plla.rate_hz > 300000000)
690 pll_overclock = true; 702 pll_overclock = true;
@@ -699,7 +711,7 @@ int __init at91_clock_init(unsigned long main_clock)
699 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); 711 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
700 712
701 if (cpu_has_plladiv2()) { 713 if (cpu_has_plladiv2()) {
702 mckr = at91_sys_read(AT91_PMC_MCKR); 714 mckr = at91_pmc_read(AT91_PMC_MCKR);
703 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ 715 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
704 } 716 }
705 717
@@ -739,7 +751,7 @@ int __init at91_clock_init(unsigned long main_clock)
739 * MCK and CPU derive from one of those primary clocks. 751 * MCK and CPU derive from one of those primary clocks.
740 * For now, assume this parentage won't change. 752 * For now, assume this parentage won't change.
741 */ 753 */
742 mckr = at91_sys_read(AT91_PMC_MCKR); 754 mckr = at91_pmc_read(AT91_PMC_MCKR);
743 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); 755 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
744 freq = mck.parent->rate_hz; 756 freq = mck.parent->rate_hz;
745 freq /= pmc_prescaler_divider(mckr); /* prescale */ 757 freq /= pmc_prescaler_divider(mckr); /* prescale */
@@ -812,9 +824,15 @@ static int __init at91_clock_reset(void)
812 pr_debug("Clocks: disable unused %s\n", clk->name); 824 pr_debug("Clocks: disable unused %s\n", clk->name);
813 } 825 }
814 826
815 at91_sys_write(AT91_PMC_PCDR, pcdr); 827 at91_pmc_write(AT91_PMC_PCDR, pcdr);
816 at91_sys_write(AT91_PMC_SCDR, scdr); 828 at91_pmc_write(AT91_PMC_SCDR, scdr);
817 829
818 return 0; 830 return 0;
819} 831}
820late_initcall(at91_clock_reset); 832late_initcall(at91_clock_reset);
833
834void at91sam9_idle(void)
835{
836 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
837 cpu_do_idle();
838}
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 7e8280e798c1..459f01a4a546 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -9,6 +9,7 @@
9 */ 9 */
10 10
11#include <linux/clkdev.h> 11#include <linux/clkdev.h>
12#include <linux/of.h>
12 13
13 /* Map io */ 14 /* Map io */
14extern void __init at91_map_io(void); 15extern void __init at91_map_io(void);
@@ -25,9 +26,13 @@ extern void __init at91_init_irq_default(void);
25extern void __init at91_init_interrupts(unsigned int priority[]); 26extern void __init at91_init_interrupts(unsigned int priority[]);
26extern void __init at91x40_init_interrupts(unsigned int priority[]); 27extern void __init at91x40_init_interrupts(unsigned int priority[]);
27extern void __init at91_aic_init(unsigned int priority[]); 28extern void __init at91_aic_init(unsigned int priority[]);
29extern int __init at91_aic_of_init(struct device_node *node,
30 struct device_node *parent);
31
28 32
29 /* Timer */ 33 /* Timer */
30struct sys_timer; 34struct sys_timer;
35extern void at91rm9200_ioremap_st(u32 addr);
31extern struct sys_timer at91rm9200_timer; 36extern struct sys_timer at91rm9200_timer;
32extern void at91sam926x_ioremap_pit(u32 addr); 37extern void at91sam926x_ioremap_pit(u32 addr);
33extern struct sys_timer at91sam926x_timer; 38extern struct sys_timer at91sam926x_timer;
@@ -56,6 +61,9 @@ struct device;
56extern void at91_irq_suspend(void); 61extern void at91_irq_suspend(void);
57extern void at91_irq_resume(void); 62extern void at91_irq_resume(void);
58 63
64/* idle */
65extern void at91sam9_idle(void);
66
59/* reset */ 67/* reset */
60extern void at91_ioremap_rstc(u32 base_addr); 68extern void at91_ioremap_rstc(u32 base_addr);
61extern void at91sam9_alt_restart(char, const char *); 69extern void at91sam9_alt_restart(char, const char *);
@@ -64,6 +72,12 @@ extern void at91sam9g45_restart(char, const char *);
64/* shutdown */ 72/* shutdown */
65extern void at91_ioremap_shdwc(u32 base_addr); 73extern void at91_ioremap_shdwc(u32 base_addr);
66 74
75/* Matrix */
76extern void at91_ioremap_matrix(u32 base_addr);
77
78/* Ram Controler */
79extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
80
67 /* GPIO */ 81 /* GPIO */
68#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */ 82#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
69#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ 83#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
@@ -74,5 +88,7 @@ struct at91_gpio_bank {
74}; 88};
75extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks); 89extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
76extern void __init at91_gpio_irq_setup(void); 90extern void __init at91_gpio_irq_setup(void);
91extern int __init at91_gpio_of_irq_setup(struct device_node *node,
92 struct device_node *parent);
77 93
78extern int at91_extern_irq; 94extern int at91_extern_irq;
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 74d6783eeabb..325837a264c9 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -11,6 +11,7 @@
11 11
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/device.h>
14#include <linux/gpio.h> 15#include <linux/gpio.h>
15#include <linux/interrupt.h> 16#include <linux/interrupt.h>
16#include <linux/irq.h> 17#include <linux/irq.h>
@@ -20,6 +21,10 @@
20#include <linux/list.h> 21#include <linux/list.h>
21#include <linux/module.h> 22#include <linux/module.h>
22#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/irqdomain.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_gpio.h>
23 28
24#include <mach/hardware.h> 29#include <mach/hardware.h>
25#include <mach/at91_pio.h> 30#include <mach/at91_pio.h>
@@ -29,9 +34,12 @@
29struct at91_gpio_chip { 34struct at91_gpio_chip {
30 struct gpio_chip chip; 35 struct gpio_chip chip;
31 struct at91_gpio_chip *next; /* Bank sharing same clock */ 36 struct at91_gpio_chip *next; /* Bank sharing same clock */
32 int id; /* ID of register bank */ 37 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
33 void __iomem *regbase; /* Base of register bank */ 38 int pioc_virq; /* PIO bank Linux virtual interrupt */
39 int pioc_idx; /* PIO bank index */
40 void __iomem *regbase; /* PIO bank virtual address */
34 struct clk *clock; /* associated clock */ 41 struct clk *clock; /* associated clock */
42 struct irq_domain *domain; /* associated irq domain */
35}; 43};
36 44
37#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 45#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
@@ -43,8 +51,9 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip,
43 unsigned offset, int val); 51 unsigned offset, int val);
44static int at91_gpiolib_direction_input(struct gpio_chip *chip, 52static int at91_gpiolib_direction_input(struct gpio_chip *chip,
45 unsigned offset); 53 unsigned offset);
54static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
46 55
47#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ 56#define AT91_GPIO_CHIP(name, nr_gpio) \
48 { \ 57 { \
49 .chip = { \ 58 .chip = { \
50 .label = name, \ 59 .label = name, \
@@ -53,20 +62,28 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
53 .get = at91_gpiolib_get, \ 62 .get = at91_gpiolib_get, \
54 .set = at91_gpiolib_set, \ 63 .set = at91_gpiolib_set, \
55 .dbg_show = at91_gpiolib_dbg_show, \ 64 .dbg_show = at91_gpiolib_dbg_show, \
56 .base = base_gpio, \ 65 .to_irq = at91_gpiolib_to_irq, \
57 .ngpio = nr_gpio, \ 66 .ngpio = nr_gpio, \
58 }, \ 67 }, \
59 } 68 }
60 69
61static struct at91_gpio_chip gpio_chip[] = { 70static struct at91_gpio_chip gpio_chip[] = {
62 AT91_GPIO_CHIP("pioA", 0x00, 32), 71 AT91_GPIO_CHIP("pioA", 32),
63 AT91_GPIO_CHIP("pioB", 0x20, 32), 72 AT91_GPIO_CHIP("pioB", 32),
64 AT91_GPIO_CHIP("pioC", 0x40, 32), 73 AT91_GPIO_CHIP("pioC", 32),
65 AT91_GPIO_CHIP("pioD", 0x60, 32), 74 AT91_GPIO_CHIP("pioD", 32),
66 AT91_GPIO_CHIP("pioE", 0x80, 32), 75 AT91_GPIO_CHIP("pioE", 32),
67}; 76};
68 77
69static int gpio_banks; 78static int gpio_banks;
79static unsigned long at91_gpio_caps;
80
81/* All PIO controllers support PIO3 features */
82#define AT91_GPIO_CAP_PIO3 (1 << 0)
83
84#define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
85
86/*--------------------------------------------------------------------------*/
70 87
71static inline void __iomem *pin_to_controller(unsigned pin) 88static inline void __iomem *pin_to_controller(unsigned pin)
72{ 89{
@@ -83,6 +100,25 @@ static inline unsigned pin_to_mask(unsigned pin)
83} 100}
84 101
85 102
103static char peripheral_function(void __iomem *pio, unsigned mask)
104{
105 char ret = 'X';
106 u8 select;
107
108 if (pio) {
109 if (has_pio3()) {
110 select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
111 select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
112 ret = 'A' + select;
113 } else {
114 ret = __raw_readl(pio + PIO_ABSR) & mask ?
115 'B' : 'A';
116 }
117 }
118
119 return ret;
120}
121
86/*--------------------------------------------------------------------------*/ 122/*--------------------------------------------------------------------------*/
87 123
88/* Not all hardware capabilities are exposed through these calls; they 124/* Not all hardware capabilities are exposed through these calls; they
@@ -130,7 +166,14 @@ int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
130 166
131 __raw_writel(mask, pio + PIO_IDR); 167 __raw_writel(mask, pio + PIO_IDR);
132 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 168 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
133 __raw_writel(mask, pio + PIO_ASR); 169 if (has_pio3()) {
170 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
171 pio + PIO_ABCDSR1);
172 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
173 pio + PIO_ABCDSR2);
174 } else {
175 __raw_writel(mask, pio + PIO_ASR);
176 }
134 __raw_writel(mask, pio + PIO_PDR); 177 __raw_writel(mask, pio + PIO_PDR);
135 return 0; 178 return 0;
136} 179}
@@ -150,7 +193,14 @@ int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
150 193
151 __raw_writel(mask, pio + PIO_IDR); 194 __raw_writel(mask, pio + PIO_IDR);
152 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 195 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
153 __raw_writel(mask, pio + PIO_BSR); 196 if (has_pio3()) {
197 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
198 pio + PIO_ABCDSR1);
199 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
200 pio + PIO_ABCDSR2);
201 } else {
202 __raw_writel(mask, pio + PIO_BSR);
203 }
154 __raw_writel(mask, pio + PIO_PDR); 204 __raw_writel(mask, pio + PIO_PDR);
155 return 0; 205 return 0;
156} 206}
@@ -158,8 +208,50 @@ EXPORT_SYMBOL(at91_set_B_periph);
158 208
159 209
160/* 210/*
161 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and 211 * mux the pin to the "C" internal peripheral role.
162 * configure it for an input. 212 */
213int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
214{
215 void __iomem *pio = pin_to_controller(pin);
216 unsigned mask = pin_to_mask(pin);
217
218 if (!pio || !has_pio3())
219 return -EINVAL;
220
221 __raw_writel(mask, pio + PIO_IDR);
222 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
223 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
224 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
225 __raw_writel(mask, pio + PIO_PDR);
226 return 0;
227}
228EXPORT_SYMBOL(at91_set_C_periph);
229
230
231/*
232 * mux the pin to the "D" internal peripheral role.
233 */
234int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
235{
236 void __iomem *pio = pin_to_controller(pin);
237 unsigned mask = pin_to_mask(pin);
238
239 if (!pio || !has_pio3())
240 return -EINVAL;
241
242 __raw_writel(mask, pio + PIO_IDR);
243 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
244 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
245 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
246 __raw_writel(mask, pio + PIO_PDR);
247 return 0;
248}
249EXPORT_SYMBOL(at91_set_D_periph);
250
251
252/*
253 * mux the pin to the gpio controller (instead of "A", "B", "C"
254 * or "D" peripheral), and configure it for an input.
163 */ 255 */
164int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) 256int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
165{ 257{
@@ -179,8 +271,8 @@ EXPORT_SYMBOL(at91_set_gpio_input);
179 271
180 272
181/* 273/*
182 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), 274 * mux the pin to the gpio controller (instead of "A", "B", "C"
183 * and configure it for an output. 275 * or "D" peripheral), and configure it for an output.
184 */ 276 */
185int __init_or_module at91_set_gpio_output(unsigned pin, int value) 277int __init_or_module at91_set_gpio_output(unsigned pin, int value)
186{ 278{
@@ -210,12 +302,37 @@ int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
210 302
211 if (!pio) 303 if (!pio)
212 return -EINVAL; 304 return -EINVAL;
305
306 if (has_pio3() && is_on)
307 __raw_writel(mask, pio + PIO_IFSCDR);
213 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 308 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
214 return 0; 309 return 0;
215} 310}
216EXPORT_SYMBOL(at91_set_deglitch); 311EXPORT_SYMBOL(at91_set_deglitch);
217 312
218/* 313/*
314 * enable/disable the debounce filter;
315 */
316int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
317{
318 void __iomem *pio = pin_to_controller(pin);
319 unsigned mask = pin_to_mask(pin);
320
321 if (!pio || !has_pio3())
322 return -EINVAL;
323
324 if (is_on) {
325 __raw_writel(mask, pio + PIO_IFSCER);
326 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
327 __raw_writel(mask, pio + PIO_IFER);
328 } else {
329 __raw_writel(mask, pio + PIO_IFDR);
330 }
331 return 0;
332}
333EXPORT_SYMBOL(at91_set_debounce);
334
335/*
219 * enable/disable the multi-driver; This is only valid for output and 336 * enable/disable the multi-driver; This is only valid for output and
220 * allows the output pin to run as an open collector output. 337 * allows the output pin to run as an open collector output.
221 */ 338 */
@@ -233,6 +350,41 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
233EXPORT_SYMBOL(at91_set_multi_drive); 350EXPORT_SYMBOL(at91_set_multi_drive);
234 351
235/* 352/*
353 * enable/disable the pull-down.
354 * If pull-up already enabled while calling the function, we disable it.
355 */
356int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
357{
358 void __iomem *pio = pin_to_controller(pin);
359 unsigned mask = pin_to_mask(pin);
360
361 if (!pio || !has_pio3())
362 return -EINVAL;
363
364 /* Disable pull-up anyway */
365 __raw_writel(mask, pio + PIO_PUDR);
366 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
367 return 0;
368}
369EXPORT_SYMBOL(at91_set_pulldown);
370
371/*
372 * disable Schmitt trigger
373 */
374int __init_or_module at91_disable_schmitt_trig(unsigned pin)
375{
376 void __iomem *pio = pin_to_controller(pin);
377 unsigned mask = pin_to_mask(pin);
378
379 if (!pio || !has_pio3())
380 return -EINVAL;
381
382 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
383 return 0;
384}
385EXPORT_SYMBOL(at91_disable_schmitt_trig);
386
387/*
236 * assuming the pin is muxed as a gpio output, set its value. 388 * assuming the pin is muxed as a gpio output, set its value.
237 */ 389 */
238int at91_set_gpio_value(unsigned pin, int value) 390int at91_set_gpio_value(unsigned pin, int value)
@@ -273,9 +425,9 @@ static u32 backups[MAX_GPIO_BANKS];
273 425
274static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 426static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
275{ 427{
276 unsigned pin = irq_to_gpio(d->irq); 428 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
277 unsigned mask = pin_to_mask(pin); 429 unsigned mask = 1 << d->hwirq;
278 unsigned bank = pin / 32; 430 unsigned bank = at91_gpio->pioc_idx;
279 431
280 if (unlikely(bank >= MAX_GPIO_BANKS)) 432 if (unlikely(bank >= MAX_GPIO_BANKS))
281 return -EINVAL; 433 return -EINVAL;
@@ -285,7 +437,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
285 else 437 else
286 wakeups[bank] &= ~mask; 438 wakeups[bank] &= ~mask;
287 439
288 irq_set_irq_wake(gpio_chip[bank].id, state); 440 irq_set_irq_wake(at91_gpio->pioc_virq, state);
289 441
290 return 0; 442 return 0;
291} 443}
@@ -301,9 +453,10 @@ void at91_gpio_suspend(void)
301 __raw_writel(backups[i], pio + PIO_IDR); 453 __raw_writel(backups[i], pio + PIO_IDR);
302 __raw_writel(wakeups[i], pio + PIO_IER); 454 __raw_writel(wakeups[i], pio + PIO_IER);
303 455
304 if (!wakeups[i]) 456 if (!wakeups[i]) {
457 clk_unprepare(gpio_chip[i].clock);
305 clk_disable(gpio_chip[i].clock); 458 clk_disable(gpio_chip[i].clock);
306 else { 459 } else {
307#ifdef CONFIG_PM_DEBUG 460#ifdef CONFIG_PM_DEBUG
308 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); 461 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
309#endif 462#endif
@@ -318,8 +471,10 @@ void at91_gpio_resume(void)
318 for (i = 0; i < gpio_banks; i++) { 471 for (i = 0; i < gpio_banks; i++) {
319 void __iomem *pio = gpio_chip[i].regbase; 472 void __iomem *pio = gpio_chip[i].regbase;
320 473
321 if (!wakeups[i]) 474 if (!wakeups[i]) {
322 clk_enable(gpio_chip[i].clock); 475 if (clk_prepare(gpio_chip[i].clock) == 0)
476 clk_enable(gpio_chip[i].clock);
477 }
323 478
324 __raw_writel(wakeups[i], pio + PIO_IDR); 479 __raw_writel(wakeups[i], pio + PIO_IDR);
325 __raw_writel(backups[i], pio + PIO_IER); 480 __raw_writel(backups[i], pio + PIO_IER);
@@ -335,7 +490,10 @@ void at91_gpio_resume(void)
335 * To use any AT91_PIN_* as an externally triggered IRQ, first call 490 * To use any AT91_PIN_* as an externally triggered IRQ, first call
336 * at91_set_gpio_input() then maybe enable its glitch filter. 491 * at91_set_gpio_input() then maybe enable its glitch filter.
337 * Then just request_irq() with the pin ID; it works like any ARM IRQ 492 * Then just request_irq() with the pin ID; it works like any ARM IRQ
338 * handler, though it always triggers on rising and falling edges. 493 * handler.
494 * First implementation always triggers on rising and falling edges
495 * whereas the newer PIO3 can be additionally configured to trigger on
496 * level, edge with any polarity.
339 * 497 *
340 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 498 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
341 * configuring them with at91_set_a_periph() or at91_set_b_periph(). 499 * configuring them with at91_set_a_periph() or at91_set_b_periph().
@@ -344,9 +502,9 @@ void at91_gpio_resume(void)
344 502
345static void gpio_irq_mask(struct irq_data *d) 503static void gpio_irq_mask(struct irq_data *d)
346{ 504{
347 unsigned pin = irq_to_gpio(d->irq); 505 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
348 void __iomem *pio = pin_to_controller(pin); 506 void __iomem *pio = at91_gpio->regbase;
349 unsigned mask = pin_to_mask(pin); 507 unsigned mask = 1 << d->hwirq;
350 508
351 if (pio) 509 if (pio)
352 __raw_writel(mask, pio + PIO_IDR); 510 __raw_writel(mask, pio + PIO_IDR);
@@ -354,9 +512,9 @@ static void gpio_irq_mask(struct irq_data *d)
354 512
355static void gpio_irq_unmask(struct irq_data *d) 513static void gpio_irq_unmask(struct irq_data *d)
356{ 514{
357 unsigned pin = irq_to_gpio(d->irq); 515 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
358 void __iomem *pio = pin_to_controller(pin); 516 void __iomem *pio = at91_gpio->regbase;
359 unsigned mask = pin_to_mask(pin); 517 unsigned mask = 1 << d->hwirq;
360 518
361 if (pio) 519 if (pio)
362 __raw_writel(mask, pio + PIO_IER); 520 __raw_writel(mask, pio + PIO_IER);
@@ -373,23 +531,66 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
373 } 531 }
374} 532}
375 533
534/* Alternate irq type for PIO3 support */
535static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
536{
537 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
538 void __iomem *pio = at91_gpio->regbase;
539 unsigned mask = 1 << d->hwirq;
540
541 switch (type) {
542 case IRQ_TYPE_EDGE_RISING:
543 __raw_writel(mask, pio + PIO_ESR);
544 __raw_writel(mask, pio + PIO_REHLSR);
545 break;
546 case IRQ_TYPE_EDGE_FALLING:
547 __raw_writel(mask, pio + PIO_ESR);
548 __raw_writel(mask, pio + PIO_FELLSR);
549 break;
550 case IRQ_TYPE_LEVEL_LOW:
551 __raw_writel(mask, pio + PIO_LSR);
552 __raw_writel(mask, pio + PIO_FELLSR);
553 break;
554 case IRQ_TYPE_LEVEL_HIGH:
555 __raw_writel(mask, pio + PIO_LSR);
556 __raw_writel(mask, pio + PIO_REHLSR);
557 break;
558 case IRQ_TYPE_EDGE_BOTH:
559 /*
560 * disable additional interrupt modes:
561 * fall back to default behavior
562 */
563 __raw_writel(mask, pio + PIO_AIMDR);
564 return 0;
565 case IRQ_TYPE_NONE:
566 default:
567 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
568 return -EINVAL;
569 }
570
571 /* enable additional interrupt modes */
572 __raw_writel(mask, pio + PIO_AIMER);
573
574 return 0;
575}
576
376static struct irq_chip gpio_irqchip = { 577static struct irq_chip gpio_irqchip = {
377 .name = "GPIO", 578 .name = "GPIO",
378 .irq_disable = gpio_irq_mask, 579 .irq_disable = gpio_irq_mask,
379 .irq_mask = gpio_irq_mask, 580 .irq_mask = gpio_irq_mask,
380 .irq_unmask = gpio_irq_unmask, 581 .irq_unmask = gpio_irq_unmask,
381 .irq_set_type = gpio_irq_type, 582 /* .irq_set_type is set dynamically */
382 .irq_set_wake = gpio_irq_set_wake, 583 .irq_set_wake = gpio_irq_set_wake,
383}; 584};
384 585
385static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 586static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
386{ 587{
387 unsigned irq_pin;
388 struct irq_data *idata = irq_desc_get_irq_data(desc); 588 struct irq_data *idata = irq_desc_get_irq_data(desc);
389 struct irq_chip *chip = irq_data_get_irq_chip(idata); 589 struct irq_chip *chip = irq_data_get_irq_chip(idata);
390 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); 590 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
391 void __iomem *pio = at91_gpio->regbase; 591 void __iomem *pio = at91_gpio->regbase;
392 u32 isr; 592 unsigned long isr;
593 int n;
393 594
394 /* temporarily mask (level sensitive) parent IRQ */ 595 /* temporarily mask (level sensitive) parent IRQ */
395 chip->irq_ack(idata); 596 chip->irq_ack(idata);
@@ -407,13 +608,10 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
407 continue; 608 continue;
408 } 609 }
409 610
410 irq_pin = gpio_to_irq(at91_gpio->chip.base); 611 n = find_first_bit(&isr, BITS_PER_LONG);
411 612 while (n < BITS_PER_LONG) {
412 while (isr) { 613 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
413 if (isr & 1) 614 n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
414 generic_handle_irq(irq_pin);
415 irq_pin++;
416 isr >>= 1;
417 } 615 }
418 } 616 }
419 chip->irq_unmask(idata); 617 chip->irq_unmask(idata);
@@ -424,6 +622,33 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
424 622
425#ifdef CONFIG_DEBUG_FS 623#ifdef CONFIG_DEBUG_FS
426 624
625static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
626{
627 char *trigger = NULL;
628 char *polarity = NULL;
629
630 if (__raw_readl(pio + PIO_IMR) & mask) {
631 if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
632 trigger = "edge";
633 polarity = "both";
634 } else {
635 if (__raw_readl(pio + PIO_ELSR) & mask) {
636 trigger = "level";
637 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
638 "high" : "low";
639 } else {
640 trigger = "edge";
641 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
642 "rising" : "falling";
643 }
644 }
645 seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
646 } else {
647 seq_printf(s, "GPIO:%s\t\t",
648 __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
649 }
650}
651
427static int at91_gpio_show(struct seq_file *s, void *unused) 652static int at91_gpio_show(struct seq_file *s, void *unused)
428{ 653{
429 int bank, j; 654 int bank, j;
@@ -431,7 +656,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
431 /* print heading */ 656 /* print heading */
432 seq_printf(s, "Pin\t"); 657 seq_printf(s, "Pin\t");
433 for (bank = 0; bank < gpio_banks; bank++) { 658 for (bank = 0; bank < gpio_banks; bank++) {
434 seq_printf(s, "PIO%c\t", 'A' + bank); 659 seq_printf(s, "PIO%c\t\t", 'A' + bank);
435 }; 660 };
436 seq_printf(s, "\n\n"); 661 seq_printf(s, "\n\n");
437 662
@@ -445,11 +670,10 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
445 unsigned mask = pin_to_mask(pin); 670 unsigned mask = pin_to_mask(pin);
446 671
447 if (__raw_readl(pio + PIO_PSR) & mask) 672 if (__raw_readl(pio + PIO_PSR) & mask)
448 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0"); 673 gpio_printf(s, pio, mask);
449 else 674 else
450 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A"); 675 seq_printf(s, "%c\t\t",
451 676 peripheral_function(pio, mask));
452 seq_printf(s, "\t");
453 } 677 }
454 678
455 seq_printf(s, "\n"); 679 seq_printf(s, "\n");
@@ -488,46 +712,152 @@ postcore_initcall(at91_gpio_debugfs_init);
488 */ 712 */
489static struct lock_class_key gpio_lock_class; 713static struct lock_class_key gpio_lock_class;
490 714
715#if defined(CONFIG_OF)
716static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
717 irq_hw_number_t hw)
718{
719 struct at91_gpio_chip *at91_gpio = h->host_data;
720
721 irq_set_lockdep_class(virq, &gpio_lock_class);
722
723 /*
724 * Can use the "simple" and not "edge" handler since it's
725 * shorter, and the AIC handles interrupts sanely.
726 */
727 irq_set_chip_and_handler(virq, &gpio_irqchip,
728 handle_simple_irq);
729 set_irq_flags(virq, IRQF_VALID);
730 irq_set_chip_data(virq, at91_gpio);
731
732 return 0;
733}
734
735static struct irq_domain_ops at91_gpio_ops = {
736 .map = at91_gpio_irq_map,
737 .xlate = irq_domain_xlate_twocell,
738};
739
740int __init at91_gpio_of_irq_setup(struct device_node *node,
741 struct device_node *parent)
742{
743 struct at91_gpio_chip *prev = NULL;
744 int alias_idx = of_alias_get_id(node, "gpio");
745 struct at91_gpio_chip *at91_gpio = &gpio_chip[alias_idx];
746
747 /* Setup proper .irq_set_type function */
748 if (has_pio3())
749 gpio_irqchip.irq_set_type = alt_gpio_irq_type;
750 else
751 gpio_irqchip.irq_set_type = gpio_irq_type;
752
753 /* Disable irqs of this PIO controller */
754 __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
755
756 /* Setup irq domain */
757 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
758 &at91_gpio_ops, at91_gpio);
759 if (!at91_gpio->domain)
760 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
761 at91_gpio->pioc_idx);
762
763 /* Setup chained handler */
764 if (at91_gpio->pioc_idx)
765 prev = &gpio_chip[at91_gpio->pioc_idx - 1];
766
767 /* The toplevel handler handles one bank of GPIOs, except
768 * on some SoC it can handles up to three...
769 * We only set up the handler for the first of the list.
770 */
771 if (prev && prev->next == at91_gpio)
772 return 0;
773
774 at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
775 at91_gpio->pioc_hwirq);
776 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
777 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
778
779 return 0;
780}
781#else
782int __init at91_gpio_of_irq_setup(struct device_node *node,
783 struct device_node *parent)
784{
785 return -EINVAL;
786}
787#endif
788
789/*
790 * irqdomain initialization: pile up irqdomains on top of AIC range
791 */
792static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
793{
794 int irq_base;
795
796 irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
797 if (irq_base < 0)
798 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
799 at91_gpio->pioc_idx, irq_base);
800 at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
801 irq_base, 0,
802 &irq_domain_simple_ops, NULL);
803 if (!at91_gpio->domain)
804 panic("at91_gpio.%d: couldn't allocate irq domain.\n",
805 at91_gpio->pioc_idx);
806}
807
491/* 808/*
492 * Called from the processor-specific init to enable GPIO interrupt support. 809 * Called from the processor-specific init to enable GPIO interrupt support.
493 */ 810 */
494void __init at91_gpio_irq_setup(void) 811void __init at91_gpio_irq_setup(void)
495{ 812{
496 unsigned pioc, irq = gpio_to_irq(0); 813 unsigned pioc;
814 int gpio_irqnbr = 0;
497 struct at91_gpio_chip *this, *prev; 815 struct at91_gpio_chip *this, *prev;
498 816
817 /* Setup proper .irq_set_type function */
818 if (has_pio3())
819 gpio_irqchip.irq_set_type = alt_gpio_irq_type;
820 else
821 gpio_irqchip.irq_set_type = gpio_irq_type;
822
499 for (pioc = 0, this = gpio_chip, prev = NULL; 823 for (pioc = 0, this = gpio_chip, prev = NULL;
500 pioc++ < gpio_banks; 824 pioc++ < gpio_banks;
501 prev = this, this++) { 825 prev = this, this++) {
502 unsigned id = this->id; 826 int offset;
503 unsigned i;
504 827
505 __raw_writel(~0, this->regbase + PIO_IDR); 828 __raw_writel(~0, this->regbase + PIO_IDR);
506 829
507 for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32; 830 /* setup irq domain for this GPIO controller */
508 i++, irq++) { 831 at91_gpio_irqdomain(this);
509 irq_set_lockdep_class(irq, &gpio_lock_class); 832
833 for (offset = 0; offset < this->chip.ngpio; offset++) {
834 unsigned int virq = irq_find_mapping(this->domain, offset);
835 irq_set_lockdep_class(virq, &gpio_lock_class);
510 836
511 /* 837 /*
512 * Can use the "simple" and not "edge" handler since it's 838 * Can use the "simple" and not "edge" handler since it's
513 * shorter, and the AIC handles interrupts sanely. 839 * shorter, and the AIC handles interrupts sanely.
514 */ 840 */
515 irq_set_chip_and_handler(irq, &gpio_irqchip, 841 irq_set_chip_and_handler(virq, &gpio_irqchip,
516 handle_simple_irq); 842 handle_simple_irq);
517 set_irq_flags(irq, IRQF_VALID); 843 set_irq_flags(virq, IRQF_VALID);
844 irq_set_chip_data(virq, this);
845
846 gpio_irqnbr++;
518 } 847 }
519 848
520 /* The toplevel handler handles one bank of GPIOs, except 849 /* The toplevel handler handles one bank of GPIOs, except
521 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in 850 * on some SoC it can handles up to three...
522 * the list, so we only set up that handler. 851 * We only set up the handler for the first of the list.
523 */ 852 */
524 if (prev && prev->next == this) 853 if (prev && prev->next == this)
525 continue; 854 continue;
526 855
527 irq_set_chip_data(id, this); 856 this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
528 irq_set_chained_handler(id, gpio_irq_handler); 857 irq_set_chip_data(this->pioc_virq, this);
858 irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
529 } 859 }
530 pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks); 860 pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
531} 861}
532 862
533/* gpiolib support */ 863/* gpiolib support */
@@ -593,48 +923,175 @@ static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
593 at91_get_gpio_value(pin) ? 923 at91_get_gpio_value(pin) ?
594 "set" : "clear"); 924 "set" : "clear");
595 else 925 else
596 seq_printf(s, "[periph %s]\n", 926 seq_printf(s, "[periph %c]\n",
597 __raw_readl(pio + PIO_ABSR) & 927 peripheral_function(pio, mask));
598 mask ? "B" : "A");
599 } 928 }
600 } 929 }
601} 930}
602 931
932static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
933{
934 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
935 int virq;
936
937 if (offset < chip->ngpio)
938 virq = irq_create_mapping(at91_gpio->domain, offset);
939 else
940 virq = -ENXIO;
941
942 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
943 chip->label, offset + chip->base, virq);
944 return virq;
945}
946
947static int __init at91_gpio_setup_clk(int idx)
948{
949 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
950
951 /* retreive PIO controller's clock */
952 at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
953 if (IS_ERR(at91_gpio->clock)) {
954 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
955 goto err;
956 }
957
958 if (clk_prepare(at91_gpio->clock))
959 goto clk_prep_err;
960
961 /* enable PIO controller's clock */
962 if (clk_enable(at91_gpio->clock)) {
963 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
964 goto clk_err;
965 }
966
967 return 0;
968
969clk_err:
970 clk_unprepare(at91_gpio->clock);
971clk_prep_err:
972 clk_put(at91_gpio->clock);
973err:
974 return -EINVAL;
975}
976
977#ifdef CONFIG_OF_GPIO
978static void __init of_at91_gpio_init_one(struct device_node *np)
979{
980 int alias_idx;
981 struct at91_gpio_chip *at91_gpio;
982
983 if (!np)
984 return;
985
986 alias_idx = of_alias_get_id(np, "gpio");
987 if (alias_idx >= MAX_GPIO_BANKS) {
988 pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
989 alias_idx, MAX_GPIO_BANKS);
990 return;
991 }
992
993 at91_gpio = &gpio_chip[alias_idx];
994 at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
995
996 at91_gpio->regbase = of_iomap(np, 0);
997 if (!at91_gpio->regbase) {
998 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
999 alias_idx);
1000 return;
1001 }
1002
1003 /* Get the interrupts property */
1004 if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
1005 pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
1006 alias_idx);
1007 goto ioremap_err;
1008 }
1009
1010 /* Get capabilities from compatibility property */
1011 if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
1012 at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
1013
1014 /* Setup clock */
1015 if (at91_gpio_setup_clk(alias_idx))
1016 goto ioremap_err;
1017
1018 at91_gpio->chip.of_node = np;
1019 gpio_banks = max(gpio_banks, alias_idx + 1);
1020 at91_gpio->pioc_idx = alias_idx;
1021 return;
1022
1023ioremap_err:
1024 iounmap(at91_gpio->regbase);
1025}
1026
1027static int __init of_at91_gpio_init(void)
1028{
1029 struct device_node *np = NULL;
1030
1031 /*
1032 * This isn't ideal, but it gets things hooked up until this
1033 * driver is converted into a platform_device
1034 */
1035 for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
1036 of_at91_gpio_init_one(np);
1037
1038 return gpio_banks > 0 ? 0 : -EINVAL;
1039}
1040#else
1041static int __init of_at91_gpio_init(void)
1042{
1043 return -EINVAL;
1044}
1045#endif
1046
1047static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
1048{
1049 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
1050
1051 at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
1052 at91_gpio->pioc_hwirq = pioc_hwirq;
1053 at91_gpio->pioc_idx = idx;
1054
1055 at91_gpio->regbase = ioremap(regbase, 512);
1056 if (!at91_gpio->regbase) {
1057 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
1058 return;
1059 }
1060
1061 if (at91_gpio_setup_clk(idx))
1062 goto ioremap_err;
1063
1064 gpio_banks = max(gpio_banks, idx + 1);
1065 return;
1066
1067ioremap_err:
1068 iounmap(at91_gpio->regbase);
1069}
1070
603/* 1071/*
604 * Called from the processor-specific init to enable GPIO pin support. 1072 * Called from the processor-specific init to enable GPIO pin support.
605 */ 1073 */
606void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) 1074void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
607{ 1075{
608 unsigned i; 1076 unsigned i;
609 struct at91_gpio_chip *at91_gpio, *last = NULL; 1077 struct at91_gpio_chip *at91_gpio, *last = NULL;
610 1078
611 BUG_ON(nr_banks > MAX_GPIO_BANKS); 1079 BUG_ON(nr_banks > MAX_GPIO_BANKS);
612 1080
613 gpio_banks = nr_banks; 1081 if (of_at91_gpio_init() < 0) {
1082 /* No GPIO controller found in device tree */
1083 for (i = 0; i < nr_banks; i++)
1084 at91_gpio_init_one(i, data[i].regbase, data[i].id);
1085 }
614 1086
615 for (i = 0; i < nr_banks; i++) { 1087 for (i = 0; i < gpio_banks; i++) {
616 at91_gpio = &gpio_chip[i]; 1088 at91_gpio = &gpio_chip[i];
617 1089
618 at91_gpio->id = data[i].id; 1090 /*
619 at91_gpio->chip.base = i * 32; 1091 * GPIO controller are grouped on some SoC:
620 1092 * PIOC, PIOD and PIOE can share the same IRQ line
621 at91_gpio->regbase = ioremap(data[i].regbase, 512); 1093 */
622 if (!at91_gpio->regbase) { 1094 if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
623 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
624 continue;
625 }
626
627 at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
628 if (!at91_gpio->clock) {
629 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
630 continue;
631 }
632
633 /* enable PIO controller's clock */
634 clk_enable(at91_gpio->clock);
635
636 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
637 if (last && last->id == at91_gpio->id)
638 last->next = at91_gpio; 1095 last->next = at91_gpio;
639 last = at91_gpio; 1096 last = at91_gpio;
640 1097
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
new file mode 100644
index 000000000000..02fae9de746b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
3 *
4 * Under GPLv2
5 */
6
7#ifndef __MACH_AT91_MATRIX_H__
8#define __MACH_AT91_MATRIX_H__
9
10#ifndef __ASSEMBLY__
11extern void __iomem *at91_matrix_base;
12
13#define at91_matrix_read(field) \
14 __raw_readl(at91_matrix_base + field)
15
16#define at91_matrix_write(field, value) \
17 __raw_writel(value, at91_matrix_base + field);
18
19#else
20.extern at91_matrix_base
21#endif
22
23#endif /* __MACH_AT91_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index c6a31bf8a5c6..732b11c37f1a 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -40,10 +40,35 @@
40#define PIO_PUER 0x64 /* Pull-up Enable Register */ 40#define PIO_PUER 0x64 /* Pull-up Enable Register */
41#define PIO_PUSR 0x68 /* Pull-up Status Register */ 41#define PIO_PUSR 0x68 /* Pull-up Status Register */
42#define PIO_ASR 0x70 /* Peripheral A Select Register */ 42#define PIO_ASR 0x70 /* Peripheral A Select Register */
43#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
43#define PIO_BSR 0x74 /* Peripheral B Select Register */ 44#define PIO_BSR 0x74 /* Peripheral B Select Register */
45#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
44#define PIO_ABSR 0x78 /* AB Status Register */ 46#define PIO_ABSR 0x78 /* AB Status Register */
47#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
48#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
49#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
50#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
51#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
52#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
53#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
54#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
45#define PIO_OWER 0xa0 /* Output Write Enable Register */ 55#define PIO_OWER 0xa0 /* Output Write Enable Register */
46#define PIO_OWDR 0xa4 /* Output Write Disable Register */ 56#define PIO_OWDR 0xa4 /* Output Write Disable Register */
47#define PIO_OWSR 0xa8 /* Output Write Status Register */ 57#define PIO_OWSR 0xa8 /* Output Write Status Register */
58#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
59#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
60#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
61#define PIO_ESR 0xc0 /* Edge Select Register */
62#define PIO_LSR 0xc4 /* Level Select Register */
63#define PIO_ELSR 0xc8 /* Edge/Level Status Register */
64#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
65#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
66#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
67#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
68
69#define ABCDSR_PERIPH_A 0x0
70#define ABCDSR_PERIPH_B 0x1
71#define ABCDSR_PERIPH_C 0x2
72#define ABCDSR_PERIPH_D 0x3
48 73
49#endif 74#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index f9fdbbe0c53a..36604782a78f 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -16,10 +16,22 @@
16#ifndef AT91_PMC_H 16#ifndef AT91_PMC_H
17#define AT91_PMC_H 17#define AT91_PMC_H
18 18
19#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ 19#ifndef __ASSEMBLY__
20#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ 20extern void __iomem *at91_pmc_base;
21 21
22#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ 22#define at91_pmc_read(field) \
23 __raw_readl(at91_pmc_base + field)
24
25#define at91_pmc_write(field, value) \
26 __raw_writel(value, at91_pmc_base + field)
27#else
28.extern at91_aic_base
29#endif
30
31#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
32#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
33
34#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */
23#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 35#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
24#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 36#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 37#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
@@ -34,17 +46,17 @@
34#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ 46#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
35#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ 47#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
36 48
37#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ 49#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */
38#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ 50#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 51#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
40 52
41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9] */ 53#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */
42#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ 54#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
43#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ 55#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
44#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ 56#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
45#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ 57#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
46 58
47#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ 59#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
48#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 60#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
49#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ 61#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
50#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ 62#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
@@ -53,12 +65,12 @@
53#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ 65#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
54#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ 66#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
55 67
56#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ 68#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */
57#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ 69#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
58#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ 70#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
59 71
60#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ 72#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
61#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ 73#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
62#define AT91_PMC_DIV (0xff << 0) /* Divider */ 74#define AT91_PMC_DIV (0xff << 0) /* Divider */
63#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 75#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
64#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 76#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
@@ -69,7 +81,7 @@
69#define AT91_PMC_USBDIV_4 (2 << 28) 81#define AT91_PMC_USBDIV_4 (2 << 28)
70#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 82#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
71 83
72#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ 84#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
73#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ 85#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
74#define AT91_PMC_CSS_SLOW (0 << 0) 86#define AT91_PMC_CSS_SLOW (0 << 0)
75#define AT91_PMC_CSS_MAIN (1 << 0) 87#define AT91_PMC_CSS_MAIN (1 << 0)
@@ -111,27 +123,27 @@
111#define AT91_PMC_PLLADIV2_OFF (0 << 12) 123#define AT91_PMC_PLLADIV2_OFF (0 << 12)
112#define AT91_PMC_PLLADIV2_ON (1 << 12) 124#define AT91_PMC_PLLADIV2_ON (1 << 12)
113 125
114#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ 126#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
115#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ 127#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
116#define AT91_PMC_USBS_PLLA (0 << 0) 128#define AT91_PMC_USBS_PLLA (0 << 0)
117#define AT91_PMC_USBS_UPLL (1 << 0) 129#define AT91_PMC_USBS_UPLL (1 << 0)
118#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ 130#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
119 131
120#define AT91_PMC_SMD (AT91_PMC + 0x3c) /* Soft Modem Clock Register [some SAM9 only] */ 132#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
121#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ 133#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */
122#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ 134#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */
123#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) 135#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV)
124 136
125#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ 137#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
126#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ 138#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */
127#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ 139#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
128#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ 140#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
129#define AT91_PMC_CSSMCK_CSS (0 << 8) 141#define AT91_PMC_CSSMCK_CSS (0 << 8)
130#define AT91_PMC_CSSMCK_MCK (1 << 8) 142#define AT91_PMC_CSSMCK_MCK (1 << 8)
131 143
132#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ 144#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
133#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ 145#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
134#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ 146#define AT91_PMC_SR 0x68 /* Status Register */
135#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ 147#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
136#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 148#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
137#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 149#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
@@ -144,18 +156,18 @@
144#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ 156#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */
145#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ 157#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
146#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ 158#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
147#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ 159#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
148 160
149#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Write Protect Mode Register [some SAM9] */ 161#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
150#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ 162#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
151#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ 163#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */
152#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ 164#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */
153 165
154#define AT91_PMC_WPSR (AT91_PMC + 0xe8) /* Write Protect Status Register [some SAM9] */ 166#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */
155#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ 167#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */
156#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ 168#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */
157 169
158#define AT91_PMC_PCR (AT91_PMC + 0x10c) /* Peripheral Control Register [some SAM9] */ 170#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */
159#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ 171#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */
160#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ 172#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */
161#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */ 173#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
new file mode 100644
index 000000000000..d8aeb278614e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -0,0 +1,32 @@
1/*
2 * Header file for the Atmel RAM Controller
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8
9#ifndef __AT91_RAMC_H__
10#define __AT91_RAMC_H__
11
12#ifndef __ASSEMBLY__
13extern void __iomem *at91_ramc_base[];
14
15#define at91_ramc_read(id, field) \
16 __raw_readl(at91_ramc_base[id] + field)
17
18#define at91_ramc_write(id, field, value) \
19 __raw_writel(value, at91_ramc_base[id] + field)
20#else
21.extern at91_ramc_base
22#endif
23
24#define AT91_MEMCTRL_MC 0
25#define AT91_MEMCTRL_SDRAMC 1
26#define AT91_MEMCTRL_DDRSDR 2
27
28#include <mach/at91rm9200_sdramc.h>
29#include <mach/at91sam9_ddrsdr.h>
30#include <mach/at91sam9_sdramc.h>
31
32#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index 8847173e4101..969aac27109f 100644
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -16,34 +16,46 @@
16#ifndef AT91_ST_H 16#ifndef AT91_ST_H
17#define AT91_ST_H 17#define AT91_ST_H
18 18
19#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ 19#ifndef __ASSEMBLY__
20extern void __iomem *at91_st_base;
21
22#define at91_st_read(field) \
23 __raw_readl(at91_st_base + field)
24
25#define at91_st_write(field, value) \
26 __raw_writel(value, at91_st_base + field);
27#else
28.extern at91_st_base
29#endif
30
31#define AT91_ST_CR 0x00 /* Control Register */
20#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ 32#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
21 33
22#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ 34#define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
23#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ 35#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
24 36
25#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ 37#define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
26#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ 38#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
27#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ 39#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
28#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ 40#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
29 41
30#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ 42#define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
31#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ 43#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
32 44
33#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ 45#define AT91_ST_SR 0x10 /* Status Register */
34#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ 46#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
35#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ 47#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
36#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ 48#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
37#define AT91_ST_ALMS (1 << 3) /* Alarm Status */ 49#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
38 50
39#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ 51#define AT91_ST_IER 0x14 /* Interrupt Enable Register */
40#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ 52#define AT91_ST_IDR 0x18 /* Interrupt Disable Register */
41#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ 53#define AT91_ST_IMR 0x1c /* Interrupt Mask Register */
42 54
43#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ 55#define AT91_ST_RTAR 0x20 /* Real-time Alarm Register */
44#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ 56#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
45 57
46#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ 58#define AT91_ST_CRTR 0x24 /* Current Real-time Register */
47#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ 59#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
48 60
49#endif 61#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index bacb51141819..603e6aac2a4f 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -77,26 +77,22 @@
77 77
78 78
79/* 79/*
80 * System Peripherals (offset from AT91_BASE_SYS) 80 * System Peripherals
81 */ 81 */
82#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
83#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
84#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
85
86#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */ 82#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
87#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */ 83#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
88#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */ 84#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
89#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */ 85#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
90#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */ 86#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
87#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
91#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */ 88#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
89#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
92 90
93#define AT91_USART0 AT91RM9200_BASE_US0 91#define AT91_USART0 AT91RM9200_BASE_US0
94#define AT91_USART1 AT91RM9200_BASE_US1 92#define AT91_USART1 AT91RM9200_BASE_US1
95#define AT91_USART2 AT91RM9200_BASE_US2 93#define AT91_USART2 AT91RM9200_BASE_US2
96#define AT91_USART3 AT91RM9200_BASE_US3 94#define AT91_USART3 AT91RM9200_BASE_US3
97 95
98#define AT91_MATRIX 0 /* not supported */
99
100/* 96/*
101 * Internal Memory. 97 * Internal Memory.
102 */ 98 */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index d34e4ed89349..aeaadfb452af 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -17,10 +17,10 @@
17#define AT91RM9200_MC_H 17#define AT91RM9200_MC_H
18 18
19/* Memory Controller */ 19/* Memory Controller */
20#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ 20#define AT91_MC_RCR 0x00 /* MC Remap Control Register */
21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ 21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
22 22
23#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ 23#define AT91_MC_ASR 0x04 /* MC Abort Status Register */
24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ 24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ 25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ 26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
@@ -40,16 +40,16 @@
40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ 40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ 41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
42 42
43#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ 43#define AT91_MC_AASR 0x08 /* MC Abort Address Status Register */
44 44
45#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ 45#define AT91_MC_MPR 0x0c /* MC Master Priority Register */
46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ 46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ 47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ 48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ 49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
50 50
51/* External Bus Interface (EBI) registers */ 51/* External Bus Interface (EBI) registers */
52#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ 52#define AT91_EBI_CSA 0x60 /* Chip Select Assignment Register */
53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ 53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
54#define AT91_EBI_CS0A_SMC (0 << 0) 54#define AT91_EBI_CS0A_SMC (0 << 0)
55#define AT91_EBI_CS0A_BFC (1 << 0) 55#define AT91_EBI_CS0A_BFC (1 << 0)
@@ -66,7 +66,7 @@
66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ 66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
67 67
68/* Static Memory Controller (SMC) registers */ 68/* Static Memory Controller (SMC) registers */
69#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ 69#define AT91_SMC_CSR(n) (0x70 + ((n) * 4)) /* SMC Chip Select Register */
70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ 70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
71#define AT91_SMC_NWS_(x) ((x) << 0) 71#define AT91_SMC_NWS_(x) ((x) << 0)
72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ 72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
@@ -87,52 +87,8 @@
87#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ 87#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
88#define AT91_SMC_RWHOLD_(x) ((x) << 28) 88#define AT91_SMC_RWHOLD_(x) ((x) << 28)
89 89
90/* SDRAM Controller registers */
91#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
92#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
93#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
94#define AT91_SDRAMC_MODE_NOP (1 << 0)
95#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
96#define AT91_SDRAMC_MODE_LMR (3 << 0)
97#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
98#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
99#define AT91_SDRAMC_DBW_32 (0 << 4)
100#define AT91_SDRAMC_DBW_16 (1 << 4)
101
102#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
103#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
104
105#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
106#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
107#define AT91_SDRAMC_NC_8 (0 << 0)
108#define AT91_SDRAMC_NC_9 (1 << 0)
109#define AT91_SDRAMC_NC_10 (2 << 0)
110#define AT91_SDRAMC_NC_11 (3 << 0)
111#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
112#define AT91_SDRAMC_NR_11 (0 << 2)
113#define AT91_SDRAMC_NR_12 (1 << 2)
114#define AT91_SDRAMC_NR_13 (2 << 2)
115#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
116#define AT91_SDRAMC_NB_2 (0 << 4)
117#define AT91_SDRAMC_NB_4 (1 << 4)
118#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
119#define AT91_SDRAMC_CAS_2 (2 << 5)
120#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
121#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
122#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
123#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
124#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
125#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
126
127#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
128#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
129#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
130#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
131#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
132#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
133
134/* Burst Flash Controller register */ 90/* Burst Flash Controller register */
135#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ 91#define AT91_BFC_MR 0xc0 /* Mode Register */
136#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ 92#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
137#define AT91_BFC_BFCOM_DISABLED (0 << 0) 93#define AT91_BFC_BFCOM_DISABLED (0 << 0)
138#define AT91_BFC_BFCOM_ASYNC (1 << 0) 94#define AT91_BFC_BFCOM_ASYNC (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
new file mode 100644
index 000000000000..aa047f458f1b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
@@ -0,0 +1,63 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Memory Controllers (SDRAMC only) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_SDRAMC_H
17#define AT91RM9200_SDRAMC_H
18
19/* SDRAM Controller registers */
20#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
21#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
22#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
23#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
24#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
25#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
26#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
27#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
28#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
29#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
30
31#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
32#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
33
34#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
35#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
36#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
37#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
38#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
39#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
40#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
41#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
42#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
43#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
44#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
45#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
46#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
47#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
48#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
49#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
50#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
51#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
52#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
53#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
54#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
55
56#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
57#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
58#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
59#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
60#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
61#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
62
63#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index fa5ca278adeb..08ae9afd00fe 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -78,15 +78,12 @@
78#define AT91SAM9260_BASE_ADC 0xfffe0000 78#define AT91SAM9260_BASE_ADC 0xfffe0000
79 79
80/* 80/*
81 * System Peripherals (offset from AT91_BASE_SYS) 81 * System Peripherals
82 */ 82 */
83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
87
88#define AT91SAM9260_BASE_ECC 0xffffe800 83#define AT91SAM9260_BASE_ECC 0xffffe800
84#define AT91SAM9260_BASE_SDRAMC 0xffffea00
89#define AT91SAM9260_BASE_SMC 0xffffec00 85#define AT91SAM9260_BASE_SMC 0xffffec00
86#define AT91SAM9260_BASE_MATRIX 0xffffee00
90#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0 87#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
91#define AT91SAM9260_BASE_PIOA 0xfffff400 88#define AT91SAM9260_BASE_PIOA 0xfffff400
92#define AT91SAM9260_BASE_PIOB 0xfffff600 89#define AT91SAM9260_BASE_PIOB 0xfffff600
@@ -96,6 +93,7 @@
96#define AT91SAM9260_BASE_RTT 0xfffffd20 93#define AT91SAM9260_BASE_RTT 0xfffffd20
97#define AT91SAM9260_BASE_PIT 0xfffffd30 94#define AT91SAM9260_BASE_PIT 0xfffffd30
98#define AT91SAM9260_BASE_WDT 0xfffffd40 95#define AT91SAM9260_BASE_WDT 0xfffffd40
96#define AT91SAM9260_BASE_GPBR 0xfffffd50
99 97
100#define AT91_USART0 AT91SAM9260_BASE_US0 98#define AT91_USART0 AT91SAM9260_BASE_US0
101#define AT91_USART1 AT91SAM9260_BASE_US1 99#define AT91_USART1 AT91SAM9260_BASE_US1
@@ -115,6 +113,8 @@
115#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ 113#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
116#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ 114#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
117#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ 115#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
116#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
117#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
118 118
119#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ 119#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
120 120
@@ -128,6 +128,8 @@
128#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ 128#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
129#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ 129#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
130#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ 130#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
131#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
132#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
131 133
132#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ 134#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
133 135
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index 020f02ed921a..f459df420629 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -15,12 +15,12 @@
15#ifndef AT91SAM9260_MATRIX_H 15#ifndef AT91SAM9260_MATRIX_H
16#define AT91SAM9260_MATRIX_H 16#define AT91SAM9260_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 24#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
25#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 25#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
26#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 26#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -28,11 +28,11 @@
28#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 28#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
29#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 29#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
30 30
31#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 31#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
32#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 32#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
33#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 33#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
34#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 34#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
35#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 35#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -43,11 +43,11 @@
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45 45
46#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 51#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
52#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 52#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
53#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 53#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -55,11 +55,11 @@
55#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 55#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
56#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 56#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
57 57
58#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 58#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
59#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 59#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
60#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 60#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
61 61
62#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ 62#define AT91_MATRIX_EBICSA 0x11C /* EBI Chip Select Assignment Register */
63#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 63#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
64#define AT91_MATRIX_CS1A_SMC (0 << 1) 64#define AT91_MATRIX_CS1A_SMC (0 << 1)
65#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 65#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 7cde2d36570e..44fbdc12ee62 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -63,14 +63,11 @@
63 63
64 64
65/* 65/*
66 * System Peripherals (offset from AT91_BASE_SYS) 66 * System Peripherals
67 */ 67 */
68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
71#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
72
73#define AT91SAM9261_BASE_SMC 0xffffec00 68#define AT91SAM9261_BASE_SMC 0xffffec00
69#define AT91SAM9261_BASE_MATRIX 0xffffee00
70#define AT91SAM9261_BASE_SDRAMC 0xffffea00
74#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0 71#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
75#define AT91SAM9261_BASE_PIOA 0xfffff400 72#define AT91SAM9261_BASE_PIOA 0xfffff400
76#define AT91SAM9261_BASE_PIOB 0xfffff600 73#define AT91SAM9261_BASE_PIOB 0xfffff600
@@ -80,6 +77,7 @@
80#define AT91SAM9261_BASE_RTT 0xfffffd20 77#define AT91SAM9261_BASE_RTT 0xfffffd20
81#define AT91SAM9261_BASE_PIT 0xfffffd30 78#define AT91SAM9261_BASE_PIT 0xfffffd30
82#define AT91SAM9261_BASE_WDT 0xfffffd40 79#define AT91SAM9261_BASE_WDT 0xfffffd40
80#define AT91SAM9261_BASE_GPBR 0xfffffd50
83 81
84#define AT91_USART0 AT91SAM9261_BASE_US0 82#define AT91_USART0 AT91SAM9261_BASE_US0
85#define AT91_USART1 AT91SAM9261_BASE_US1 83#define AT91_USART1 AT91SAM9261_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index 69c6501915d9..a50cdf8b8ca4 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -15,15 +15,15 @@
15#ifndef AT91SAM9261_MATRIX_H 15#ifndef AT91SAM9261_MATRIX_H
16#define AT91SAM9261_MATRIX_H 16#define AT91SAM9261_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ 18#define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */
19#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 19#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
20#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 20#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
21 21
22#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ 22#define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */
23#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ 23#define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */
24#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ 24#define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */
25#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ 25#define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */
26#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ 26#define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */
27#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 27#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
28#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 28#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
29#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 29#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -31,7 +31,7 @@
31#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 31#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
32#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ 32#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
33 33
34#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ 34#define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */
35#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 35#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
36#define AT91_MATRIX_ITCM_0 (0 << 0) 36#define AT91_MATRIX_ITCM_0 (0 << 0)
37#define AT91_MATRIX_ITCM_16 (5 << 0) 37#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -43,7 +43,7 @@
43#define AT91_MATRIX_DTCM_32 (6 << 4) 43#define AT91_MATRIX_DTCM_32 (6 << 4)
44#define AT91_MATRIX_DTCM_64 (7 << 4) 44#define AT91_MATRIX_DTCM_64 (7 << 4)
45 45
46#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ 46#define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */
47#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 47#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
48#define AT91_MATRIX_CS1A_SMC (0 << 1) 48#define AT91_MATRIX_CS1A_SMC (0 << 1)
49#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 49#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
@@ -58,7 +58,7 @@
58#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 58#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
59#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ 59#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
60 60
61#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ 61#define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */
62#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ 62#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
63 63
64#endif 64#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 5949abda962b..d96cbb2e03c4 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -72,18 +72,15 @@
72#define AT91SAM9263_BASE_2DGE 0xfffc8000 72#define AT91SAM9263_BASE_2DGE 0xfffc8000
73 73
74/* 74/*
75 * System Peripherals (offset from AT91_BASE_SYS) 75 * System Peripherals
76 */ 76 */
77#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
81#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
82
83#define AT91SAM9263_BASE_ECC0 0xffffe000 77#define AT91SAM9263_BASE_ECC0 0xffffe000
78#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
84#define AT91SAM9263_BASE_SMC0 0xffffe400 79#define AT91SAM9263_BASE_SMC0 0xffffe400
85#define AT91SAM9263_BASE_ECC1 0xffffe600 80#define AT91SAM9263_BASE_ECC1 0xffffe600
81#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
86#define AT91SAM9263_BASE_SMC1 0xffffea00 82#define AT91SAM9263_BASE_SMC1 0xffffea00
83#define AT91SAM9263_BASE_MATRIX 0xffffec00
87#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1 84#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
88#define AT91SAM9263_BASE_PIOA 0xfffff200 85#define AT91SAM9263_BASE_PIOA 0xfffff200
89#define AT91SAM9263_BASE_PIOB 0xfffff400 86#define AT91SAM9263_BASE_PIOB 0xfffff400
@@ -96,6 +93,7 @@
96#define AT91SAM9263_BASE_PIT 0xfffffd30 93#define AT91SAM9263_BASE_PIT 0xfffffd30
97#define AT91SAM9263_BASE_WDT 0xfffffd40 94#define AT91SAM9263_BASE_WDT 0xfffffd40
98#define AT91SAM9263_BASE_RTT1 0xfffffd50 95#define AT91SAM9263_BASE_RTT1 0xfffffd50
96#define AT91SAM9263_BASE_GPBR 0xfffffd60
99 97
100#define AT91_USART0 AT91SAM9263_BASE_US0 98#define AT91_USART0 AT91SAM9263_BASE_US0
101#define AT91_USART1 AT91SAM9263_BASE_US1 99#define AT91_USART1 AT91SAM9263_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 9b3efd3eb2f3..ebb5fdb565e0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -15,15 +15,15 @@
15#ifndef AT91SAM9263_MATRIX_H 15#ifndef AT91SAM9263_MATRIX_H
16#define AT91SAM9263_MATRIX_H 16#define AT91SAM9263_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ 24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ 25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ 26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 27#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
28#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 28#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
29#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 29#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -31,14 +31,14 @@
31#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 31#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 32#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
33 33
34#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 34#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
35#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 35#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
36#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 36#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
37#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 37#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
38#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 38#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
39#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 39#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
40#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ 40#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
41#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ 41#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 42#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 43#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -49,22 +49,22 @@
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
51 51
52#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 52#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
53#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ 53#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
54#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 54#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
55#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ 55#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
56#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 56#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
57#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ 57#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
58#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 58#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
59#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ 59#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
60#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 60#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
61#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ 61#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
62#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 62#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
63#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ 63#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
64#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ 64#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
65#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ 65#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
66#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ 66#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
67#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ 67#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 68#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 69#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 70#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -75,7 +75,7 @@
75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ 75#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ 76#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
77 77
78#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 78#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 79#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 80#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
81#define AT91_MATRIX_RCB2 (1 << 2) 81#define AT91_MATRIX_RCB2 (1 << 2)
@@ -86,7 +86,7 @@
86#define AT91_MATRIX_RCB7 (1 << 7) 86#define AT91_MATRIX_RCB7 (1 << 7)
87#define AT91_MATRIX_RCB8 (1 << 8) 87#define AT91_MATRIX_RCB8 (1 << 8)
88 88
89#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ 89#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 90#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
91#define AT91_MATRIX_ITCM_0 (0 << 0) 91#define AT91_MATRIX_ITCM_0 (0 << 0)
92#define AT91_MATRIX_ITCM_16 (5 << 0) 92#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -96,7 +96,7 @@
96#define AT91_MATRIX_DTCM_16 (5 << 4) 96#define AT91_MATRIX_DTCM_16 (5 << 4)
97#define AT91_MATRIX_DTCM_32 (6 << 4) 97#define AT91_MATRIX_DTCM_32 (6 << 4)
98 98
99#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ 99#define AT91_MATRIX_EBI0CSA 0x120 /* EBI0 Chip Select Assignment Register */
100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ 100#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) 101#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) 102#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
@@ -114,7 +114,7 @@
114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) 114#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) 115#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
116 116
117#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ 117#define AT91_MATRIX_EBI1CSA 0x124 /* EBI1 Chip Select Assignment Register */
118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ 118#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) 119#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) 120#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index 5d4a9f846584..0210797abf2e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -121,10 +121,4 @@
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ 121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ 122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123 123
124/* Register access macros */
125#define at91_ramc_read(num, reg) \
126 at91_sys_read(AT91_DDRSDRC##num + reg)
127#define at91_ramc_write(num, reg, value) \
128 at91_sys_write(AT91_DDRSDRC##num + reg, value)
129
130#endif 124#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 100f5a592926..3d085a9a7450 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -82,10 +82,4 @@
82#define AT91_SDRAMC_MD_SDRAM 0 82#define AT91_SDRAMC_MD_SDRAM 0
83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 83#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
84 84
85/* Register access macros */
86#define at91_ramc_read(num, reg) \
87 at91_sys_read(AT91_SDRAMC##num + reg)
88#define at91_ramc_write(num, reg, value) \
89 at91_sys_write(AT91_SDRAMC##num + reg, value)
90
91#endif 85#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index dd9c95ea0862..d052abcff852 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -84,17 +84,14 @@
84#define AT91SAM9G45_BASE_TC5 0xfffd4080 84#define AT91SAM9G45_BASE_TC5 0xfffd4080
85 85
86/* 86/*
87 * System Peripherals (offset from AT91_BASE_SYS) 87 * System Peripherals
88 */ 88 */
89#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
93#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
94
95#define AT91SAM9G45_BASE_ECC 0xffffe200 89#define AT91SAM9G45_BASE_ECC 0xffffe200
90#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
91#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
96#define AT91SAM9G45_BASE_DMA 0xffffec00 92#define AT91SAM9G45_BASE_DMA 0xffffec00
97#define AT91SAM9G45_BASE_SMC 0xffffe800 93#define AT91SAM9G45_BASE_SMC 0xffffe800
94#define AT91SAM9G45_BASE_MATRIX 0xffffea00
98#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1 95#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
99#define AT91SAM9G45_BASE_PIOA 0xfffff200 96#define AT91SAM9G45_BASE_PIOA 0xfffff200
100#define AT91SAM9G45_BASE_PIOB 0xfffff400 97#define AT91SAM9G45_BASE_PIOB 0xfffff400
@@ -107,6 +104,7 @@
107#define AT91SAM9G45_BASE_PIT 0xfffffd30 104#define AT91SAM9G45_BASE_PIT 0xfffffd30
108#define AT91SAM9G45_BASE_WDT 0xfffffd40 105#define AT91SAM9G45_BASE_WDT 0xfffffd40
109#define AT91SAM9G45_BASE_RTC 0xfffffdb0 106#define AT91SAM9G45_BASE_RTC 0xfffffdb0
107#define AT91SAM9G45_BASE_GPBR 0xfffffd60
110 108
111#define AT91_USART0 AT91SAM9G45_BASE_US0 109#define AT91_USART0 AT91SAM9G45_BASE_US0
112#define AT91_USART1 AT91SAM9G45_BASE_US1 110#define AT91_USART1 AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index c972d60e0aeb..b76e2ed2fbc2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -15,18 +15,18 @@
15#ifndef AT91SAM9G45_MATRIX_H 15#ifndef AT91SAM9G45_MATRIX_H
16#define AT91SAM9G45_MATRIX_H 16#define AT91SAM9G45_MATRIX_H
17 17
18#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 18#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
19#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 19#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
20#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 20#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
21#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 21#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
22#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 22#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
23#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 23#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
24#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ 24#define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */
25#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ 25#define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */
26#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ 26#define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */
27#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ 27#define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */
28#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ 28#define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */
29#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ 29#define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */
30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 30#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
31#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 31#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
32#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 32#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -37,14 +37,14 @@
37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) 37#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
38#define AT91_MATRIX_ULBT_128 (7 << 0) 38#define AT91_MATRIX_ULBT_128 (7 << 0)
39 39
40#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 40#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
41#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 41#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
42#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 42#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
43#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 43#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
44#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 44#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
45#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 45#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
46#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ 46#define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */
47#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ 47#define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */
48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 48#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 49#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 50#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -52,22 +52,22 @@
52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 52#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ 53#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
54 54
55#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 55#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
56#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ 56#define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */
57#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 57#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
58#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ 58#define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */
59#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 59#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
60#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ 60#define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */
61#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 61#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
62#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ 62#define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */
63#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 63#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
64#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ 64#define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */
65#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 65#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
66#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ 66#define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */
67#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ 67#define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */
68#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ 68#define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */
69#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ 69#define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */
70#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ 70#define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */
71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 71#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 72#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 73#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -81,7 +81,7 @@
81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ 81#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ 82#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
83 83
84#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 84#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 85#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 86#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
87#define AT91_MATRIX_RCB2 (1 << 2) 87#define AT91_MATRIX_RCB2 (1 << 2)
@@ -95,7 +95,7 @@
95#define AT91_MATRIX_RCB10 (1 << 10) 95#define AT91_MATRIX_RCB10 (1 << 10)
96#define AT91_MATRIX_RCB11 (1 << 11) 96#define AT91_MATRIX_RCB11 (1 << 11)
97 97
98#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ 98#define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */
99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 99#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
100#define AT91_MATRIX_ITCM_0 (0 << 0) 100#define AT91_MATRIX_ITCM_0 (0 << 0)
101#define AT91_MATRIX_ITCM_32 (6 << 0) 101#define AT91_MATRIX_ITCM_32 (6 << 0)
@@ -107,12 +107,12 @@
107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) 107#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) 108#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
109 109
110#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ 110#define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */
111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ 111#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
112#define AT91C_VDEC_SEL_OFF (0 << 0) 112#define AT91C_VDEC_SEL_OFF (0 << 0)
113#define AT91C_VDEC_SEL_ON (1 << 0) 113#define AT91C_VDEC_SEL_ON (1 << 0)
114 114
115#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ 115#define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */
116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ 116#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 117#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) 118#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
@@ -138,13 +138,13 @@
138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) 138#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) 139#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
140 140
141#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ 141#define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */
142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ 142#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) 143#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) 144#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ 145#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
146 146
147#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ 147#define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */
148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ 148#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) 149#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
150#define AT91_MATRIX_WPSR_WPV (1 << 0) 150#define AT91_MATRIX_WPSR_WPV (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index d7bead7118da..e0073eb10144 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,15 +69,13 @@
69/* 69/*
70 * System Peripherals (offset from AT91_BASE_SYS) 70 * System Peripherals (offset from AT91_BASE_SYS)
71 */ 71 */
72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
75#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 72#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
76#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
77 73
78#define AT91SAM9RL_BASE_DMA 0xffffe600 74#define AT91SAM9RL_BASE_DMA 0xffffe600
79#define AT91SAM9RL_BASE_ECC 0xffffe800 75#define AT91SAM9RL_BASE_ECC 0xffffe800
76#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
80#define AT91SAM9RL_BASE_SMC 0xffffec00 77#define AT91SAM9RL_BASE_SMC 0xffffec00
78#define AT91SAM9RL_BASE_MATRIX 0xffffee00
81#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0 79#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
82#define AT91SAM9RL_BASE_PIOA 0xfffff400 80#define AT91SAM9RL_BASE_PIOA 0xfffff400
83#define AT91SAM9RL_BASE_PIOB 0xfffff600 81#define AT91SAM9RL_BASE_PIOB 0xfffff600
@@ -88,6 +86,7 @@
88#define AT91SAM9RL_BASE_RTT 0xfffffd20 86#define AT91SAM9RL_BASE_RTT 0xfffffd20
89#define AT91SAM9RL_BASE_PIT 0xfffffd30 87#define AT91SAM9RL_BASE_PIT 0xfffffd30
90#define AT91SAM9RL_BASE_WDT 0xfffffd40 88#define AT91SAM9RL_BASE_WDT 0xfffffd40
89#define AT91SAM9RL_BASE_GPBR 0xfffffd60
91#define AT91SAM9RL_BASE_RTC 0xfffffe00 90#define AT91SAM9RL_BASE_RTC 0xfffffe00
92 91
93#define AT91_USART0 AT91SAM9RL_BASE_US0 92#define AT91_USART0 AT91SAM9RL_BASE_US0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
index 5f9149071fe5..6d160adadafc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
@@ -14,12 +14,12 @@
14#ifndef AT91SAM9RL_MATRIX_H 14#ifndef AT91SAM9RL_MATRIX_H
15#define AT91SAM9RL_MATRIX_H 15#define AT91SAM9RL_MATRIX_H
16 16
17#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ 17#define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */
18#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ 18#define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */
19#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ 19#define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */
20#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ 20#define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */
21#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ 21#define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */
22#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ 22#define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */
23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ 23#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
24#define AT91_MATRIX_ULBT_INFINITE (0 << 0) 24#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
25#define AT91_MATRIX_ULBT_SINGLE (1 << 0) 25#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
@@ -27,12 +27,12 @@
27#define AT91_MATRIX_ULBT_EIGHT (3 << 0) 27#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) 28#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
29 29
30#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ 30#define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */
31#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ 31#define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */
32#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ 32#define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */
33#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ 33#define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */
34#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ 34#define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */
35#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ 35#define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */
36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ 36#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ 37#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
@@ -43,12 +43,12 @@
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
45 45
46#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ 46#define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */
47#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ 47#define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */
48#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ 48#define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */
49#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ 49#define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */
50#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ 50#define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */
51#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ 51#define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */
52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ 52#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ 53#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ 54#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
@@ -56,7 +56,7 @@
56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ 56#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ 57#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
58 58
59#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ 59#define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */
60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ 60#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ 61#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
62#define AT91_MATRIX_RCB2 (1 << 2) 62#define AT91_MATRIX_RCB2 (1 << 2)
@@ -64,7 +64,7 @@
64#define AT91_MATRIX_RCB4 (1 << 4) 64#define AT91_MATRIX_RCB4 (1 << 4)
65#define AT91_MATRIX_RCB5 (1 << 5) 65#define AT91_MATRIX_RCB5 (1 << 5)
66 66
67#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ 67#define AT91_MATRIX_TCMR 0x114 /* TCM Configuration Register */
68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ 68#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
69#define AT91_MATRIX_ITCM_0 (0 << 0) 69#define AT91_MATRIX_ITCM_0 (0 << 0)
70#define AT91_MATRIX_ITCM_16 (5 << 0) 70#define AT91_MATRIX_ITCM_16 (5 << 0)
@@ -74,7 +74,7 @@
74#define AT91_MATRIX_DTCM_16 (5 << 4) 74#define AT91_MATRIX_DTCM_16 (5 << 4)
75#define AT91_MATRIX_DTCM_32 (6 << 4) 75#define AT91_MATRIX_DTCM_32 (6 << 4)
76 76
77#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ 77#define AT91_MATRIX_EBICSA 0x120 /* EBI0 Chip Select Assignment Register */
78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ 78#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
79#define AT91_MATRIX_CS1A_SMC (0 << 1) 79#define AT91_MATRIX_CS1A_SMC (0 << 1)
80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) 80#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 8476871a2f9f..a297a77d88e2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -55,10 +55,9 @@
55#define AT91SAM9X5_BASE_USART2 0xf8024000 55#define AT91SAM9X5_BASE_USART2 0xf8024000
56 56
57/* 57/*
58 * System Peripherals (offset from AT91_BASE_SYS) 58 * System Peripherals
59 */ 59 */
60#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS) 60#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
61#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
62 61
63/* 62/*
64 * Base addresses for early serial code (uncompress.h) 63 * Base addresses for early serial code (uncompress.h)
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index a57829f4fd18..90680217064e 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -28,18 +28,18 @@
28#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ 28#define AT91X40_ID_IRQ2 18 /* External IRQ 2 */
29 29
30/* 30/*
31 * System Peripherals (offset from AT91_BASE_SYS) 31 * System Peripherals
32 */ 32 */
33#define AT91_BASE_SYS 0xffc00000 33#define AT91_BASE_SYS 0xffc00000
34 34
35#define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */ 35#define AT91_EBI 0xffe00000 /* External Bus Interface */
36#define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */ 36#define AT91_SF 0xfff00000 /* Special Function */
37#define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */ 37#define AT91_USART1 0xfffcc000 /* USART 1 */
38#define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */ 38#define AT91_USART0 0xfffd0000 /* USART 0 */
39#define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */ 39#define AT91_TC 0xfffe0000 /* Timer Counter */
40#define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ 40#define AT91_PIOA 0xffff0000 /* PIO Controller A */
41#define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ 41#define AT91_PS 0xffff4000 /* Power Save */
42#define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ 42#define AT91_WD 0xffff8000 /* Watchdog Timer */
43 43
44/* 44/*
45 * The AT91x40 series doesn't have a debug unit like the other AT91 parts. 45 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index e3fd225121c7..eed465ab0dd7 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -191,10 +191,15 @@
191extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup); 191extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
192extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); 192extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
193extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); 193extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
194extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
195extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
194extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); 196extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
195extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); 197extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
196extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); 198extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
199extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
197extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); 200extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
201extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
202extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
198 203
199/* callable at any time */ 204/* callable at any time */
200extern int at91_set_gpio_value(unsigned pin, int value); 205extern int at91_set_gpio_value(unsigned pin, int value);
@@ -204,18 +209,6 @@ extern int at91_get_gpio_value(unsigned pin);
204extern void at91_gpio_suspend(void); 209extern void at91_gpio_suspend(void);
205extern void at91_gpio_resume(void); 210extern void at91_gpio_resume(void);
206 211
207/*-------------------------------------------------------------------------*/
208
209/* wrappers for "new style" GPIO calls. the old AT91-specific ones should
210 * eventually be removed (along with this errno.h inclusion), and the
211 * gpio request/free calls should probably be implemented.
212 */
213
214#include <asm/errno.h>
215
216#define gpio_to_irq(gpio) (gpio + NR_AIC_IRQS)
217#define irq_to_gpio(irq) (irq - NR_AIC_IRQS)
218
219#endif /* __ASSEMBLY__ */ 212#endif /* __ASSEMBLY__ */
220 213
221#endif 214#endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index fd7dce4f7378..e9e29a6c3868 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -59,9 +59,10 @@
59 59
60/* 60/*
61 * On all at91 have the Advanced Interrupt Controller starts at address 61 * On all at91 have the Advanced Interrupt Controller starts at address
62 * 0xfffff000 62 * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
63 */ 63 */
64#define AT91_AIC 0xfffff000 64#define AT91_AIC 0xfffff000
65#define AT91_PMC 0xfffffc00
65 66
66/* 67/*
67 * Peripheral identifiers/interrupts. 68 * Peripheral identifiers/interrupts.
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 4ca09ef7ca29..4003001eca3d 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -28,22 +28,4 @@
28#define __io(a) __typesafe_io(a) 28#define __io(a) __typesafe_io(a)
29#define __mem_pci(a) (a) 29#define __mem_pci(a) (a)
30 30
31#ifndef __ASSEMBLY__
32
33static inline unsigned int at91_sys_read(unsigned int reg_offset)
34{
35 void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
36
37 return __raw_readl(addr + reg_offset);
38}
39
40static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
41{
42 void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
43
44 __raw_writel(value, addr + reg_offset);
45}
46
47#endif
48
49#endif 31#endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index be6b639ecd7b..cfcfcbe36269 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -24,6 +24,12 @@
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/mm.h> 25#include <linux/mm.h>
26#include <linux/types.h> 26#include <linux/types.h>
27#include <linux/irq.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/irqdomain.h>
32#include <linux/err.h>
27 33
28#include <mach/hardware.h> 34#include <mach/hardware.h>
29#include <asm/irq.h> 35#include <asm/irq.h>
@@ -34,22 +40,24 @@
34#include <asm/mach/map.h> 40#include <asm/mach/map.h>
35 41
36void __iomem *at91_aic_base; 42void __iomem *at91_aic_base;
43static struct irq_domain *at91_aic_domain;
44static struct device_node *at91_aic_np;
37 45
38static void at91_aic_mask_irq(struct irq_data *d) 46static void at91_aic_mask_irq(struct irq_data *d)
39{ 47{
40 /* Disable interrupt on AIC */ 48 /* Disable interrupt on AIC */
41 at91_aic_write(AT91_AIC_IDCR, 1 << d->irq); 49 at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
42} 50}
43 51
44static void at91_aic_unmask_irq(struct irq_data *d) 52static void at91_aic_unmask_irq(struct irq_data *d)
45{ 53{
46 /* Enable interrupt on AIC */ 54 /* Enable interrupt on AIC */
47 at91_aic_write(AT91_AIC_IECR, 1 << d->irq); 55 at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
48} 56}
49 57
50unsigned int at91_extern_irq; 58unsigned int at91_extern_irq;
51 59
52#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq) 60#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
53 61
54static int at91_aic_set_type(struct irq_data *d, unsigned type) 62static int at91_aic_set_type(struct irq_data *d, unsigned type)
55{ 63{
@@ -63,13 +71,13 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
63 srctype = AT91_AIC_SRCTYPE_RISING; 71 srctype = AT91_AIC_SRCTYPE_RISING;
64 break; 72 break;
65 case IRQ_TYPE_LEVEL_LOW: 73 case IRQ_TYPE_LEVEL_LOW:
66 if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */ 74 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
67 srctype = AT91_AIC_SRCTYPE_LOW; 75 srctype = AT91_AIC_SRCTYPE_LOW;
68 else 76 else
69 return -EINVAL; 77 return -EINVAL;
70 break; 78 break;
71 case IRQ_TYPE_EDGE_FALLING: 79 case IRQ_TYPE_EDGE_FALLING:
72 if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq)) /* only supported on external interrupts */ 80 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
73 srctype = AT91_AIC_SRCTYPE_FALLING; 81 srctype = AT91_AIC_SRCTYPE_FALLING;
74 else 82 else
75 return -EINVAL; 83 return -EINVAL;
@@ -78,8 +86,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
78 return -EINVAL; 86 return -EINVAL;
79 } 87 }
80 88
81 smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE; 89 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
82 at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype); 90 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
83 return 0; 91 return 0;
84} 92}
85 93
@@ -90,13 +98,13 @@ static u32 backups;
90 98
91static int at91_aic_set_wake(struct irq_data *d, unsigned value) 99static int at91_aic_set_wake(struct irq_data *d, unsigned value)
92{ 100{
93 if (unlikely(d->irq >= 32)) 101 if (unlikely(d->hwirq >= NR_AIC_IRQS))
94 return -EINVAL; 102 return -EINVAL;
95 103
96 if (value) 104 if (value)
97 wakeups |= (1 << d->irq); 105 wakeups |= (1 << d->hwirq);
98 else 106 else
99 wakeups &= ~(1 << d->irq); 107 wakeups &= ~(1 << d->hwirq);
100 108
101 return 0; 109 return 0;
102} 110}
@@ -127,46 +135,112 @@ static struct irq_chip at91_aic_chip = {
127 .irq_set_wake = at91_aic_set_wake, 135 .irq_set_wake = at91_aic_set_wake,
128}; 136};
129 137
138static void __init at91_aic_hw_init(unsigned int spu_vector)
139{
140 int i;
141
142 /*
143 * Perform 8 End Of Interrupt Command to make sure AIC
144 * will not Lock out nIRQ
145 */
146 for (i = 0; i < 8; i++)
147 at91_aic_write(AT91_AIC_EOICR, 0);
148
149 /*
150 * Spurious Interrupt ID in Spurious Vector Register.
151 * When there is no current interrupt, the IRQ Vector Register
152 * reads the value stored in AIC_SPU
153 */
154 at91_aic_write(AT91_AIC_SPU, spu_vector);
155
156 /* No debugging in AIC: Debug (Protect) Control Register */
157 at91_aic_write(AT91_AIC_DCR, 0);
158
159 /* Disable and clear all interrupts initially */
160 at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
161 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
162}
163
164#if defined(CONFIG_OF)
165static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
166 irq_hw_number_t hw)
167{
168 /* Put virq number in Source Vector Register */
169 at91_aic_write(AT91_AIC_SVR(hw), virq);
170
171 /* Active Low interrupt, without priority */
172 at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
173
174 irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
175 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
176
177 return 0;
178}
179
180static struct irq_domain_ops at91_aic_irq_ops = {
181 .map = at91_aic_irq_map,
182 .xlate = irq_domain_xlate_twocell,
183};
184
185int __init at91_aic_of_init(struct device_node *node,
186 struct device_node *parent)
187{
188 at91_aic_base = of_iomap(node, 0);
189 at91_aic_np = node;
190
191 at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS,
192 &at91_aic_irq_ops, NULL);
193 if (!at91_aic_domain)
194 panic("Unable to add AIC irq domain (DT)\n");
195
196 irq_set_default_host(at91_aic_domain);
197
198 at91_aic_hw_init(NR_AIC_IRQS);
199
200 return 0;
201}
202#endif
203
130/* 204/*
131 * Initialize the AIC interrupt controller. 205 * Initialize the AIC interrupt controller.
132 */ 206 */
133void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) 207void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
134{ 208{
135 unsigned int i; 209 unsigned int i;
210 int irq_base;
136 211
137 at91_aic_base = ioremap(AT91_AIC, 512); 212 at91_aic_base = ioremap(AT91_AIC, 512);
138
139 if (!at91_aic_base) 213 if (!at91_aic_base)
140 panic("Impossible to ioremap AT91_AIC\n"); 214 panic("Unable to ioremap AIC registers\n");
215
216 /* Add irq domain for AIC */
217 irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
218 if (irq_base < 0) {
219 WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
220 irq_base = 0;
221 }
222 at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
223 irq_base, 0,
224 &irq_domain_simple_ops, NULL);
225
226 if (!at91_aic_domain)
227 panic("Unable to add AIC irq domain\n");
228
229 irq_set_default_host(at91_aic_domain);
141 230
142 /* 231 /*
143 * The IVR is used by macro get_irqnr_and_base to read and verify. 232 * The IVR is used by macro get_irqnr_and_base to read and verify.
144 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. 233 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
145 */ 234 */
146 for (i = 0; i < NR_AIC_IRQS; i++) { 235 for (i = 0; i < NR_AIC_IRQS; i++) {
147 /* Put irq number in Source Vector Register: */ 236 /* Put hardware irq number in Source Vector Register: */
148 at91_aic_write(AT91_AIC_SVR(i), i); 237 at91_aic_write(AT91_AIC_SVR(i), i);
149 /* Active Low interrupt, with the specified priority */ 238 /* Active Low interrupt, with the specified priority */
150 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); 239 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
151 240
152 irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); 241 irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
153 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 242 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
154
155 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
156 if (i < 8)
157 at91_aic_write(AT91_AIC_EOICR, 0);
158 } 243 }
159 244
160 /* 245 at91_aic_hw_init(NR_AIC_IRQS);
161 * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
162 * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
163 */
164 at91_aic_write(AT91_AIC_SPU, NR_AIC_IRQS);
165
166 /* No debugging in AIC: Debug (Protect) Control Register */
167 at91_aic_write(AT91_AIC_DCR, 0);
168
169 /* Disable and clear all interrupts initially */
170 at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
171 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
172} 246}
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index d554e6771b4e..6c9d5e69ac28 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -136,7 +136,7 @@ static int at91_pm_verify_clocks(void)
136 unsigned long scsr; 136 unsigned long scsr;
137 int i; 137 int i;
138 138
139 scsr = at91_sys_read(AT91_PMC_SCSR); 139 scsr = at91_pmc_read(AT91_PMC_SCSR);
140 140
141 /* USB must not be using PLLB */ 141 /* USB must not be using PLLB */
142 if (cpu_is_at91rm9200()) { 142 if (cpu_is_at91rm9200()) {
@@ -160,7 +160,7 @@ static int at91_pm_verify_clocks(void)
160 if ((scsr & (AT91_PMC_PCK0 << i)) == 0) 160 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
161 continue; 161 continue;
162 162
163 css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; 163 css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
164 if (css != AT91_PMC_CSS_SLOW) { 164 if (css != AT91_PMC_CSS_SLOW) {
165 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); 165 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
166 return 0; 166 return 0;
@@ -188,13 +188,27 @@ int at91_suspend_entering_slow_clock(void)
188EXPORT_SYMBOL(at91_suspend_entering_slow_clock); 188EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
189 189
190 190
191static void (*slow_clock)(void); 191static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
192 void __iomem *ramc1, int memctrl);
192 193
193#ifdef CONFIG_AT91_SLOW_CLOCK 194#ifdef CONFIG_AT91_SLOW_CLOCK
194extern void at91_slow_clock(void); 195extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
196 void __iomem *ramc1, int memctrl);
195extern u32 at91_slow_clock_sz; 197extern u32 at91_slow_clock_sz;
196#endif 198#endif
197 199
200void __iomem *at91_ramc_base[2];
201
202void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
203{
204 if (id < 0 || id > 1) {
205 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
206 BUG();
207 }
208 at91_ramc_base[id] = ioremap(addr, size);
209 if (!at91_ramc_base[id])
210 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
211}
198 212
199static int at91_pm_enter(suspend_state_t state) 213static int at91_pm_enter(suspend_state_t state)
200{ 214{
@@ -203,7 +217,7 @@ static int at91_pm_enter(suspend_state_t state)
203 217
204 pr_debug("AT91: PM - wake mask %08x, pm state %d\n", 218 pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
205 /* remember all the always-wake irqs */ 219 /* remember all the always-wake irqs */
206 (at91_sys_read(AT91_PMC_PCSR) 220 (at91_pmc_read(AT91_PMC_PCSR)
207 | (1 << AT91_ID_FIQ) 221 | (1 << AT91_ID_FIQ)
208 | (1 << AT91_ID_SYS) 222 | (1 << AT91_ID_SYS)
209 | (at91_extern_irq)) 223 | (at91_extern_irq))
@@ -228,11 +242,18 @@ static int at91_pm_enter(suspend_state_t state)
228 * turning off the main oscillator; reverse on wakeup. 242 * turning off the main oscillator; reverse on wakeup.
229 */ 243 */
230 if (slow_clock) { 244 if (slow_clock) {
245 int memctrl = AT91_MEMCTRL_SDRAMC;
246
247 if (cpu_is_at91rm9200())
248 memctrl = AT91_MEMCTRL_MC;
249 else if (cpu_is_at91sam9g45())
250 memctrl = AT91_MEMCTRL_DDRSDR;
231#ifdef CONFIG_AT91_SLOW_CLOCK 251#ifdef CONFIG_AT91_SLOW_CLOCK
232 /* copy slow_clock handler to SRAM, and call it */ 252 /* copy slow_clock handler to SRAM, and call it */
233 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); 253 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
234#endif 254#endif
235 slow_clock(); 255 slow_clock(at91_pmc_base, at91_ramc_base[0],
256 at91_ramc_base[1], memctrl);
236 break; 257 break;
237 } else { 258 } else {
238 pr_info("AT91: PM - no slow clock mode enabled ...\n"); 259 pr_info("AT91: PM - no slow clock mode enabled ...\n");
@@ -301,7 +322,7 @@ static int __init at91_pm_init(void)
301 322
302#ifdef CONFIG_ARCH_AT91RM9200 323#ifdef CONFIG_ARCH_AT91RM9200
303 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ 324 /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
304 at91_sys_write(AT91_SDRAMC_LPR, 0); 325 at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
305#endif 326#endif
306 327
307 suspend_set_ops(&at91_pm_ops); 328 suspend_set_ops(&at91_pm_ops);
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index bba9ce1aaaec..89f56f3a802e 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -11,8 +11,9 @@
11#ifndef __ARCH_ARM_MACH_AT91_PM 11#ifndef __ARCH_ARM_MACH_AT91_PM
12#define __ARCH_ARM_MACH_AT91_PM 12#define __ARCH_ARM_MACH_AT91_PM
13 13
14#include <mach/at91_ramc.h>
14#ifdef CONFIG_ARCH_AT91RM9200 15#ifdef CONFIG_ARCH_AT91RM9200
15#include <mach/at91rm9200_mc.h> 16#include <mach/at91rm9200_sdramc.h>
16 17
17/* 18/*
18 * The AT91RM9200 goes into self-refresh mode with this command, and will 19 * The AT91RM9200 goes into self-refresh mode with this command, and will
@@ -26,7 +27,7 @@
26 27
27static inline void at91rm9200_standby(void) 28static inline void at91rm9200_standby(void)
28{ 29{
29 u32 lpr = at91_sys_read(AT91_SDRAMC_LPR); 30 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
30 31
31 asm volatile( 32 asm volatile(
32 "b 1f\n\t" 33 "b 1f\n\t"
@@ -37,15 +38,14 @@ static inline void at91rm9200_standby(void)
37 " mcr p15, 0, %0, c7, c0, 4\n\t" 38 " mcr p15, 0, %0, c7, c0, 4\n\t"
38 " str %5, [%1, %2]" 39 " str %5, [%1, %2]"
39 : 40 :
40 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91_SDRAMC_LPR), 41 : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
41 "r" (1), "r" (AT91_SDRAMC_SRR), 42 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
42 "r" (lpr)); 43 "r" (lpr));
43} 44}
44 45
45#define at91_standby at91rm9200_standby 46#define at91_standby at91rm9200_standby
46 47
47#elif defined(CONFIG_ARCH_AT91SAM9G45) 48#elif defined(CONFIG_ARCH_AT91SAM9G45)
48#include <mach/at91sam9_ddrsdr.h>
49 49
50/* We manage both DDRAM/SDRAM controllers, we need more than one value to 50/* We manage both DDRAM/SDRAM controllers, we need more than one value to
51 * remember. 51 * remember.
@@ -78,7 +78,6 @@ static inline void at91sam9g45_standby(void)
78#define at91_standby at91sam9g45_standby 78#define at91_standby at91sam9g45_standby
79 79
80#else 80#else
81#include <mach/at91sam9_sdramc.h>
82 81
83#ifdef CONFIG_ARCH_AT91SAM9263 82#ifdef CONFIG_ARCH_AT91SAM9263
84/* 83/*
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index f8539a8bcd6c..db5452123f17 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -15,14 +15,7 @@
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <mach/at91_pmc.h> 17#include <mach/at91_pmc.h>
18 18#include <mach/at91_ramc.h>
19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91SAM9G45)
22#include <mach/at91sam9_ddrsdr.h>
23#else
24#include <mach/at91sam9_sdramc.h>
25#endif
26 19
27 20
28#ifdef CONFIG_ARCH_AT91SAM9263 21#ifdef CONFIG_ARCH_AT91SAM9263
@@ -46,17 +39,23 @@
46#define PLLALOCK_TIMEOUT 1000 39#define PLLALOCK_TIMEOUT 1000
47#define PLLBLOCK_TIMEOUT 1000 40#define PLLBLOCK_TIMEOUT 1000
48 41
42pmc .req r0
43sdramc .req r1
44ramc1 .req r2
45memctrl .req r3
46tmp1 .req r4
47tmp2 .req r5
49 48
50/* 49/*
51 * Wait until master clock is ready (after switching master clock source) 50 * Wait until master clock is ready (after switching master clock source)
52 */ 51 */
53 .macro wait_mckrdy 52 .macro wait_mckrdy
54 mov r4, #MCKRDY_TIMEOUT 53 mov tmp2, #MCKRDY_TIMEOUT
551: sub r4, r4, #1 541: sub tmp2, tmp2, #1
56 cmp r4, #0 55 cmp tmp2, #0
57 beq 2f 56 beq 2f
58 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] 57 ldr tmp1, [pmc, #AT91_PMC_SR]
59 tst r3, #AT91_PMC_MCKRDY 58 tst tmp1, #AT91_PMC_MCKRDY
60 beq 1b 59 beq 1b
612: 602:
62 .endm 61 .endm
@@ -65,12 +64,12 @@
65 * Wait until master oscillator has stabilized. 64 * Wait until master oscillator has stabilized.
66 */ 65 */
67 .macro wait_moscrdy 66 .macro wait_moscrdy
68 mov r4, #MOSCRDY_TIMEOUT 67 mov tmp2, #MOSCRDY_TIMEOUT
691: sub r4, r4, #1 681: sub tmp2, tmp2, #1
70 cmp r4, #0 69 cmp tmp2, #0
71 beq 2f 70 beq 2f
72 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] 71 ldr tmp1, [pmc, #AT91_PMC_SR]
73 tst r3, #AT91_PMC_MOSCS 72 tst tmp1, #AT91_PMC_MOSCS
74 beq 1b 73 beq 1b
752: 742:
76 .endm 75 .endm
@@ -79,12 +78,12 @@
79 * Wait until PLLA has locked. 78 * Wait until PLLA has locked.
80 */ 79 */
81 .macro wait_pllalock 80 .macro wait_pllalock
82 mov r4, #PLLALOCK_TIMEOUT 81 mov tmp2, #PLLALOCK_TIMEOUT
831: sub r4, r4, #1 821: sub tmp2, tmp2, #1
84 cmp r4, #0 83 cmp tmp2, #0
85 beq 2f 84 beq 2f
86 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] 85 ldr tmp1, [pmc, #AT91_PMC_SR]
87 tst r3, #AT91_PMC_LOCKA 86 tst tmp1, #AT91_PMC_LOCKA
88 beq 1b 87 beq 1b
892: 882:
90 .endm 89 .endm
@@ -93,79 +92,98 @@
93 * Wait until PLLB has locked. 92 * Wait until PLLB has locked.
94 */ 93 */
95 .macro wait_pllblock 94 .macro wait_pllblock
96 mov r4, #PLLBLOCK_TIMEOUT 95 mov tmp2, #PLLBLOCK_TIMEOUT
971: sub r4, r4, #1 961: sub tmp2, tmp2, #1
98 cmp r4, #0 97 cmp tmp2, #0
99 beq 2f 98 beq 2f
100 ldr r3, [r1, #(AT91_PMC_SR - AT91_PMC)] 99 ldr tmp1, [pmc, #AT91_PMC_SR]
101 tst r3, #AT91_PMC_LOCKB 100 tst tmp1, #AT91_PMC_LOCKB
102 beq 1b 101 beq 1b
1032: 1022:
104 .endm 103 .endm
105 104
106 .text 105 .text
107 106
107/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
108 * void __iomem *ramc1, int memctrl)
109 */
108ENTRY(at91_slow_clock) 110ENTRY(at91_slow_clock)
109 /* Save registers on stack */ 111 /* Save registers on stack */
110 stmfd sp!, {r0 - r12, lr} 112 stmfd sp!, {r4 - r12, lr}
111 113
112 /* 114 /*
113 * Register usage: 115 * Register usage:
114 * R1 = Base address of AT91_PMC 116 * R0 = Base address of AT91_PMC
115 * R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS) 117 * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
116 * R3 = temporary register 118 * R2 = Base address of second RAM Controller or 0 if not present
119 * R3 = Memory controller
117 * R4 = temporary register 120 * R4 = temporary register
118 * R5 = Base address of second RAM Controller or 0 if not present 121 * R5 = temporary register
119 */ 122 */
120 ldr r1, .at91_va_base_pmc
121 ldr r2, .at91_va_base_sdramc
122 ldr r5, .at91_va_base_ramc1
123 123
124 /* Drain write buffer */ 124 /* Drain write buffer */
125 mov r0, #0 125 mov tmp1, #0
126 mcr p15, 0, r0, c7, c10, 4 126 mcr p15, 0, tmp1, c7, c10, 4
127
128 cmp memctrl, #AT91_MEMCTRL_MC
129 bne ddr_sr_enable
127 130
128#ifdef CONFIG_ARCH_AT91RM9200 131 /*
132 * at91rm9200 Memory controller
133 */
129 /* Put SDRAM in self-refresh mode */ 134 /* Put SDRAM in self-refresh mode */
130 mov r3, #1 135 mov tmp1, #1
131 str r3, [r2, #AT91_SDRAMC_SRR] 136 str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
132#elif defined(CONFIG_ARCH_AT91SAM9G45) 137 b sdr_sr_done
138
139 /*
140 * DDRSDR Memory controller
141 */
142ddr_sr_enable:
143 cmp memctrl, #AT91_MEMCTRL_DDRSDR
144 bne sdr_sr_enable
133 145
134 /* prepare for DDRAM self-refresh mode */ 146 /* prepare for DDRAM self-refresh mode */
135 ldr r3, [r2, #AT91_DDRSDRC_LPR] 147 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
136 str r3, .saved_sam9_lpr 148 str tmp1, .saved_sam9_lpr
137 bic r3, #AT91_DDRSDRC_LPCB 149 bic tmp1, #AT91_DDRSDRC_LPCB
138 orr r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH 150 orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
139 151
140 /* figure out if we use the second ram controller */ 152 /* figure out if we use the second ram controller */
141 cmp r5, #0 153 cmp ramc1, #0
142 ldrne r4, [r5, #AT91_DDRSDRC_LPR] 154 ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
143 strne r4, .saved_sam9_lpr1 155 strne tmp2, .saved_sam9_lpr1
144 bicne r4, #AT91_DDRSDRC_LPCB 156 bicne tmp2, #AT91_DDRSDRC_LPCB
145 orrne r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH 157 orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
146 158
147 /* Enable DDRAM self-refresh mode */ 159 /* Enable DDRAM self-refresh mode */
148 str r3, [r2, #AT91_DDRSDRC_LPR] 160 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
149 strne r4, [r5, #AT91_DDRSDRC_LPR] 161 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
150#else 162
163 b sdr_sr_done
164
165 /*
166 * SDRAMC Memory controller
167 */
168sdr_sr_enable:
151 /* Enable SDRAM self-refresh mode */ 169 /* Enable SDRAM self-refresh mode */
152 ldr r3, [r2, #AT91_SDRAMC_LPR] 170 ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
153 str r3, .saved_sam9_lpr 171 str tmp1, .saved_sam9_lpr
154 172
155 bic r3, #AT91_SDRAMC_LPCB 173 bic tmp1, #AT91_SDRAMC_LPCB
156 orr r3, #AT91_SDRAMC_LPCB_SELF_REFRESH 174 orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
157 str r3, [r2, #AT91_SDRAMC_LPR] 175 str tmp1, [sdramc, #AT91_SDRAMC_LPR]
158#endif
159 176
177sdr_sr_done:
160 /* Save Master clock setting */ 178 /* Save Master clock setting */
161 ldr r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 179 ldr tmp1, [pmc, #AT91_PMC_MCKR]
162 str r3, .saved_mckr 180 str tmp1, .saved_mckr
163 181
164 /* 182 /*
165 * Set the Master clock source to slow clock 183 * Set the Master clock source to slow clock
166 */ 184 */
167 bic r3, r3, #AT91_PMC_CSS 185 bic tmp1, tmp1, #AT91_PMC_CSS
168 str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 186 str tmp1, [pmc, #AT91_PMC_MCKR]
169 187
170 wait_mckrdy 188 wait_mckrdy
171 189
@@ -175,61 +193,61 @@ ENTRY(at91_slow_clock)
175 * 193 *
176 * See AT91RM9200 errata #27 and #28 for details. 194 * See AT91RM9200 errata #27 and #28 for details.
177 */ 195 */
178 mov r3, #0 196 mov tmp1, #0
179 str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 197 str tmp1, [pmc, #AT91_PMC_MCKR]
180 198
181 wait_mckrdy 199 wait_mckrdy
182#endif 200#endif
183 201
184 /* Save PLLA setting and disable it */ 202 /* Save PLLA setting and disable it */
185 ldr r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] 203 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
186 str r3, .saved_pllar 204 str tmp1, .saved_pllar
187 205
188 mov r3, #AT91_PMC_PLLCOUNT 206 mov tmp1, #AT91_PMC_PLLCOUNT
189 orr r3, r3, #(1 << 29) /* bit 29 always set */ 207 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
190 str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] 208 str tmp1, [pmc, #AT91_CKGR_PLLAR]
191 209
192 /* Save PLLB setting and disable it */ 210 /* Save PLLB setting and disable it */
193 ldr r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 211 ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
194 str r3, .saved_pllbr 212 str tmp1, .saved_pllbr
195 213
196 mov r3, #AT91_PMC_PLLCOUNT 214 mov tmp1, #AT91_PMC_PLLCOUNT
197 str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 215 str tmp1, [pmc, #AT91_CKGR_PLLBR]
198 216
199 /* Turn off the main oscillator */ 217 /* Turn off the main oscillator */
200 ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 218 ldr tmp1, [pmc, #AT91_CKGR_MOR]
201 bic r3, r3, #AT91_PMC_MOSCEN 219 bic tmp1, tmp1, #AT91_PMC_MOSCEN
202 str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 220 str tmp1, [pmc, #AT91_CKGR_MOR]
203 221
204 /* Wait for interrupt */ 222 /* Wait for interrupt */
205 mcr p15, 0, r0, c7, c0, 4 223 mcr p15, 0, tmp1, c7, c0, 4
206 224
207 /* Turn on the main oscillator */ 225 /* Turn on the main oscillator */
208 ldr r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 226 ldr tmp1, [pmc, #AT91_CKGR_MOR]
209 orr r3, r3, #AT91_PMC_MOSCEN 227 orr tmp1, tmp1, #AT91_PMC_MOSCEN
210 str r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)] 228 str tmp1, [pmc, #AT91_CKGR_MOR]
211 229
212 wait_moscrdy 230 wait_moscrdy
213 231
214 /* Restore PLLB setting */ 232 /* Restore PLLB setting */
215 ldr r3, .saved_pllbr 233 ldr tmp1, .saved_pllbr
216 str r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)] 234 str tmp1, [pmc, #AT91_CKGR_PLLBR]
217 235
218 tst r3, #(AT91_PMC_MUL & 0xff0000) 236 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
219 bne 1f 237 bne 1f
220 tst r3, #(AT91_PMC_MUL & ~0xff0000) 238 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
221 beq 2f 239 beq 2f
2221: 2401:
223 wait_pllblock 241 wait_pllblock
2242: 2422:
225 243
226 /* Restore PLLA setting */ 244 /* Restore PLLA setting */
227 ldr r3, .saved_pllar 245 ldr tmp1, .saved_pllar
228 str r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)] 246 str tmp1, [pmc, #AT91_CKGR_PLLAR]
229 247
230 tst r3, #(AT91_PMC_MUL & 0xff0000) 248 tst tmp1, #(AT91_PMC_MUL & 0xff0000)
231 bne 3f 249 bne 3f
232 tst r3, #(AT91_PMC_MUL & ~0xff0000) 250 tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
233 beq 4f 251 beq 4f
2343: 2523:
235 wait_pllalock 253 wait_pllalock
@@ -242,11 +260,11 @@ ENTRY(at91_slow_clock)
242 * 260 *
243 * See AT91RM9200 errata #27 and #28 for details. 261 * See AT91RM9200 errata #27 and #28 for details.
244 */ 262 */
245 ldr r3, .saved_mckr 263 ldr tmp1, .saved_mckr
246 tst r3, #AT91_PMC_PRES 264 tst tmp1, #AT91_PMC_PRES
247 beq 2f 265 beq 2f
248 and r3, r3, #AT91_PMC_PRES 266 and tmp1, tmp1, #AT91_PMC_PRES
249 str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 267 str tmp1, [pmc, #AT91_PMC_MCKR]
250 268
251 wait_mckrdy 269 wait_mckrdy
252#endif 270#endif
@@ -254,31 +272,45 @@ ENTRY(at91_slow_clock)
254 /* 272 /*
255 * Restore master clock setting 273 * Restore master clock setting
256 */ 274 */
2572: ldr r3, .saved_mckr 2752: ldr tmp1, .saved_mckr
258 str r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)] 276 str tmp1, [pmc, #AT91_PMC_MCKR]
259 277
260 wait_mckrdy 278 wait_mckrdy
261 279
262#ifdef CONFIG_ARCH_AT91RM9200 280 /*
263 /* Do nothing - self-refresh is automatically disabled. */ 281 * at91rm9200 Memory controller
264#elif defined(CONFIG_ARCH_AT91SAM9G45) 282 * Do nothing - self-refresh is automatically disabled.
283 */
284 cmp memctrl, #AT91_MEMCTRL_MC
285 beq ram_restored
286
287 /*
288 * DDRSDR Memory controller
289 */
290 cmp memctrl, #AT91_MEMCTRL_DDRSDR
291 bne sdr_en_restore
265 /* Restore LPR on AT91 with DDRAM */ 292 /* Restore LPR on AT91 with DDRAM */
266 ldr r3, .saved_sam9_lpr 293 ldr tmp1, .saved_sam9_lpr
267 str r3, [r2, #AT91_DDRSDRC_LPR] 294 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
268 295
269 /* if we use the second ram controller */ 296 /* if we use the second ram controller */
270 cmp r5, #0 297 cmp ramc1, #0
271 ldrne r4, .saved_sam9_lpr1 298 ldrne tmp2, .saved_sam9_lpr1
272 strne r4, [r5, #AT91_DDRSDRC_LPR] 299 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
300
301 b ram_restored
273 302
274#else 303 /*
304 * SDRAMC Memory controller
305 */
306sdr_en_restore:
275 /* Restore LPR on AT91 with SDRAM */ 307 /* Restore LPR on AT91 with SDRAM */
276 ldr r3, .saved_sam9_lpr 308 ldr tmp1, .saved_sam9_lpr
277 str r3, [r2, #AT91_SDRAMC_LPR] 309 str tmp1, [sdramc, #AT91_SDRAMC_LPR]
278#endif
279 310
311ram_restored:
280 /* Restore registers, and return */ 312 /* Restore registers, and return */
281 ldmfd sp!, {r0 - r12, pc} 313 ldmfd sp!, {r4 - r12, pc}
282 314
283 315
284.saved_mckr: 316.saved_mckr:
@@ -296,26 +328,5 @@ ENTRY(at91_slow_clock)
296.saved_sam9_lpr1: 328.saved_sam9_lpr1:
297 .word 0 329 .word 0
298 330
299.at91_va_base_pmc:
300 .word AT91_VA_BASE_SYS + AT91_PMC
301
302#ifdef CONFIG_ARCH_AT91RM9200
303.at91_va_base_sdramc:
304 .word AT91_VA_BASE_SYS
305#elif defined(CONFIG_ARCH_AT91SAM9G45)
306.at91_va_base_sdramc:
307 .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
308#else
309.at91_va_base_sdramc:
310 .word AT91_VA_BASE_SYS + AT91_SDRAMC0
311#endif
312
313.at91_va_base_ramc1:
314#if defined(CONFIG_ARCH_AT91SAM9G45)
315 .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
316#else
317 .word 0
318#endif
319
320ENTRY(at91_slow_clock_sz) 331ENTRY(at91_slow_clock_sz)
321 .word .-at91_slow_clock 332 .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 620c67e8f814..372396c2ecb6 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -276,6 +276,15 @@ void __init at91_ioremap_rstc(u32 base_addr)
276 panic("Impossible to ioremap at91_rstc_base\n"); 276 panic("Impossible to ioremap at91_rstc_base\n");
277} 277}
278 278
279void __iomem *at91_matrix_base;
280
281void __init at91_ioremap_matrix(u32 base_addr)
282{
283 at91_matrix_base = ioremap(base_addr, 512);
284 if (!at91_matrix_base)
285 panic("Impossible to ioremap at91_matrix_base\n");
286}
287
279void __init at91_initialize(unsigned long main_clock) 288void __init at91_initialize(unsigned long main_clock)
280{ 289{
281 at91_boot_soc.ioremap_registers(); 290 at91_boot_soc.ioremap_registers();
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 21:13:42 -0400