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-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h112
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h30
-rw-r--r--arch/arm/mach-at91/pm.h8
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S5
4 files changed, 26 insertions, 129 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
deleted file mode 100644
index d21932dcd6fa..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
3 *
4 * (C) 2008 Andrew Victor
5 *
6 * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
7 * Based on AT91CAP9 datasheet revision B.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H
17
18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1
22#define AT91_DDRSDRC_MODE_PRECHARGE 2
23#define AT91_DDRSDRC_MODE_LMR 3
24#define AT91_DDRSDRC_MODE_REFRESH 4
25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6
27
28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30
31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
35#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
36#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
37#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
38#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
39#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
40#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
41#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
42#define AT91_DDRSDRC_NR_11 (0 << 2)
43#define AT91_DDRSDRC_NR_12 (1 << 2)
44#define AT91_DDRSDRC_NR_13 (2 << 2)
45#define AT91_DDRSDRC_NR_14 (3 << 2)
46#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
47#define AT91_DDRSDRC_CAS_2 (2 << 4)
48#define AT91_DDRSDRC_CAS_3 (3 << 4)
49#define AT91_DDRSDRC_CAS_25 (6 << 4)
50#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
51#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
52
53#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
54#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
55#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
56#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
57#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
58#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
59#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
60#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
61#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
62
63#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
64#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
65#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
66#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
67#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
68
69#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
70#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
71#define AT91_DDRSDRC_LPCB_DISABLE 0
72#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
73#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
74#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
75#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
76#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
77#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
78#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
79#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
80#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
81#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
82#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
83
84#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
85#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
86#define AT91_DDRSDRC_MD_SDR 0
87#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
88#define AT91_DDRSDRC_MD_DDR 2
89#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
90#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
91#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
92#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
93
94#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
95#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
96#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
97#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
98#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
99#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
100#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
101#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
102#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
103#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
104
105/* Register access macros */
106#define at91_ramc_read(num, reg) \
107 at91_sys_read(AT91_DDRSDRC##num + reg)
108#define at91_ramc_write(num, reg, value) \
109 at91_sys_write(AT91_DDRSDRC##num + reg, value)
110
111
112#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index d27b15ba8ebf..e2f8da8ce5bc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -46,10 +46,10 @@
46#define AT91_DDRSDRC_CAS_25 (6 << 4) 46#define AT91_DDRSDRC_CAS_25 (6 << 4)
47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ 47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */ 49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */ 50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */ 51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */ 52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
53 53
54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ 54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
@@ -59,7 +59,8 @@
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ 60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */ 62#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
63#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 64#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
64 65
65#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ 66#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
@@ -68,13 +69,14 @@
68#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 69#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 70#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
70 71
71#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */ 72#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
72#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ 73#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
73#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ 74#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
74#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ 75#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ 76#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
76 77
77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ 78#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
79#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 80#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
79#define AT91_DDRSDRC_LPCB_DISABLE 0 81#define AT91_DDRSDRC_LPCB_DISABLE 0
80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 82#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -92,32 +94,40 @@
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 94#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93 95
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 96#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
97#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 98#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0 99#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 100#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
101#define AT91CAP9_DDRSDRC_MD_DDR 2
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 102#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
99#define AT91_DDRSDRC_MD_DDR2 6 103#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ 104#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
101#define AT91_DDRSDRC_DBW_32BITS (0 << 4) 105#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
102#define AT91_DDRSDRC_DBW_16BITS (1 << 4) 106#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
103 107
104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ 108#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
109#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 110#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 111#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 112#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
113#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
114#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
115#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ 116#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
117#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
118#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
109 119
110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */ 120#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ 121#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
112 122
113#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ 123#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
114 124
115#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */ 125#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
116#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ 126#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
117#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ 127#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
118#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ 128#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119 129
120#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */ 130#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ 131#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ 132#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123 133
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index ce9a20699111..7eb40d24242f 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void)
25 : : "r" (0)) 25 : : "r" (0))
26 26
27#elif defined(CONFIG_ARCH_AT91CAP9) 27#elif defined(CONFIG_ARCH_AT91CAP9)
28#include <mach/at91cap9_ddrsdr.h> 28#include <mach/at91sam9_ddrsdr.h>
29 29
30 30
31static inline u32 sdram_selfrefresh_enable(void) 31static inline u32 sdram_selfrefresh_enable(void)
32{ 32{
33 u32 saved_lpr, lpr; 33 u32 saved_lpr, lpr;
34 34
35 saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); 35 saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
36 36
37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB; 37 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
38 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH); 38 at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
39 return saved_lpr; 39 return saved_lpr;
40} 40}
41 41
42#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr) 42#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
43#define wait_for_interrupt_enable() cpu_do_idle() 43#define wait_for_interrupt_enable() cpu_do_idle()
44 44
45#elif defined(CONFIG_ARCH_AT91SAM9G45) 45#elif defined(CONFIG_ARCH_AT91SAM9G45)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index f7922a436172..92dfb8461392 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -18,9 +18,8 @@
18 18
19#if defined(CONFIG_ARCH_AT91RM9200) 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <mach/at91rm9200_mc.h> 20#include <mach/at91rm9200_mc.h>
21#elif defined(CONFIG_ARCH_AT91CAP9) 21#elif defined(CONFIG_ARCH_AT91CAP9) \
22#include <mach/at91cap9_ddrsdr.h> 22 || defined(CONFIG_ARCH_AT91SAM9G45)
23#elif defined(CONFIG_ARCH_AT91SAM9G45)
24#include <mach/at91sam9_ddrsdr.h> 23#include <mach/at91sam9_ddrsdr.h>
25#else 24#else
26#include <mach/at91sam9_sdramc.h> 25#include <mach/at91sam9_sdramc.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 08:59:43 -0500