aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-at91/include/mach
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-at91/include/mach')
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rstc.h18
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h108
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h30
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/board.h2
10 files changed, 42 insertions, 128 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
index cbd2bf052c1f..875fa336800b 100644
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -16,13 +16,25 @@
16#ifndef AT91_RSTC_H 16#ifndef AT91_RSTC_H
17#define AT91_RSTC_H 17#define AT91_RSTC_H
18 18
19#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ 19#ifndef __ASSEMBLY__
20extern void __iomem *at91_rstc_base;
21
22#define at91_rstc_read(field) \
23 __raw_readl(at91_rstc_base + field)
24
25#define at91_rstc_write(field, value) \
26 __raw_writel(value, at91_rstc_base + field);
27#else
28.extern at91_rstc_base
29#endif
30
31#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
20#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ 32#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
21#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ 33#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
22#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ 34#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
23#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ 35#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
24 36
25#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ 37#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
26#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ 38#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
27#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ 39#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
28#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) 40#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
@@ -33,7 +45,7 @@
33#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ 45#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
34#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ 46#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
35 47
36#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ 48#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
37#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ 49#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
38#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ 50#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
39#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ 51#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index 4c0e2f6011d7..61d952902f2b 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -83,7 +83,6 @@
83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 83#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 84#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
87#define AT91_GPBR (cpu_is_at91cap9_revB() ? \ 86#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
88 (0xfffffd50 - AT91_BASE_SYS) : \ 87 (0xfffffd50 - AT91_BASE_SYS) : \
89 (0xfffffd60 - AT91_BASE_SYS)) 88 (0xfffffd60 - AT91_BASE_SYS))
@@ -96,6 +95,7 @@
96#define AT91CAP9_BASE_PIOB 0xfffff400 95#define AT91CAP9_BASE_PIOB 0xfffff400
97#define AT91CAP9_BASE_PIOC 0xfffff600 96#define AT91CAP9_BASE_PIOC 0xfffff600
98#define AT91CAP9_BASE_PIOD 0xfffff800 97#define AT91CAP9_BASE_PIOD 0xfffff800
98#define AT91CAP9_BASE_RSTC 0xfffffd00
99#define AT91CAP9_BASE_SHDWC 0xfffffd10 99#define AT91CAP9_BASE_SHDWC 0xfffffd10
100#define AT91CAP9_BASE_RTT 0xfffffd20 100#define AT91CAP9_BASE_RTT 0xfffffd20
101#define AT91CAP9_BASE_PIT 0xfffffd30 101#define AT91CAP9_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
deleted file mode 100644
index 976f4a6c3353..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
3 *
4 * (C) 2008 Andrew Victor
5 *
6 * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
7 * Based on AT91CAP9 datasheet revision B.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91CAP9_DDRSDR_H
16#define AT91CAP9_DDRSDR_H
17
18#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
19#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
20#define AT91_DDRSDRC_MODE_NORMAL 0
21#define AT91_DDRSDRC_MODE_NOP 1
22#define AT91_DDRSDRC_MODE_PRECHARGE 2
23#define AT91_DDRSDRC_MODE_LMR 3
24#define AT91_DDRSDRC_MODE_REFRESH 4
25#define AT91_DDRSDRC_MODE_EXT_LMR 5
26#define AT91_DDRSDRC_MODE_DEEP 6
27
28#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
29#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
30
31#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
32#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
33#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
34#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
35#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
36#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
37#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
38#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
39#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
40#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
41#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
42#define AT91_DDRSDRC_NR_11 (0 << 2)
43#define AT91_DDRSDRC_NR_12 (1 << 2)
44#define AT91_DDRSDRC_NR_13 (2 << 2)
45#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
46#define AT91_DDRSDRC_CAS_2 (2 << 4)
47#define AT91_DDRSDRC_CAS_3 (3 << 4)
48#define AT91_DDRSDRC_CAS_25 (6 << 4)
49#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
50#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
51
52#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
53#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
54#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
55#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
56#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
57#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
58#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
59#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
60#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
61
62#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
63#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
64#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
65#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
66#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
67
68#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
69#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
70#define AT91_DDRSDRC_LPCB_DISABLE 0
71#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
72#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
73#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
74#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
75#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
76#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
77#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
78#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
79#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
80#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
81#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
82
83#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
84#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
85#define AT91_DDRSDRC_MD_SDR 0
86#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
87#define AT91_DDRSDRC_MD_DDR 2
88#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
89
90#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
91#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
92#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
93#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
94#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
95#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
96#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
97#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
98#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
99#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
100
101/* Register access macros */
102#define at91_ramc_read(num, reg) \
103 at91_sys_read(AT91_DDRSDRC##num + reg)
104#define at91_ramc_write(num, reg, value) \
105 at91_sys_write(AT91_DDRSDRC##num + reg, value)
106
107
108#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index f937c476bb67..fa5ca278adeb 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -83,7 +83,6 @@
83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 83#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 84#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
87#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 86#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
88 87
89#define AT91SAM9260_BASE_ECC 0xffffe800 88#define AT91SAM9260_BASE_ECC 0xffffe800
@@ -92,6 +91,7 @@
92#define AT91SAM9260_BASE_PIOA 0xfffff400 91#define AT91SAM9260_BASE_PIOA 0xfffff400
93#define AT91SAM9260_BASE_PIOB 0xfffff600 92#define AT91SAM9260_BASE_PIOB 0xfffff600
94#define AT91SAM9260_BASE_PIOC 0xfffff800 93#define AT91SAM9260_BASE_PIOC 0xfffff800
94#define AT91SAM9260_BASE_RSTC 0xfffffd00
95#define AT91SAM9260_BASE_SHDWC 0xfffffd10 95#define AT91SAM9260_BASE_SHDWC 0xfffffd10
96#define AT91SAM9260_BASE_RTT 0xfffffd20 96#define AT91SAM9260_BASE_RTT 0xfffffd20
97#define AT91SAM9260_BASE_PIT 0xfffffd30 97#define AT91SAM9260_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 175604e261be..7cde2d36570e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,6 @@
68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 68#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 69#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 70#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
71#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
72#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 71#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
73 72
74#define AT91SAM9261_BASE_SMC 0xffffec00 73#define AT91SAM9261_BASE_SMC 0xffffec00
@@ -76,6 +75,7 @@
76#define AT91SAM9261_BASE_PIOA 0xfffff400 75#define AT91SAM9261_BASE_PIOA 0xfffff400
77#define AT91SAM9261_BASE_PIOB 0xfffff600 76#define AT91SAM9261_BASE_PIOB 0xfffff600
78#define AT91SAM9261_BASE_PIOC 0xfffff800 77#define AT91SAM9261_BASE_PIOC 0xfffff800
78#define AT91SAM9261_BASE_RSTC 0xfffffd00
79#define AT91SAM9261_BASE_SHDWC 0xfffffd10 79#define AT91SAM9261_BASE_SHDWC 0xfffffd10
80#define AT91SAM9261_BASE_RTT 0xfffffd20 80#define AT91SAM9261_BASE_RTT 0xfffffd20
81#define AT91SAM9261_BASE_PIT 0xfffffd30 81#define AT91SAM9261_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 80c915002d83..5949abda962b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -78,7 +78,6 @@
78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) 78#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) 79#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 80#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
81#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
82#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 81#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
83 82
84#define AT91SAM9263_BASE_ECC0 0xffffe000 83#define AT91SAM9263_BASE_ECC0 0xffffe000
@@ -91,6 +90,7 @@
91#define AT91SAM9263_BASE_PIOC 0xfffff600 90#define AT91SAM9263_BASE_PIOC 0xfffff600
92#define AT91SAM9263_BASE_PIOD 0xfffff800 91#define AT91SAM9263_BASE_PIOD 0xfffff800
93#define AT91SAM9263_BASE_PIOE 0xfffffa00 92#define AT91SAM9263_BASE_PIOE 0xfffffa00
93#define AT91SAM9263_BASE_RSTC 0xfffffd00
94#define AT91SAM9263_BASE_SHDWC 0xfffffd10 94#define AT91SAM9263_BASE_SHDWC 0xfffffd10
95#define AT91SAM9263_BASE_RTT0 0xfffffd20 95#define AT91SAM9263_BASE_RTT0 0xfffffd20
96#define AT91SAM9263_BASE_PIT 0xfffffd30 96#define AT91SAM9263_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index d27b15ba8ebf..e2f8da8ce5bc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -46,10 +46,10 @@
46#define AT91_DDRSDRC_CAS_25 (6 << 4) 46#define AT91_DDRSDRC_CAS_25 (6 << 4)
47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ 47#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 48#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */ 49#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */ 50#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */ 51#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */ 52#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
53 53
54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ 54#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 55#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
@@ -59,7 +59,8 @@
59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 59#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ 60#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 61#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
62#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */ 62#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
63#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 64#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
64 65
65#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ 66#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
@@ -68,13 +69,14 @@
68#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 69#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
69#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 70#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
70 71
71#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */ 72#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
72#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ 73#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
73#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ 74#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
74#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ 75#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
75#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ 76#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
76 77
77#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ 78#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
79#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
78#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 80#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
79#define AT91_DDRSDRC_LPCB_DISABLE 0 81#define AT91_DDRSDRC_LPCB_DISABLE 0
80#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 82#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -92,32 +94,40 @@
92#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 94#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
93 95
94#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 96#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
97#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
95#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ 98#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
96#define AT91_DDRSDRC_MD_SDR 0 99#define AT91_DDRSDRC_MD_SDR 0
97#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 100#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
101#define AT91CAP9_DDRSDRC_MD_DDR 2
98#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 102#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
99#define AT91_DDRSDRC_MD_DDR2 6 103#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
100#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ 104#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
101#define AT91_DDRSDRC_DBW_32BITS (0 << 4) 105#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
102#define AT91_DDRSDRC_DBW_16BITS (1 << 4) 106#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
103 107
104#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ 108#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
109#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
105#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 110#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
106#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 111#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
107#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 112#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
113#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
114#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
115#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
108#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ 116#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
117#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
118#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
109 119
110#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */ 120#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
111#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ 121#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
112 122
113#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ 123#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
114 124
115#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */ 125#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
116#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ 126#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
117#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ 127#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
118#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ 128#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
119 129
120#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */ 130#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
121#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ 131#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
122#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ 132#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
123 133
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index f0c23c960dec..dd9c95ea0862 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -90,7 +90,6 @@
90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) 90#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) 91#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 92#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
93#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
94#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 93#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
95 94
96#define AT91SAM9G45_BASE_ECC 0xffffe200 95#define AT91SAM9G45_BASE_ECC 0xffffe200
@@ -102,6 +101,7 @@
102#define AT91SAM9G45_BASE_PIOC 0xfffff600 101#define AT91SAM9G45_BASE_PIOC 0xfffff600
103#define AT91SAM9G45_BASE_PIOD 0xfffff800 102#define AT91SAM9G45_BASE_PIOD 0xfffff800
104#define AT91SAM9G45_BASE_PIOE 0xfffffa00 103#define AT91SAM9G45_BASE_PIOE 0xfffffa00
104#define AT91SAM9G45_BASE_RSTC 0xfffffd00
105#define AT91SAM9G45_BASE_SHDWC 0xfffffd10 105#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
106#define AT91SAM9G45_BASE_RTT 0xfffffd20 106#define AT91SAM9G45_BASE_RTT 0xfffffd20
107#define AT91SAM9G45_BASE_PIT 0xfffffd30 107#define AT91SAM9G45_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 2bb359e60b97..d7bead7118da 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -72,7 +72,6 @@
72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS) 72#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) 73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 74#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
75#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
76#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 75#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
77#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 76#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
78 77
@@ -84,6 +83,7 @@
84#define AT91SAM9RL_BASE_PIOB 0xfffff600 83#define AT91SAM9RL_BASE_PIOB 0xfffff600
85#define AT91SAM9RL_BASE_PIOC 0xfffff800 84#define AT91SAM9RL_BASE_PIOC 0xfffff800
86#define AT91SAM9RL_BASE_PIOD 0xfffffa00 85#define AT91SAM9RL_BASE_PIOD 0xfffffa00
86#define AT91SAM9RL_BASE_RSTC 0xfffffd00
87#define AT91SAM9RL_BASE_SHDWC 0xfffffd10 87#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
88#define AT91SAM9RL_BASE_RTT 0xfffffd20 88#define AT91SAM9RL_BASE_RTT 0xfffffd20
89#define AT91SAM9RL_BASE_PIT 0xfffffd30 89#define AT91SAM9RL_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index d0b377b21bd7..3b33f07b1e11 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data);
88struct at91_usbh_data { 88struct at91_usbh_data {
89 u8 ports; /* number of ports on root hub */ 89 u8 ports; /* number of ports on root hub */
90 int vbus_pin[2]; /* port power-control pin */ 90 int vbus_pin[2]; /* port power-control pin */
91 u8 vbus_pin_inverted; 91 u8 vbus_pin_active_low[2];
92 u8 overcurrent_supported; 92 u8 overcurrent_supported;
93 int overcurrent_pin[2]; 93 int overcurrent_pin[2];
94 u8 overcurrent_status[2]; 94 u8 overcurrent_status[2];
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 21:36:51 -0500