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-rw-r--r--arch/arm/mach-at91/include/mach/at91_aic.h36
-rw-r--r--arch/arm/mach-at91/include/mach/at91_spi.h81
-rw-r--r--arch/arm/mach-at91/include/mach/at91_ssc.h106
-rw-r--r--arch/arm/mach-at91/include/mach/entry-macro.S27
-rw-r--r--arch/arm/mach-at91/include/mach/irqs.h48
5 files changed, 35 insertions, 263 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index 3045781c473f..eaea66197fa1 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -23,12 +23,23 @@ extern void __iomem *at91_aic_base;
23 __raw_readl(at91_aic_base + field) 23 __raw_readl(at91_aic_base + field)
24 24
25#define at91_aic_write(field, value) \ 25#define at91_aic_write(field, value) \
26 __raw_writel(value, at91_aic_base + field); 26 __raw_writel(value, at91_aic_base + field)
27#else 27#else
28.extern at91_aic_base 28.extern at91_aic_base
29#endif 29#endif
30 30
31/* Number of irq lines managed by AIC */
32#define NR_AIC_IRQS 32
33#define NR_AIC5_IRQS 128
34
35#define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */
36#define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */
37
38#define AT91_AIC_IRQ_MIN_PRIORITY 0
39#define AT91_AIC_IRQ_MAX_PRIORITY 7
40
31#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ 41#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
42#define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */
32#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ 43#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
33#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ 44#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
34#define AT91_AIC_SRCTYPE_LOW (0 << 5) 45#define AT91_AIC_SRCTYPE_LOW (0 << 5)
@@ -37,29 +48,52 @@ extern void __iomem *at91_aic_base;
37#define AT91_AIC_SRCTYPE_RISING (3 << 5) 48#define AT91_AIC_SRCTYPE_RISING (3 << 5)
38 49
39#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ 50#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
51#define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */
40#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ 52#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
53#define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */
41#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ 54#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
55#define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */
42#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ 56#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
57#define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */
43#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ 58#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
44 59
45#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ 60#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
61#define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */
62#define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */
63#define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */
64#define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */
46#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ 65#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
66#define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */
47#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ 67#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
68#define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */
48#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ 69#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
49#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ 70#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
50 71
51#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ 72#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
73#define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */
52#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ 74#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
75#define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */
53#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ 76#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
77#define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */
54#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ 78#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
79#define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */
55#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ 80#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
81#define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */
56#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ 82#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
83#define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */
57#define AT91_AIC_DCR 0x138 /* Debug Control Register */ 84#define AT91_AIC_DCR 0x138 /* Debug Control Register */
85#define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */
58#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ 86#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
59#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ 87#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
60 88
61#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ 89#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
90#define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */
62#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ 91#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
92#define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */
63#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ 93#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
94#define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */
95
96void at91_aic_handle_irq(struct pt_regs *regs);
97void at91_aic5_handle_irq(struct pt_regs *regs);
64 98
65#endif 99#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h
deleted file mode 100644
index 2f6ba0c5636e..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_spi.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_spi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Serial Peripheral Interface (SPI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_SPI_H
17#define AT91_SPI_H
18
19#define AT91_SPI_CR 0x00 /* Control Register */
20#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
21#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
22#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
23#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
24
25#define AT91_SPI_MR 0x04 /* Mode Register */
26#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
27#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
28#define AT91_SPI_PS_FIXED (0 << 1)
29#define AT91_SPI_PS_VARIABLE (1 << 1)
30#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
31#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
32#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
33#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
34#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
35#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
36
37#define AT91_SPI_RDR 0x08 /* Receive Data Register */
38#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
39#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
40
41#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
42#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
43#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
44#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
45
46#define AT91_SPI_SR 0x10 /* Status Register */
47#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
48#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
49#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
50#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
51#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
52#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
53#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
54#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
55#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
56#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
57#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
58
59#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
60#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
61#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
62
63#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
64#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
65#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
66#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
67#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
68#define AT91_SPI_BITS_8 (0 << 4)
69#define AT91_SPI_BITS_9 (1 << 4)
70#define AT91_SPI_BITS_10 (2 << 4)
71#define AT91_SPI_BITS_11 (3 << 4)
72#define AT91_SPI_BITS_12 (4 << 4)
73#define AT91_SPI_BITS_13 (5 << 4)
74#define AT91_SPI_BITS_14 (6 << 4)
75#define AT91_SPI_BITS_15 (7 << 4)
76#define AT91_SPI_BITS_16 (8 << 4)
77#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
78#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
79#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
80
81#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h
deleted file mode 100644
index a81114c11c74..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_ssc.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_ssc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Serial Synchronous Controller (SSC) registers.
7 * Based on AT91RM9200 datasheet revision E.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91_SSC_H
16#define AT91_SSC_H
17
18#define AT91_SSC_CR 0x00 /* Control Register */
19#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
20#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
21#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
22#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
23#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
24
25#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
26#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
27
28#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
29#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
30#define AT91_SSC_CKS_DIV (0 << 0)
31#define AT91_SSC_CKS_CLOCK (1 << 0)
32#define AT91_SSC_CKS_PIN (2 << 0)
33#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
34#define AT91_SSC_CKO_NONE (0 << 2)
35#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
36#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
37#define AT91_SSC_CKI_FALLING (0 << 5)
38#define AT91_SSC_CK_RISING (1 << 5)
39#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
40#define AT91_SSC_CKG_NONE (0 << 6)
41#define AT91_SSC_CKG_RFLOW (1 << 6)
42#define AT91_SSC_CKG_RFHIGH (2 << 6)
43#define AT91_SSC_START (0xf << 8) /* Start Selection */
44#define AT91_SSC_START_CONTINUOUS (0 << 8)
45#define AT91_SSC_START_TX_RX (1 << 8)
46#define AT91_SSC_START_LOW_RF (2 << 8)
47#define AT91_SSC_START_HIGH_RF (3 << 8)
48#define AT91_SSC_START_FALLING_RF (4 << 8)
49#define AT91_SSC_START_RISING_RF (5 << 8)
50#define AT91_SSC_START_LEVEL_RF (6 << 8)
51#define AT91_SSC_START_EDGE_RF (7 << 8)
52#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
53#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
54#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
55
56#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
57#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
58#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
59#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
60#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
61#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
62#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
63#define AT91_SSC_FSOS_NONE (0 << 20)
64#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
65#define AT91_SSC_FSOS_POSITIVE (2 << 20)
66#define AT91_SSC_FSOS_LOW (3 << 20)
67#define AT91_SSC_FSOS_HIGH (4 << 20)
68#define AT91_SSC_FSOS_TOGGLE (5 << 20)
69#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
70#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
71#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
72
73#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
74#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
75#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
76#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
77
78#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
79#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
80#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
81#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
82
83#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
84#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
85
86#define AT91_SSC_SR 0x40 /* Status Register */
87#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
88#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
89#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
90#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
91#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
92#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
93#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
94#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
95#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
96#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
97#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
98#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
99#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
100#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
101
102#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
103#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
104#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
105
106#endif
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
deleted file mode 100644
index 903bf205a333..000000000000
--- a/arch/arm/mach-at91/include/mach/entry-macro.S
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/entry-macro.S
3 *
4 * Copyright (C) 2003-2005 SAN People
5 *
6 * Low-level IRQ helper macros for AT91RM9200 platforms
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <mach/hardware.h>
14#include <mach/at91_aic.h>
15
16 .macro get_irqnr_preamble, base, tmp
17 ldr \base, =at91_aic_base @ base virtual address of AIC peripheral
18 ldr \base, [\base]
19 .endm
20
21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
22 ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
23 ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number
24 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
25 streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now.
26 .endm
27
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
deleted file mode 100644
index ac8b7dfc85ef..000000000000
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/irqs.h
3 *
4 * Copyright (C) 2004 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_IRQS_H
22#define __ASM_ARCH_IRQS_H
23
24#include <linux/io.h>
25#include <mach/at91_aic.h>
26
27#define NR_AIC_IRQS 32
28
29
30/*
31 * Acknowledge interrupt with AIC after interrupt has been handled.
32 * (by kernel/irq.c)
33 */
34#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0)
35
36
37/*
38 * IRQ interrupt symbols are the AT91xxx_ID_* symbols
39 * for IRQs handled directly through the AIC, or else the AT91_PIN_*
40 * symbols in gpio.h for ones handled indirectly as GPIOs.
41 * We make provision for 5 banks of GPIO.
42 */
43#define NR_IRQS (NR_AIC_IRQS + (5 * 32))
44
45/* FIQ is AIC source 0. */
46#define FIQ_START AT91_ID_FIQ
47
48#endif
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