diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h | 84 |
1 files changed, 42 insertions, 42 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h index c972d60e0aeb..b76e2ed2fbc2 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h | |||
| @@ -15,18 +15,18 @@ | |||
| 15 | #ifndef AT91SAM9G45_MATRIX_H | 15 | #ifndef AT91SAM9G45_MATRIX_H |
| 16 | #define AT91SAM9G45_MATRIX_H | 16 | #define AT91SAM9G45_MATRIX_H |
| 17 | 17 | ||
| 18 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | 18 | #define AT91_MATRIX_MCFG0 0x00 /* Master Configuration Register 0 */ |
| 19 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | 19 | #define AT91_MATRIX_MCFG1 0x04 /* Master Configuration Register 1 */ |
| 20 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | 20 | #define AT91_MATRIX_MCFG2 0x08 /* Master Configuration Register 2 */ |
| 21 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | 21 | #define AT91_MATRIX_MCFG3 0x0C /* Master Configuration Register 3 */ |
| 22 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | 22 | #define AT91_MATRIX_MCFG4 0x10 /* Master Configuration Register 4 */ |
| 23 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | 23 | #define AT91_MATRIX_MCFG5 0x14 /* Master Configuration Register 5 */ |
| 24 | #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ | 24 | #define AT91_MATRIX_MCFG6 0x18 /* Master Configuration Register 6 */ |
| 25 | #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ | 25 | #define AT91_MATRIX_MCFG7 0x1C /* Master Configuration Register 7 */ |
| 26 | #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ | 26 | #define AT91_MATRIX_MCFG8 0x20 /* Master Configuration Register 8 */ |
| 27 | #define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ | 27 | #define AT91_MATRIX_MCFG9 0x24 /* Master Configuration Register 9 */ |
| 28 | #define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ | 28 | #define AT91_MATRIX_MCFG10 0x28 /* Master Configuration Register 10 */ |
| 29 | #define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ | 29 | #define AT91_MATRIX_MCFG11 0x2C /* Master Configuration Register 11 */ |
| 30 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | 30 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ |
| 31 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | 31 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) |
| 32 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | 32 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) |
| @@ -37,14 +37,14 @@ | |||
| 37 | #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) | 37 | #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) |
| 38 | #define AT91_MATRIX_ULBT_128 (7 << 0) | 38 | #define AT91_MATRIX_ULBT_128 (7 << 0) |
| 39 | 39 | ||
| 40 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | 40 | #define AT91_MATRIX_SCFG0 0x40 /* Slave Configuration Register 0 */ |
| 41 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | 41 | #define AT91_MATRIX_SCFG1 0x44 /* Slave Configuration Register 1 */ |
| 42 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | 42 | #define AT91_MATRIX_SCFG2 0x48 /* Slave Configuration Register 2 */ |
| 43 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | 43 | #define AT91_MATRIX_SCFG3 0x4C /* Slave Configuration Register 3 */ |
| 44 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | 44 | #define AT91_MATRIX_SCFG4 0x50 /* Slave Configuration Register 4 */ |
| 45 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | 45 | #define AT91_MATRIX_SCFG5 0x54 /* Slave Configuration Register 5 */ |
| 46 | #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ | 46 | #define AT91_MATRIX_SCFG6 0x58 /* Slave Configuration Register 6 */ |
| 47 | #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ | 47 | #define AT91_MATRIX_SCFG7 0x5C /* Slave Configuration Register 7 */ |
| 48 | #define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | 48 | #define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
| 49 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | 49 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
| 50 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | 50 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
| @@ -52,22 +52,22 @@ | |||
| 52 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | 52 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
| 53 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | 53 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ |
| 54 | 54 | ||
| 55 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | 55 | #define AT91_MATRIX_PRAS0 0x80 /* Priority Register A for Slave 0 */ |
| 56 | #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ | 56 | #define AT91_MATRIX_PRBS0 0x84 /* Priority Register B for Slave 0 */ |
| 57 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | 57 | #define AT91_MATRIX_PRAS1 0x88 /* Priority Register A for Slave 1 */ |
| 58 | #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ | 58 | #define AT91_MATRIX_PRBS1 0x8C /* Priority Register B for Slave 1 */ |
| 59 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | 59 | #define AT91_MATRIX_PRAS2 0x90 /* Priority Register A for Slave 2 */ |
| 60 | #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ | 60 | #define AT91_MATRIX_PRBS2 0x94 /* Priority Register B for Slave 2 */ |
| 61 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | 61 | #define AT91_MATRIX_PRAS3 0x98 /* Priority Register A for Slave 3 */ |
| 62 | #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ | 62 | #define AT91_MATRIX_PRBS3 0x9C /* Priority Register B for Slave 3 */ |
| 63 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | 63 | #define AT91_MATRIX_PRAS4 0xA0 /* Priority Register A for Slave 4 */ |
| 64 | #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ | 64 | #define AT91_MATRIX_PRBS4 0xA4 /* Priority Register B for Slave 4 */ |
| 65 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | 65 | #define AT91_MATRIX_PRAS5 0xA8 /* Priority Register A for Slave 5 */ |
| 66 | #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ | 66 | #define AT91_MATRIX_PRBS5 0xAC /* Priority Register B for Slave 5 */ |
| 67 | #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ | 67 | #define AT91_MATRIX_PRAS6 0xB0 /* Priority Register A for Slave 6 */ |
| 68 | #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ | 68 | #define AT91_MATRIX_PRBS6 0xB4 /* Priority Register B for Slave 6 */ |
| 69 | #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ | 69 | #define AT91_MATRIX_PRAS7 0xB8 /* Priority Register A for Slave 7 */ |
| 70 | #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ | 70 | #define AT91_MATRIX_PRBS7 0xBC /* Priority Register B for Slave 7 */ |
| 71 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | 71 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ |
| 72 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | 72 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ |
| 73 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | 73 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ |
| @@ -81,7 +81,7 @@ | |||
| 81 | #define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ | 81 | #define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ |
| 82 | #define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ | 82 | #define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ |
| 83 | 83 | ||
| 84 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | 84 | #define AT91_MATRIX_MRCR 0x100 /* Master Remap Control Register */ |
| 85 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | 85 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
| 86 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | 86 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
| 87 | #define AT91_MATRIX_RCB2 (1 << 2) | 87 | #define AT91_MATRIX_RCB2 (1 << 2) |
| @@ -95,7 +95,7 @@ | |||
| 95 | #define AT91_MATRIX_RCB10 (1 << 10) | 95 | #define AT91_MATRIX_RCB10 (1 << 10) |
| 96 | #define AT91_MATRIX_RCB11 (1 << 11) | 96 | #define AT91_MATRIX_RCB11 (1 << 11) |
| 97 | 97 | ||
| 98 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ | 98 | #define AT91_MATRIX_TCMR 0x110 /* TCM Configuration Register */ |
| 99 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | 99 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
| 100 | #define AT91_MATRIX_ITCM_0 (0 << 0) | 100 | #define AT91_MATRIX_ITCM_0 (0 << 0) |
| 101 | #define AT91_MATRIX_ITCM_32 (6 << 0) | 101 | #define AT91_MATRIX_ITCM_32 (6 << 0) |
| @@ -107,12 +107,12 @@ | |||
| 107 | #define AT91_MATRIX_TCM_NO_WS (0x0 << 11) | 107 | #define AT91_MATRIX_TCM_NO_WS (0x0 << 11) |
| 108 | #define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) | 108 | #define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) |
| 109 | 109 | ||
| 110 | #define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ | 110 | #define AT91_MATRIX_VIDEO 0x118 /* Video Mode Configuration Register */ |
| 111 | #define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ | 111 | #define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ |
| 112 | #define AT91C_VDEC_SEL_OFF (0 << 0) | 112 | #define AT91C_VDEC_SEL_OFF (0 << 0) |
| 113 | #define AT91C_VDEC_SEL_ON (1 << 0) | 113 | #define AT91C_VDEC_SEL_ON (1 << 0) |
| 114 | 114 | ||
| 115 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ | 115 | #define AT91_MATRIX_EBICSA 0x128 /* EBI Chip Select Assignment Register */ |
| 116 | #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | 116 | #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
| 117 | #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) | 117 | #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) |
| 118 | #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) | 118 | #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) |
| @@ -138,13 +138,13 @@ | |||
| 138 | #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) | 138 | #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) |
| 139 | #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) | 139 | #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) |
| 140 | 140 | ||
| 141 | #define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ | 141 | #define AT91_MATRIX_WPMR 0x1E4 /* Write Protect Mode Register */ |
| 142 | #define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ | 142 | #define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ |
| 143 | #define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) | 143 | #define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) |
| 144 | #define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) | 144 | #define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) |
| 145 | #define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ | 145 | #define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ |
| 146 | 146 | ||
| 147 | #define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ | 147 | #define AT91_MATRIX_WPSR 0x1E8 /* Write Protect Status Register */ |
| 148 | #define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ | 148 | #define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ |
| 149 | #define AT91_MATRIX_WPSR_NO_WPV (0 << 0) | 149 | #define AT91_MATRIX_WPSR_NO_WPV (0 << 0) |
| 150 | #define AT91_MATRIX_WPSR_WPV (1 << 0) | 150 | #define AT91_MATRIX_WPSR_WPV (1 << 0) |