diff options
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91sam9261_matrix.h')
-rw-r--r-- | arch/arm/mach-at91/include/mach/at91sam9261_matrix.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h index 69c6501915d9..a50cdf8b8ca4 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h | |||
@@ -15,15 +15,15 @@ | |||
15 | #ifndef AT91SAM9261_MATRIX_H | 15 | #ifndef AT91SAM9261_MATRIX_H |
16 | #define AT91SAM9261_MATRIX_H | 16 | #define AT91SAM9261_MATRIX_H |
17 | 17 | ||
18 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ | 18 | #define AT91_MATRIX_MCFG 0x00 /* Master Configuration Register */ |
19 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | 19 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
20 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | 20 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
21 | 21 | ||
22 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ | 22 | #define AT91_MATRIX_SCFG0 0x04 /* Slave Configuration Register 0 */ |
23 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ | 23 | #define AT91_MATRIX_SCFG1 0x08 /* Slave Configuration Register 1 */ |
24 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ | 24 | #define AT91_MATRIX_SCFG2 0x0C /* Slave Configuration Register 2 */ |
25 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ | 25 | #define AT91_MATRIX_SCFG3 0x10 /* Slave Configuration Register 3 */ |
26 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ | 26 | #define AT91_MATRIX_SCFG4 0x14 /* Slave Configuration Register 4 */ |
27 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | 27 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ |
28 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | 28 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ |
29 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | 29 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) |
@@ -31,7 +31,7 @@ | |||
31 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | 31 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) |
32 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | 32 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ |
33 | 33 | ||
34 | #define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ | 34 | #define AT91_MATRIX_TCR 0x24 /* TCM Configuration Register */ |
35 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | 35 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ |
36 | #define AT91_MATRIX_ITCM_0 (0 << 0) | 36 | #define AT91_MATRIX_ITCM_0 (0 << 0) |
37 | #define AT91_MATRIX_ITCM_16 (5 << 0) | 37 | #define AT91_MATRIX_ITCM_16 (5 << 0) |
@@ -43,7 +43,7 @@ | |||
43 | #define AT91_MATRIX_DTCM_32 (6 << 4) | 43 | #define AT91_MATRIX_DTCM_32 (6 << 4) |
44 | #define AT91_MATRIX_DTCM_64 (7 << 4) | 44 | #define AT91_MATRIX_DTCM_64 (7 << 4) |
45 | 45 | ||
46 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ | 46 | #define AT91_MATRIX_EBICSA 0x30 /* EBI Chip Select Assignment Register */ |
47 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | 47 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ |
48 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | 48 | #define AT91_MATRIX_CS1A_SMC (0 << 1) |
49 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | 49 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) |
@@ -58,7 +58,7 @@ | |||
58 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | 58 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) |
59 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | 59 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ |
60 | 60 | ||
61 | #define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ | 61 | #define AT91_MATRIX_USBPUCR 0x34 /* USB Pad Pull-Up Control Register */ |
62 | #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ | 62 | #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ |
63 | 63 | ||
64 | #endif | 64 | #endif |