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-rw-r--r--arch/arm/mach-at91/gpio.c982
1 files changed, 0 insertions, 982 deletions
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
deleted file mode 100644
index d3f05aaad8ba..000000000000
--- a/arch/arm/mach-at91/gpio.c
+++ /dev/null
@@ -1,982 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk.h>
13#include <linux/errno.h>
14#include <linux/device.h>
15#include <linux/gpio.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/debugfs.h>
19#include <linux/seq_file.h>
20#include <linux/kernel.h>
21#include <linux/list.h>
22#include <linux/module.h>
23#include <linux/io.h>
24#include <linux/irqdomain.h>
25#include <linux/irqchip/chained_irq.h>
26#include <linux/of_address.h>
27
28#include <mach/hardware.h>
29#include <mach/at91_pio.h>
30
31#include "generic.h"
32#include "gpio.h"
33
34#define MAX_NB_GPIO_PER_BANK 32
35
36struct at91_gpio_chip {
37 struct gpio_chip chip;
38 struct at91_gpio_chip *next; /* Bank sharing same clock */
39 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
40 int pioc_virq; /* PIO bank Linux virtual interrupt */
41 int pioc_idx; /* PIO bank index */
42 void __iomem *regbase; /* PIO bank virtual address */
43 struct clk *clock; /* associated clock */
44 struct irq_domain *domain; /* associated irq domain */
45};
46
47#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
48
49static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
50static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
51static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
52static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
53static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset);
54static int at91_gpiolib_direction_output(struct gpio_chip *chip,
55 unsigned offset, int val);
56static int at91_gpiolib_direction_input(struct gpio_chip *chip,
57 unsigned offset);
58static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
59
60#define AT91_GPIO_CHIP(name) \
61 { \
62 .chip = { \
63 .label = name, \
64 .request = at91_gpiolib_request, \
65 .get_direction = at91_gpiolib_get_direction, \
66 .direction_input = at91_gpiolib_direction_input, \
67 .direction_output = at91_gpiolib_direction_output, \
68 .get = at91_gpiolib_get, \
69 .set = at91_gpiolib_set, \
70 .dbg_show = at91_gpiolib_dbg_show, \
71 .to_irq = at91_gpiolib_to_irq, \
72 .ngpio = MAX_NB_GPIO_PER_BANK, \
73 }, \
74 }
75
76static struct at91_gpio_chip gpio_chip[] = {
77 AT91_GPIO_CHIP("pioA"),
78 AT91_GPIO_CHIP("pioB"),
79 AT91_GPIO_CHIP("pioC"),
80 AT91_GPIO_CHIP("pioD"),
81 AT91_GPIO_CHIP("pioE"),
82};
83
84static int gpio_banks;
85static unsigned long at91_gpio_caps;
86
87/* All PIO controllers support PIO3 features */
88#define AT91_GPIO_CAP_PIO3 (1 << 0)
89
90#define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
91
92/*--------------------------------------------------------------------------*/
93
94static inline void __iomem *pin_to_controller(unsigned pin)
95{
96 pin /= MAX_NB_GPIO_PER_BANK;
97 if (likely(pin < gpio_banks))
98 return gpio_chip[pin].regbase;
99
100 return NULL;
101}
102
103static inline unsigned pin_to_mask(unsigned pin)
104{
105 return 1 << (pin % MAX_NB_GPIO_PER_BANK);
106}
107
108
109static char peripheral_function(void __iomem *pio, unsigned mask)
110{
111 char ret = 'X';
112 u8 select;
113
114 if (pio) {
115 if (has_pio3()) {
116 select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
117 select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
118 ret = 'A' + select;
119 } else {
120 ret = __raw_readl(pio + PIO_ABSR) & mask ?
121 'B' : 'A';
122 }
123 }
124
125 return ret;
126}
127
128/*--------------------------------------------------------------------------*/
129
130/* Not all hardware capabilities are exposed through these calls; they
131 * only encapsulate the most common features and modes. (So if you
132 * want to change signals in groups, do it directly.)
133 *
134 * Bootloaders will usually handle some of the pin multiplexing setup.
135 * The intent is certainly that by the time Linux is fully booted, all
136 * pins should have been fully initialized. These setup calls should
137 * only be used by board setup routines, or possibly in driver probe().
138 *
139 * For bootloaders doing all that setup, these calls could be inlined
140 * as NOPs so Linux won't duplicate any setup code
141 */
142
143
144/*
145 * mux the pin to the "GPIO" peripheral role.
146 */
147int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
148{
149 void __iomem *pio = pin_to_controller(pin);
150 unsigned mask = pin_to_mask(pin);
151
152 if (!pio)
153 return -EINVAL;
154 __raw_writel(mask, pio + PIO_IDR);
155 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
156 __raw_writel(mask, pio + PIO_PER);
157 return 0;
158}
159EXPORT_SYMBOL(at91_set_GPIO_periph);
160
161
162/*
163 * mux the pin to the "A" internal peripheral role.
164 */
165int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
166{
167 void __iomem *pio = pin_to_controller(pin);
168 unsigned mask = pin_to_mask(pin);
169
170 if (!pio)
171 return -EINVAL;
172
173 __raw_writel(mask, pio + PIO_IDR);
174 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
175 if (has_pio3()) {
176 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
177 pio + PIO_ABCDSR1);
178 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
179 pio + PIO_ABCDSR2);
180 } else {
181 __raw_writel(mask, pio + PIO_ASR);
182 }
183 __raw_writel(mask, pio + PIO_PDR);
184 return 0;
185}
186EXPORT_SYMBOL(at91_set_A_periph);
187
188
189/*
190 * mux the pin to the "B" internal peripheral role.
191 */
192int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
193{
194 void __iomem *pio = pin_to_controller(pin);
195 unsigned mask = pin_to_mask(pin);
196
197 if (!pio)
198 return -EINVAL;
199
200 __raw_writel(mask, pio + PIO_IDR);
201 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
202 if (has_pio3()) {
203 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
204 pio + PIO_ABCDSR1);
205 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
206 pio + PIO_ABCDSR2);
207 } else {
208 __raw_writel(mask, pio + PIO_BSR);
209 }
210 __raw_writel(mask, pio + PIO_PDR);
211 return 0;
212}
213EXPORT_SYMBOL(at91_set_B_periph);
214
215
216/*
217 * mux the pin to the "C" internal peripheral role.
218 */
219int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
220{
221 void __iomem *pio = pin_to_controller(pin);
222 unsigned mask = pin_to_mask(pin);
223
224 if (!pio || !has_pio3())
225 return -EINVAL;
226
227 __raw_writel(mask, pio + PIO_IDR);
228 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
229 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
230 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
231 __raw_writel(mask, pio + PIO_PDR);
232 return 0;
233}
234EXPORT_SYMBOL(at91_set_C_periph);
235
236
237/*
238 * mux the pin to the "D" internal peripheral role.
239 */
240int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
241{
242 void __iomem *pio = pin_to_controller(pin);
243 unsigned mask = pin_to_mask(pin);
244
245 if (!pio || !has_pio3())
246 return -EINVAL;
247
248 __raw_writel(mask, pio + PIO_IDR);
249 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
250 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
251 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
252 __raw_writel(mask, pio + PIO_PDR);
253 return 0;
254}
255EXPORT_SYMBOL(at91_set_D_periph);
256
257
258/*
259 * mux the pin to the gpio controller (instead of "A", "B", "C"
260 * or "D" peripheral), and configure it for an input.
261 */
262int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
263{
264 void __iomem *pio = pin_to_controller(pin);
265 unsigned mask = pin_to_mask(pin);
266
267 if (!pio)
268 return -EINVAL;
269
270 __raw_writel(mask, pio + PIO_IDR);
271 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
272 __raw_writel(mask, pio + PIO_ODR);
273 __raw_writel(mask, pio + PIO_PER);
274 return 0;
275}
276EXPORT_SYMBOL(at91_set_gpio_input);
277
278
279/*
280 * mux the pin to the gpio controller (instead of "A", "B", "C"
281 * or "D" peripheral), and configure it for an output.
282 */
283int __init_or_module at91_set_gpio_output(unsigned pin, int value)
284{
285 void __iomem *pio = pin_to_controller(pin);
286 unsigned mask = pin_to_mask(pin);
287
288 if (!pio)
289 return -EINVAL;
290
291 __raw_writel(mask, pio + PIO_IDR);
292 __raw_writel(mask, pio + PIO_PUDR);
293 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
294 __raw_writel(mask, pio + PIO_OER);
295 __raw_writel(mask, pio + PIO_PER);
296 return 0;
297}
298EXPORT_SYMBOL(at91_set_gpio_output);
299
300
301/*
302 * enable/disable the glitch filter; mostly used with IRQ handling.
303 */
304int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
305{
306 void __iomem *pio = pin_to_controller(pin);
307 unsigned mask = pin_to_mask(pin);
308
309 if (!pio)
310 return -EINVAL;
311
312 if (has_pio3() && is_on)
313 __raw_writel(mask, pio + PIO_IFSCDR);
314 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
315 return 0;
316}
317EXPORT_SYMBOL(at91_set_deglitch);
318
319/*
320 * enable/disable the debounce filter;
321 */
322int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
323{
324 void __iomem *pio = pin_to_controller(pin);
325 unsigned mask = pin_to_mask(pin);
326
327 if (!pio || !has_pio3())
328 return -EINVAL;
329
330 if (is_on) {
331 __raw_writel(mask, pio + PIO_IFSCER);
332 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
333 __raw_writel(mask, pio + PIO_IFER);
334 } else {
335 __raw_writel(mask, pio + PIO_IFDR);
336 }
337 return 0;
338}
339EXPORT_SYMBOL(at91_set_debounce);
340
341/*
342 * enable/disable the multi-driver; This is only valid for output and
343 * allows the output pin to run as an open collector output.
344 */
345int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
346{
347 void __iomem *pio = pin_to_controller(pin);
348 unsigned mask = pin_to_mask(pin);
349
350 if (!pio)
351 return -EINVAL;
352
353 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
354 return 0;
355}
356EXPORT_SYMBOL(at91_set_multi_drive);
357
358/*
359 * enable/disable the pull-down.
360 * If pull-up already enabled while calling the function, we disable it.
361 */
362int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
363{
364 void __iomem *pio = pin_to_controller(pin);
365 unsigned mask = pin_to_mask(pin);
366
367 if (!pio || !has_pio3())
368 return -EINVAL;
369
370 /* Disable pull-up anyway */
371 __raw_writel(mask, pio + PIO_PUDR);
372 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
373 return 0;
374}
375EXPORT_SYMBOL(at91_set_pulldown);
376
377/*
378 * disable Schmitt trigger
379 */
380int __init_or_module at91_disable_schmitt_trig(unsigned pin)
381{
382 void __iomem *pio = pin_to_controller(pin);
383 unsigned mask = pin_to_mask(pin);
384
385 if (!pio || !has_pio3())
386 return -EINVAL;
387
388 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
389 return 0;
390}
391EXPORT_SYMBOL(at91_disable_schmitt_trig);
392
393/*
394 * assuming the pin is muxed as a gpio output, set its value.
395 */
396int at91_set_gpio_value(unsigned pin, int value)
397{
398 void __iomem *pio = pin_to_controller(pin);
399 unsigned mask = pin_to_mask(pin);
400
401 if (!pio)
402 return -EINVAL;
403 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
404 return 0;
405}
406EXPORT_SYMBOL(at91_set_gpio_value);
407
408
409/*
410 * read the pin's value (works even if it's not muxed as a gpio).
411 */
412int at91_get_gpio_value(unsigned pin)
413{
414 void __iomem *pio = pin_to_controller(pin);
415 unsigned mask = pin_to_mask(pin);
416 u32 pdsr;
417
418 if (!pio)
419 return -EINVAL;
420 pdsr = __raw_readl(pio + PIO_PDSR);
421 return (pdsr & mask) != 0;
422}
423EXPORT_SYMBOL(at91_get_gpio_value);
424
425/*--------------------------------------------------------------------------*/
426
427#ifdef CONFIG_PM
428
429static u32 wakeups[MAX_GPIO_BANKS];
430static u32 backups[MAX_GPIO_BANKS];
431
432static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
433{
434 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
435 unsigned mask = 1 << d->hwirq;
436 unsigned bank = at91_gpio->pioc_idx;
437
438 if (unlikely(bank >= MAX_GPIO_BANKS))
439 return -EINVAL;
440
441 if (state)
442 wakeups[bank] |= mask;
443 else
444 wakeups[bank] &= ~mask;
445
446 irq_set_irq_wake(at91_gpio->pioc_virq, state);
447
448 return 0;
449}
450
451void at91_gpio_suspend(void)
452{
453 int i;
454
455 for (i = 0; i < gpio_banks; i++) {
456 void __iomem *pio = gpio_chip[i].regbase;
457
458 backups[i] = __raw_readl(pio + PIO_IMR);
459 __raw_writel(backups[i], pio + PIO_IDR);
460 __raw_writel(wakeups[i], pio + PIO_IER);
461
462 if (!wakeups[i]) {
463 clk_unprepare(gpio_chip[i].clock);
464 clk_disable(gpio_chip[i].clock);
465 } else {
466#ifdef CONFIG_PM_DEBUG
467 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
468#endif
469 }
470 }
471}
472
473void at91_gpio_resume(void)
474{
475 int i;
476
477 for (i = 0; i < gpio_banks; i++) {
478 void __iomem *pio = gpio_chip[i].regbase;
479
480 if (!wakeups[i]) {
481 if (clk_prepare(gpio_chip[i].clock) == 0)
482 clk_enable(gpio_chip[i].clock);
483 }
484
485 __raw_writel(wakeups[i], pio + PIO_IDR);
486 __raw_writel(backups[i], pio + PIO_IER);
487 }
488}
489
490#else
491#define gpio_irq_set_wake NULL
492#endif
493
494
495/* Several AIC controller irqs are dispatched through this GPIO handler.
496 * To use any AT91_PIN_* as an externally triggered IRQ, first call
497 * at91_set_gpio_input() then maybe enable its glitch filter.
498 * Then just request_irq() with the pin ID; it works like any ARM IRQ
499 * handler.
500 * First implementation always triggers on rising and falling edges
501 * whereas the newer PIO3 can be additionally configured to trigger on
502 * level, edge with any polarity.
503 *
504 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
505 * configuring them with at91_set_a_periph() or at91_set_b_periph().
506 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
507 */
508
509static void gpio_irq_mask(struct irq_data *d)
510{
511 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
512 void __iomem *pio = at91_gpio->regbase;
513 unsigned mask = 1 << d->hwirq;
514
515 if (pio)
516 __raw_writel(mask, pio + PIO_IDR);
517}
518
519static void gpio_irq_unmask(struct irq_data *d)
520{
521 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
522 void __iomem *pio = at91_gpio->regbase;
523 unsigned mask = 1 << d->hwirq;
524
525 if (pio)
526 __raw_writel(mask, pio + PIO_IER);
527}
528
529static int gpio_irq_type(struct irq_data *d, unsigned type)
530{
531 switch (type) {
532 case IRQ_TYPE_NONE:
533 case IRQ_TYPE_EDGE_BOTH:
534 return 0;
535 default:
536 return -EINVAL;
537 }
538}
539
540/* Alternate irq type for PIO3 support */
541static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
542{
543 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
544 void __iomem *pio = at91_gpio->regbase;
545 unsigned mask = 1 << d->hwirq;
546
547 switch (type) {
548 case IRQ_TYPE_EDGE_RISING:
549 __raw_writel(mask, pio + PIO_ESR);
550 __raw_writel(mask, pio + PIO_REHLSR);
551 break;
552 case IRQ_TYPE_EDGE_FALLING:
553 __raw_writel(mask, pio + PIO_ESR);
554 __raw_writel(mask, pio + PIO_FELLSR);
555 break;
556 case IRQ_TYPE_LEVEL_LOW:
557 __raw_writel(mask, pio + PIO_LSR);
558 __raw_writel(mask, pio + PIO_FELLSR);
559 break;
560 case IRQ_TYPE_LEVEL_HIGH:
561 __raw_writel(mask, pio + PIO_LSR);
562 __raw_writel(mask, pio + PIO_REHLSR);
563 break;
564 case IRQ_TYPE_EDGE_BOTH:
565 /*
566 * disable additional interrupt modes:
567 * fall back to default behavior
568 */
569 __raw_writel(mask, pio + PIO_AIMDR);
570 return 0;
571 case IRQ_TYPE_NONE:
572 default:
573 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
574 return -EINVAL;
575 }
576
577 /* enable additional interrupt modes */
578 __raw_writel(mask, pio + PIO_AIMER);
579
580 return 0;
581}
582
583static struct irq_chip gpio_irqchip = {
584 .name = "GPIO",
585 .irq_disable = gpio_irq_mask,
586 .irq_mask = gpio_irq_mask,
587 .irq_unmask = gpio_irq_unmask,
588 /* .irq_set_type is set dynamically */
589 .irq_set_wake = gpio_irq_set_wake,
590};
591
592static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
593{
594 struct irq_chip *chip = irq_desc_get_chip(desc);
595 struct irq_data *idata = irq_desc_get_irq_data(desc);
596 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
597 void __iomem *pio = at91_gpio->regbase;
598 unsigned long isr;
599 int n;
600
601 chained_irq_enter(chip, desc);
602 for (;;) {
603 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
604 * When there none are pending, we're finished unless we need
605 * to process multiple banks (like ID_PIOCDE on sam9263).
606 */
607 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
608 if (!isr) {
609 if (!at91_gpio->next)
610 break;
611 at91_gpio = at91_gpio->next;
612 pio = at91_gpio->regbase;
613 continue;
614 }
615
616 n = find_first_bit(&isr, BITS_PER_LONG);
617 while (n < BITS_PER_LONG) {
618 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
619 n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
620 }
621 }
622 chained_irq_exit(chip, desc);
623 /* now it may re-trigger */
624}
625
626/*--------------------------------------------------------------------------*/
627
628#ifdef CONFIG_DEBUG_FS
629
630static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
631{
632 char *trigger = NULL;
633 char *polarity = NULL;
634
635 if (__raw_readl(pio + PIO_IMR) & mask) {
636 if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
637 trigger = "edge";
638 polarity = "both";
639 } else {
640 if (__raw_readl(pio + PIO_ELSR) & mask) {
641 trigger = "level";
642 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
643 "high" : "low";
644 } else {
645 trigger = "edge";
646 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
647 "rising" : "falling";
648 }
649 }
650 seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
651 } else {
652 seq_printf(s, "GPIO:%s\t\t",
653 __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
654 }
655}
656
657static int at91_gpio_show(struct seq_file *s, void *unused)
658{
659 int bank, j;
660
661 /* print heading */
662 seq_printf(s, "Pin\t");
663 for (bank = 0; bank < gpio_banks; bank++) {
664 seq_printf(s, "PIO%c\t\t", 'A' + bank);
665 };
666 seq_printf(s, "\n\n");
667
668 /* print pin status */
669 for (j = 0; j < 32; j++) {
670 seq_printf(s, "%i:\t", j);
671
672 for (bank = 0; bank < gpio_banks; bank++) {
673 unsigned pin = (32 * bank) + j;
674 void __iomem *pio = pin_to_controller(pin);
675 unsigned mask = pin_to_mask(pin);
676
677 if (__raw_readl(pio + PIO_PSR) & mask)
678 gpio_printf(s, pio, mask);
679 else
680 seq_printf(s, "%c\t\t",
681 peripheral_function(pio, mask));
682 }
683
684 seq_printf(s, "\n");
685 }
686
687 return 0;
688}
689
690static int at91_gpio_open(struct inode *inode, struct file *file)
691{
692 return single_open(file, at91_gpio_show, NULL);
693}
694
695static const struct file_operations at91_gpio_operations = {
696 .open = at91_gpio_open,
697 .read = seq_read,
698 .llseek = seq_lseek,
699 .release = single_release,
700};
701
702static int __init at91_gpio_debugfs_init(void)
703{
704 /* /sys/kernel/debug/at91_gpio */
705 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
706 return 0;
707}
708postcore_initcall(at91_gpio_debugfs_init);
709
710#endif
711
712/*--------------------------------------------------------------------------*/
713
714/*
715 * This lock class tells lockdep that GPIO irqs are in a different
716 * category than their parents, so it won't report false recursion.
717 */
718static struct lock_class_key gpio_lock_class;
719
720/*
721 * irqdomain initialization: pile up irqdomains on top of AIC range
722 */
723static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
724{
725 int irq_base;
726
727 irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
728 if (irq_base < 0)
729 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
730 at91_gpio->pioc_idx, irq_base);
731 at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
732 irq_base, 0,
733 &irq_domain_simple_ops, NULL);
734 if (!at91_gpio->domain)
735 panic("at91_gpio.%d: couldn't allocate irq domain.\n",
736 at91_gpio->pioc_idx);
737}
738
739/*
740 * Called from the processor-specific init to enable GPIO interrupt support.
741 */
742void __init at91_gpio_irq_setup(void)
743{
744 unsigned pioc;
745 int gpio_irqnbr = 0;
746 struct at91_gpio_chip *this, *prev;
747
748 /* Setup proper .irq_set_type function */
749 if (has_pio3())
750 gpio_irqchip.irq_set_type = alt_gpio_irq_type;
751 else
752 gpio_irqchip.irq_set_type = gpio_irq_type;
753
754 for (pioc = 0, this = gpio_chip, prev = NULL;
755 pioc++ < gpio_banks;
756 prev = this, this++) {
757 int offset;
758
759 __raw_writel(~0, this->regbase + PIO_IDR);
760
761 /* setup irq domain for this GPIO controller */
762 at91_gpio_irqdomain(this);
763
764 for (offset = 0; offset < this->chip.ngpio; offset++) {
765 unsigned int virq = irq_find_mapping(this->domain, offset);
766 irq_set_lockdep_class(virq, &gpio_lock_class);
767
768 /*
769 * Can use the "simple" and not "edge" handler since it's
770 * shorter, and the AIC handles interrupts sanely.
771 */
772 irq_set_chip_and_handler(virq, &gpio_irqchip,
773 handle_simple_irq);
774 set_irq_flags(virq, IRQF_VALID);
775 irq_set_chip_data(virq, this);
776
777 gpio_irqnbr++;
778 }
779
780 /* The toplevel handler handles one bank of GPIOs, except
781 * on some SoC it can handles up to three...
782 * We only set up the handler for the first of the list.
783 */
784 if (prev && prev->next == this)
785 continue;
786
787 this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
788 irq_set_chip_data(this->pioc_virq, this);
789 irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
790 }
791 pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
792}
793
794/* gpiolib support */
795static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
796{
797 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
798 void __iomem *pio = at91_gpio->regbase;
799 unsigned mask = 1 << offset;
800
801 __raw_writel(mask, pio + PIO_PER);
802 return 0;
803}
804
805static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset)
806{
807 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
808 void __iomem *pio = at91_gpio->regbase;
809 unsigned mask = 1 << offset;
810 u32 osr;
811
812 osr = __raw_readl(pio + PIO_OSR);
813 return !(osr & mask);
814}
815
816static int at91_gpiolib_direction_input(struct gpio_chip *chip,
817 unsigned offset)
818{
819 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
820 void __iomem *pio = at91_gpio->regbase;
821 unsigned mask = 1 << offset;
822
823 __raw_writel(mask, pio + PIO_ODR);
824 return 0;
825}
826
827static int at91_gpiolib_direction_output(struct gpio_chip *chip,
828 unsigned offset, int val)
829{
830 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
831 void __iomem *pio = at91_gpio->regbase;
832 unsigned mask = 1 << offset;
833
834 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
835 __raw_writel(mask, pio + PIO_OER);
836 return 0;
837}
838
839static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
840{
841 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
842 void __iomem *pio = at91_gpio->regbase;
843 unsigned mask = 1 << offset;
844 u32 pdsr;
845
846 pdsr = __raw_readl(pio + PIO_PDSR);
847 return (pdsr & mask) != 0;
848}
849
850static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
851{
852 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
853 void __iomem *pio = at91_gpio->regbase;
854 unsigned mask = 1 << offset;
855
856 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
857}
858
859static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
860{
861 int i;
862
863 for (i = 0; i < chip->ngpio; i++) {
864 unsigned pin = chip->base + i;
865 void __iomem *pio = pin_to_controller(pin);
866 unsigned mask = pin_to_mask(pin);
867 const char *gpio_label;
868
869 gpio_label = gpiochip_is_requested(chip, i);
870 if (gpio_label) {
871 seq_printf(s, "[%s] GPIO%s%d: ",
872 gpio_label, chip->label, i);
873 if (__raw_readl(pio + PIO_PSR) & mask)
874 seq_printf(s, "[gpio] %s\n",
875 at91_get_gpio_value(pin) ?
876 "set" : "clear");
877 else
878 seq_printf(s, "[periph %c]\n",
879 peripheral_function(pio, mask));
880 }
881 }
882}
883
884static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
885{
886 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
887 int virq;
888
889 if (offset < chip->ngpio)
890 virq = irq_create_mapping(at91_gpio->domain, offset);
891 else
892 virq = -ENXIO;
893
894 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
895 chip->label, offset + chip->base, virq);
896 return virq;
897}
898
899static int __init at91_gpio_setup_clk(int idx)
900{
901 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
902
903 /* retreive PIO controller's clock */
904 at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
905 if (IS_ERR(at91_gpio->clock)) {
906 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
907 goto err;
908 }
909
910 if (clk_prepare(at91_gpio->clock))
911 goto clk_prep_err;
912
913 /* enable PIO controller's clock */
914 if (clk_enable(at91_gpio->clock)) {
915 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
916 goto clk_err;
917 }
918
919 return 0;
920
921clk_err:
922 clk_unprepare(at91_gpio->clock);
923clk_prep_err:
924 clk_put(at91_gpio->clock);
925err:
926 return -EINVAL;
927}
928
929static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
930{
931 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
932
933 at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
934 at91_gpio->pioc_hwirq = pioc_hwirq;
935 at91_gpio->pioc_idx = idx;
936
937 at91_gpio->regbase = ioremap(regbase, 512);
938 if (!at91_gpio->regbase) {
939 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
940 return;
941 }
942
943 if (at91_gpio_setup_clk(idx))
944 goto ioremap_err;
945
946 gpio_banks = max(gpio_banks, idx + 1);
947 return;
948
949ioremap_err:
950 iounmap(at91_gpio->regbase);
951}
952
953/*
954 * Called from the processor-specific init to enable GPIO pin support.
955 */
956void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
957{
958 unsigned i;
959 struct at91_gpio_chip *at91_gpio, *last = NULL;
960
961 BUG_ON(nr_banks > MAX_GPIO_BANKS);
962
963 if (of_have_populated_dt())
964 return;
965
966 for (i = 0; i < nr_banks; i++)
967 at91_gpio_init_one(i, data[i].regbase, data[i].id);
968
969 for (i = 0; i < gpio_banks; i++) {
970 at91_gpio = &gpio_chip[i];
971
972 /*
973 * GPIO controller are grouped on some SoC:
974 * PIOC, PIOD and PIOE can share the same IRQ line
975 */
976 if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
977 last->next = at91_gpio;
978 last = at91_gpio;
979
980 gpiochip_add(&at91_gpio->chip);
981 }
982}
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-30 19:57:01 -0400